ffirs.qxd 10/11/2007 9:07 AM Page i VLSI Circuit Design Methodology Demystified ffirs.qxd 10/11/2007 9:07 AM Page ii IEEE Press 445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Mohamed E. El-Hawary, Editor in Chief R. Abari T. Chen R. J. Herrick S. Basu T. G. Croda S. V. Kartalopoulos A. Chatterjee S. Farshchi M. S. Newman B. M. Hammerli Kenneth Moore, Director of IEEE Book and Information Services (BIS) Catherine Faduska, Senior Acquisitions Editor Jeanne Audino, Project Editor Technical Reviewers Poras T. Balsara, University of Texas at Dallas Peggy Ping Gui, Southern Methodist University Gabriele Manganaro, National Semiconductor Corp. Andrew Marshall, Texas Instruments, Inc. ffirs.qxd 10/11/2007 9:07 AM Page iii VLSI Circuit Design Methodology Demystified A Conceptual Taxonomy Liming Xiu IEEE PRESS WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC., PUBLICATION ffirs.qxd 10/11/2007 9:07 AM Page iv Copyright © 2008 by the Institute of Electrical and Electronics Engineers, Inc. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. All rights reserved. Published simultaneously in Canada. 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For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Wiley Bicentennial Logo: Richard J. Pacifico Library of Congress Cataloging-in-Publication Data is available. ISBN 978-0-470-12742-1 Printed in the United States of America. 10987654321 ffirs.qxd 10/11/2007 9:07 AM Page v To my wife, Zhihong, my daughters, Katherine and Helen, and my parents, Zunxin and Zhengfeng ftoc.qxd 10/11/2007 9:08 AM Page vii Contents Foreword xi Richard Templeton Foreword xiii Hans Stork Preface xv Acknowledgments xvii CHAPTER 1 THE BIG PICTURE 1 1. What is a chip? 1 2. What are the requirements of a successful chip design? 3 3. What are the challenges in today’s very deep submicron 4 (VDSM), multimillion gate designs? 4. What major process technologies are used in today’s design 5 environment? 5. What are the goals of new chip design? 8 6. What are the major approaches of today’s very large scale 9 integration (VLSI) circuit design practices? 7. What is standard cell-based, application-specific integrated 11 circuit (ASIC) design methodology? 8. What is the system-on-chip (SoC) approach? 12 9. What are the driving forces behind the SoC trend? 15 10. What are the major tasks in developing a SoC chip from 15 concept to silicon? 11. What are the major costs of developing a chip? 16 CHAPTER 2 THE BASICS OF THE CMOS PROCESS 17 AND DEVICES 12. What are the major process steps in building MOSFET 17 transistors? vii ftoc.qxd 10/11/2007 9:08 AM Page viii viii CONTENTS 13. What are the two types of MOSFET transistors? 19 14. What are base layers and metal layers? 20 15. What are wafers and dies? 24 16. What is semiconductor lithography? 28 17. What is a package? 33 CHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41 18. What is the role of functional verification in the IC 41 design process? 19. What are some of the design integrity issues? 44 20. What is design for testability? 46 21. Why is reducing the chip’s power consumption so important? 48 22. What are some of the challenges in chip packaging? 49 23. What are the advantages of design reuse? 50 24. What is hardware/software co-design? 51 25. Why is the clock so important? 54 26. What is the leakage current problem? 57 27. What is design for manufacturability? 60 28. What is chip reliability? 62 29. What is analog integration in the digital environment? 65 30. What is the role of EDA tools in IC design? 67 31. What is the role of the embedded processor in the SoC 69 environment? CHAPTER 4 CELL-BASED ASIC DESIGN METHODOLOGY 73 32. What are the major tasks and personnel required in a chip 73 design project? 33. What are the major steps in ASIC chip construction? 74 34. What is the ASIC design flow? 75 35. What are the two major aspects of ASIC design flow? 77 36. What are the characteristics of good design flow? 80 37. What is the role of market research in an ASIC project? 81 38. What is the optimal solution of an ASIC project? 82 39. What is system-level study of a project? 84 40. What are the approaches for verifying design at the 85 system level? 41. What is register-transfer-level (RTL) system-level description? 86 42. What are methods of verifying design at the register-transfer- 87 level? 43. What is a test bench? 88 44. What is code coverage? 89 ftoc.qxd 10/11/2007 9:08 AM Page ix CONTENTS ix 45. What is functional coverage? 89 46. What is bug rate convergence? 90 47. What is design planning? 91 48. What are hard macro and soft macro? 92 49. What is hardware description language (HDL)? 92 50. What is register-transfer-level (RTL) description of hardware? 93 51. What is standard cell? What are the differences among standard 94 cell, gate-array, and sea-of-gate approaches? 52. What is an ASIC library? 103 53. What is logic synthesis? 105 54. What are the optimization targets of logic synthesis? 106 55. What is schematic or netlist? 107 56. What is the gate count of a design? 111 57. What is the purpose of test insertion during logic synthesis? 111 58. What is the most commonly used model in VLSI circuit testing? 112 59. What are controllability and observability in a digital circuit? 114 60. What is a testable circuit? 115 61. What is the aim of scan insertion? 116 62. What is fault coverage? What is defect part per million (DPPM)? 117 63. Why is design for testability important for a product’s 119 financial success? 64. What is chip power usage analysis? 120 65. What are the major components of CMOS power consumption? 121 66. What is power optimization? 123 67. What is VLSI physical design? 123 68. What are the problems that make VLSI physical design so 124 challenging? 69. What is floorplanning? 128 70. What is the placement process? 131 71. What is the routing process? 133 72. What is a power network? 135 73. What is clock distribution? 139 74. What are the key requirements for constructing a clock tree? 143 75. What is the difference between time skew and length skew in a 145 clock tree? 76. What is scan chain? 149 77. What is scan chain reordering? 151 78. What is parasitic extraction? 152 79. What is delay calculation? 155 80. What is back annotation? 156 81. What kind of signal integrity problems do place and route 156 ftoc.qxd 10/11/2007 9:08 AM Page x x CONTENTS tools handle? 82. What is cross-talk delay? 157 83. What is cross-talk noise? 158 84. What is IR drop? 159 85. What are the major netlist formats for design representation? 162 86. What is gate-level logic verification before tapeout? 162 87. What is equivalence check? 163 88. What is timing verification? 164 89. What is design constraint? 165 90. What is static timing analysis (STA)? 165 91. What is simulation approach on timing verification? 169 92. What is the logical-effort-based timing closure approach? 173 93. What is physical verification? 178 94. What are design rule check (DRC), design verification (DV), 179 and geometry verification (GV)? 95. What is schematic verification (SV) or layout versus 181 schematic (LVS)? 96. What is automatic test pattern generation (ATPG)? 182 97. What is tapeout? 184 98. What is yield? 184 99. What are the qualities of a good IC implementation designer? 187 Conclusion 189 Acronyms 191 Bibliography 195 Index 199 fbetw.qxd 10/11/2007 9:10 AM Page xi Foreword Richard Templeton President and CEO Texas Instruments, Inc.