HPC Performance Profiling Using Intel Vtune Amplifier XE
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Intel Advisor for Dgpu Intel® Advisor Workflows
Profile DPC++ and GPU workload performance Intel® VTune™ Profiler, Advisor Vladimir Tsymbal, Technical Consulting Engineer, Intel, IAGS Agenda • Introduction to GPU programming model • Overview of GPU Analysis in Intel® VTune Profiler • Offload Performance Tuning • GPU Compute/Media Hotspots • A DPC++ Code Sample Analysis Demo • Using Intel® Advisor to increase performance • Offload Advisor discrete GPUs • GPU Roofline for discrete GPUs Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 2 Intel GPUs and Programming Model Gen9 Application Workloads • Most common Optimized Middleware & Frameworks in mobile, desktop and Intel oneAPI Product workstations Intel® Media SDK Direct Direct API-Based Gen11 Programming Programming Programming • Data Parallel Mobile OpenCL platforms with C API C++ Libraries Ice Lake CPU Gen12 Low-Level Hardware Interface • Intel Xe-LP GPU • Tiger Lake CPU Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 3 GPU Application Analysis GPU Compute/Media Hotspots • Visibility into both host and GPU sides • HW-events based performance tuning methodology • Provides overtime and aggregated views GPU In-kernel Profiling • GPU source/instruction level profiling • SW instrumentation • Two modes: Basic Block latency and memory access latency Identify GPU occupancy and which kernel to profile. Tune a kernel on a fine grain level Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 4 GPU Analysis: Aggregated and Overtime Views Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. -
Getting Started with Oneapi
ONEAPI SINGLE PROGRAMMING MODEL TO DELIVER CROSS-ARCHITECTURE PERFORMANCE Getting started with oneAPI March 2020 How oneAPIaddresses our Heterogeneous World? DIVERSE WORKLOADS DEMAND DIVERSEARCHITECTURES The future is a diverse mix of scalar, vector, matrix, andspatial architectures deployed in CPU, GPU, AI, FPGA, and other accelerators. Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 4 *Other names and brands may be claimed as the property of others. CHALLENGE: PROGRAMMING IN A HETEROGENEOUSWORLD ▷ Diverse set of data-centric hardware ▷ No common programming language or APIs ▷ Inconsistent tool support across platforms ▷ Proprietary solutions on individual platforms S V M S ▷ Each platform requires unique software investment Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 5 *Other names and brands may be claimed as the property of others. INTEL'S ONEAPI CORECONCEPT ▷ Project oneAPI delivers a unified programming model to simplify development across diverse architectures ▷ Common developer experience across SVMS ▷ Uncompromised native high-level language performance ▷ Support for CPU, GPU, AI, and FPGA ▷ Unified language and libraries for ▷ Based on industry standards and expressing parallelism open specifications https://www.oneapi.com/spec/ Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 6 *Other names and brands may be claimed as the property of others. ONEAPI FOR CROSS-ARCHITECTUREPERFORMANCE Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 7 *Other names and brands may be claimed as the property of others. WHAT IS DATA PARALLELC++? WHAT ISDPC++? The language is: C++ + SYCL https://www.khronos.org/sycl/ + Additional Features such as.. -
Michael Steyer Technical Consulting Engineer Intel Architecture, Graphics & Software Analysis Tools
Michael Steyer Technical Consulting Engineer Intel Architecture, Graphics & Software Analysis Tools Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Aspects of HPC/Throughput Application Performance What are the Aspects of Performance Intel Hardware Features Multi-core Intel® Omni Intel® Optane™ Intel® Advanced Intel® Path HBM DC persistent Vector Xeon® Extensions 512 Architecture memory (Intel® AVX-512) processor Distributed memory Memory I/O Threading CPU Core Message size False Sharing File I/O Threaded/serial ratio uArch issues (IPC) Rank placement Access with strides I/O latency Thread Imbalance Vectorization Rank Imbalance Latency I/O waits RTL overhead FPU usage efficiency RTL Overhead Bandwidth System-wide I/O (scheduling, forking) Network Bandwidth NUMA Synchronization Cluster Node Core Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. IntelWhat Parallel are the Studio Aspects Tools covering of Performance the Aspects Intel Hardware Features Multi-core Intel® Intel® Omni Intel® Optane™ Advanced Intel®Path DC persistent Intel® Vector HBM Extensions Architectur Intel® VTune™memory AmplifierXeon® processor 512 (Intel® Tracee Intel®AVX-512) DistributedAnalyzer memory Memory I/O Threading AdvisorCPU Core Messageand size False Sharing File I/O Threaded/serial ratio uArch issues (IPC) Rank placement Access with strides I/O latency Thread Imbalance Vectorization RankCollector Imbalance Latency I/O waits RTL overhead FPU usage efficiency RTL Overhead Bandwidth System-wide I/O (scheduling, forking) Network Bandwidth NUMA Synchronization Cluster Node Core Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. -
Intel® Software Products Highlights and Best Practices
Intel® Software Products Highlights and Best Practices Edmund Preiss Business Development Manager Entdecken Sie weitere interessante Artikel und News zum Thema auf all-electronics.de! Hier klicken & informieren! Agenda • Key enhancements and highlights since ISTEP’11 • Industry segments using Intel® Software Development Products • Customer Demo and Best Practices Copyright© 2012, Intel Corporation. All rights reserved. 2 *Other brands and names are the property of their respective owners. Key enhancements & highlights since ISTEP’11 3 All in One -- Intel® Cluster Studio XE 2012 Analysis & Correctness Tools Shared & Distributed Memory Application Development Intel Cluster Studio XE supports: -Shared Memory Processing MPI Libraries & Tools -Distributed Memory Processing Compilers & Libraries Programming Models -Hybrid Processing Copyright© 2012, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Intel® VTune™ Amplifier XE New VTune Amplifier XE features very well received by Software Developers Key reasons : • More intuitive – Improved GUI points to application inefficiencies • Preconfigured & customizable analysis profiles • Timeline View highlights concurrency issues • New Event/PC counter ratio analysis concept easy to grasp Copyright© 2012, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Intel® VTune™ Amplifier XE The Old Way versus The New Way The Old Way: To see if there is an issue with branch misprediction, multiply event value (86,400,000) by 14 cycles, then divide by CPU_CLK_UNHALTED.THREAD (5,214,000,000). Then compare the resulting value to a threshold. If it is too high, investigate. The New Way: Look at the Branch Mispredict metric, and see if any cells are pink. -
Linux Kernel and Driver Development Training Slides
Linux Kernel and Driver Development Training Linux Kernel and Driver Development Training © Copyright 2004-2021, Bootlin. Creative Commons BY-SA 3.0 license. Latest update: October 9, 2021. Document updates and sources: https://bootlin.com/doc/training/linux-kernel Corrections, suggestions, contributions and translations are welcome! embedded Linux and kernel engineering Send them to [email protected] - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 1/470 Rights to copy © Copyright 2004-2021, Bootlin License: Creative Commons Attribution - Share Alike 3.0 https://creativecommons.org/licenses/by-sa/3.0/legalcode You are free: I to copy, distribute, display, and perform the work I to make derivative works I to make commercial use of the work Under the following conditions: I Attribution. You must give the original author credit. I Share Alike. If you alter, transform, or build upon this work, you may distribute the resulting work only under a license identical to this one. I For any reuse or distribution, you must make clear to others the license terms of this work. I Any of these conditions can be waived if you get permission from the copyright holder. Your fair use and other rights are in no way affected by the above. Document sources: https://github.com/bootlin/training-materials/ - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 2/470 Hyperlinks in the document There are many hyperlinks in the document I Regular hyperlinks: https://kernel.org/ I Kernel documentation links: dev-tools/kasan I Links to kernel source files and directories: drivers/input/ include/linux/fb.h I Links to the declarations, definitions and instances of kernel symbols (functions, types, data, structures): platform_get_irq() GFP_KERNEL struct file_operations - Kernel, drivers and embedded Linux - Development, consulting, training and support - https://bootlin.com 3/470 Company at a glance I Engineering company created in 2004, named ”Free Electrons” until Feb. -
Tips and Tricks: Designing Low Power Native and Webapps
Tips and Tricks: Designing low power Native and WebApps Harita Chilukuri and Abhishek Dhanotia Acknowledgements • William Baughman for his help with the browser analysis • Ross Burton & Thomas Wood for information on Tizen Architecture • Tom Baker, Luis “Fernando” Recalde, Raji Shunmuganathan and Yamini Nimmagadda for reviews and comments 2 tizen.org Power – Onus lies on Software too! Use system resources to provide best User WEBAPPS Experience with minimum power NATIVE APPS RUNTIME Interfaces with HW components, DRIVERS / MIDDLEWARE Independent device power management Frequency Governors, CPU Power OS Management ACPI/RTPM Provides features for low power HARDWARE Clock Gating, Power Gating, Sleep States 3 tizen.org Power – Onus lies on Software too! • A single bad application can lead to exceeding power budget • Hardware and OS provide many features for low power – Apps need to use them smartly to improve power efficiency • Good understanding of underlying system can help in designing better apps Images are properties of their respective owners 4 tizen.org Agenda Tips for Power Tools General Low Power Q&A & Metrics guidelines Applications 5 tizen.org Estimating Power - Metrics • CPU utilization • Memory bandwidth • CPU C and P state residencies • Device D states - For non-CPU components • S states – system sleep states • Wakeups, interrupts Soft metrics can help tune the application for optimal power 6 tizen.org Estimating Power - Tools • CPU utilization – Vmstat, Top – VTune, Perf for CPU cycles • Memory bandwidth – Vtune • CPU C and P states, Device D states – VTune, Powertop • Wakeups, Interrupts, Timers – Powertop, /proc stats • Tracing tool in Chrome browser ** VTune is an Intel product and can be purchased, others are publicly available Linux tools * Other names and brands may be claimed as the property of others. -
Dr. Fabio Baruffa Senior Technical Consulting Engineer, Intel IAGS Legal Disclaimer & Optimization Notice
Dr. Fabio Baruffa Senior Technical Consulting Engineer, Intel IAGS Legal Disclaimer & Optimization Notice Performance results are based on testing as of September 2018 and may not reflect all publicly available security updates. See configuration disclosure for details. No product can be absolutely secure. Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. INFORMATION IN THIS DOCUMENT IS PROVIDED “AS IS”. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Copyright © 2019, Intel Corporation. All rights reserved. Intel, the Intel logo, Pentium, Xeon, Core, VTune, OpenVINO, Cilk, are trademarks of Intel Corporation or its subsidiaries in the U.S. and other countries. Optimization Notice Intel’s compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. -
2019-11-20 Intel Profiling Tools
Profiling Using the Intel Performance Profilers Ryan Honeyager November 21, 2019 JEDI Topic Discussion Meeting Intel-Provided Tools • Intel Advisor – Helps optimize programs to use vectorization and shared-memory threading. • Intel Inspector – A memory and thread checking and debugging tool. • Intel VTune Amplifier (Profiler) – Performs many kinds of code profiling. • Only discussing VTune Amplifier today • All tools are free and can be downloaded from Intel’s website. • They all work with C++ and Fortran, support MPI, and work with GCC, Intel compilers, Clang. No special compiler options needed beyond building in Debug and RelWithDebInfo modes. • All are installed on Hera already (module load vtune inspector advisor). VTune Amplifier (soon to be renamed VTune Profiler) • Performs many kinds of code profiling: • Examine code hotspots by CPU utilization • Threading / MPI efficiency • Memory consumption • Can profile using either CPU instructions (mostly Intel processors) or with software emulation. Defaults to polling every 10 ms. • Profiling cost varies – hotspot analysis is <5-10%, memory consumption analysis is 2-5x. • Has both GUI and console interfaces. Supports remote profiling via SSH, and can also save / load profiling results for future analysis. Example: See https://github.com/JCSDA/oops/pull/442. Reduced execution time of test by 45% (1.68 to 0.93 seconds) by rewriting ten lines of code. Console-based usage • amplxe-cl –collect hotspots –result-dir out –quiet -- your_app_here.x arg1 arg2 … • If –quiet is not specified, a summary report is printed to the console. • The results directory is around 5-10 MB per unit test. Can be transferred between computers. • Not restricted to profiling an application. -
Intel® Embedded Software Development Tool Suite for Intel® Atom™ Processor
Intel® Embedded Software Development Tool Suite For Intel® Atom™ processor Turbocharge your code for Intel® Atom™ processor-based Product Brief embedded systems Intel® Embedded Software High Performance Data, Media and Signal Powerful Application and JTAG-based Development Tool Suite Processing Libraries Debug for Intel® Atom™ processor High Performance C/C++ Compiler Advanced Performance Analysis Tool Benefit from a comprehensive software development tools solution for your Intel® Atom™ processor- based embedded system designs and application software development. Coding, compiling, debugging and performance tuning made simple. The Intel® Embedded Software Development Tool Suite for Intel® Atom™ processor is a complete solution that addresses embedded software development requirements for Intel® Atom™ processor- powered platforms such as embedded systems, tablets, netbooks, smartphones, IVI and other CE devices. The Embedded Software Development Tool Suite covers the entire software development cycle: coding, compiling, debugging, and analyzing performance. All included tools are Linux* hosted, are compatible with GNU tools, and support multiple Linux* OS based targets. Intel® C++ Compiler for Linux* Intel® Integrated Performance Primitives for Linux* Intel® Application Debugger for Intel® Atom™ processor Intel® JTAG Debugger for Intel® Atom™ processor Intel® VTune™ Amplifier XE for Linux* Compatibility and support for Linux* based targets e.g. Yocto Project* Features and Benefits Feature Benefits Intel® C++ Compiler Boost -
Pin Tutorial What Is Instrumentation?
Pin Tutorial What is Instrumentation? A technique that inserts extra code into a program to collect runtime information Instrumentation approaches: • Source instrumentation: – Instrument source programs • Binary instrumentation: – Instrument executables directly 1 Pin Tutorial 2007 Why use Dynamic Instrumentation? No need to recompile or relink Discover code at runtime Handle dynamically-generated code Attach to running processes 2 Pin Tutorial 2007 Advantages of Pin Instrumentation Easy-to-use Instrumentation: • Uses dynamic instrumentation – Do not need source code, recompilation, post-linking Programmable Instrumentation: • Provides rich APIs to write in C/C++ your own instrumentation tools (called Pintools) Multiplatform: • Supports x86, x86-64, Itanium, Xscale • Supports Linux, Windows, MacOS Robust: • Instruments real-life applications: Database, web browsers, … • Instruments multithreaded applications • Supports signals Efficient: • Applies compiler optimizations on instrumentation code 3 Pin Tutorial 2007 Using Pin Launch and instrument an application $ pin –t pintool –- application Instrumentation engine Instrumentation tool (provided in the kit) (write your own, or use one provided in the kit) Attach to and instrument an application $ pin –t pintool –pid 1234 4 Pin Tutorial 2007 Pin Instrumentation APIs Basic APIs are architecture independent: • Provide common functionalities like determining: – Control-flow changes – Memory accesses Architecture-specific APIs • e.g., Info about segmentation registers on IA32 Call-based APIs: -
Intel Threading Building Blocks
Praise for Intel Threading Building Blocks “The Age of Serial Computing is over. With the advent of multi-core processors, parallel- computing technology that was once relegated to universities and research labs is now emerging as mainstream. Intel Threading Building Blocks updates and greatly expands the ‘work-stealing’ technology pioneered by the MIT Cilk system of 15 years ago, providing a modern industrial-strength C++ library for concurrent programming. “Not only does this book offer an excellent introduction to the library, it furnishes novices and experts alike with a clear and accessible discussion of the complexities of concurrency.” — Charles E. Leiserson, MIT Computer Science and Artificial Intelligence Laboratory “We used to say make it right, then make it fast. We can’t do that anymore. TBB lets us design for correctness and speed up front for Maya. This book shows you how to extract the most benefit from using TBB in your code.” — Martin Watt, Senior Software Engineer, Autodesk “TBB promises to change how parallel programming is done in C++. This book will be extremely useful to any C++ programmer. With this book, James achieves two important goals: • Presents an excellent introduction to parallel programming, illustrating the most com- mon parallel programming patterns and the forces governing their use. • Documents the Threading Building Blocks C++ library—a library that provides generic algorithms for these patterns. “TBB incorporates many of the best ideas that researchers in object-oriented parallel computing developed in the last two decades.” — Marc Snir, Head of the Computer Science Department, University of Illinois at Urbana-Champaign “This book was my first introduction to Intel Threading Building Blocks. -
In-Memory Protocol Fuzz Testing Using the Pin Toolkit
In-Memory Protocol Fuzz Testing using the Pin Toolkit BACHELOR’S THESIS submitted in partial fulfillment of the requirements for the degree of Bachelor of Science in Computer Engineering by Patrik Fimml Registration Number 1027027 to the Faculty of Informatics at the Vienna University of Technology Advisor: Dipl.-Ing. Markus Kammerstetter Vienna, 5th March, 2015 Patrik Fimml Markus Kammerstetter Technische Universität Wien A-1040 Wien Karlsplatz 13 Tel. +43-1-58801-0 www.tuwien.ac.at Erklärung zur Verfassung der Arbeit Patrik Fimml Kaiserstraße 92 1070 Wien Hiermit erkläre ich, dass ich diese Arbeit selbständig verfasst habe, dass ich die verwen- deten Quellen und Hilfsmittel vollständig angegeben habe und dass ich die Stellen der Arbeit – einschließlich Tabellen, Karten und Abbildungen –, die anderen Werken oder dem Internet im Wortlaut oder dem Sinn nach entnommen sind, auf jeden Fall unter Angabe der Quelle als Entlehnung kenntlich gemacht habe. Wien, 5. März 2015 Patrik Fimml iii Abstract In this Bachelor’s thesis, we explore in-memory fuzz testing of TCP server binaries. We use the Pin instrumentation framework to inject faults directly into application buffers and take snapshots of the program state. On a simple testing binary, this results in a 2.7× speedup compared to a naive fuzz testing implementation. To evaluate our implementation, we apply it to a VNC server binary as an example for a real-world application. We describe obstacles that we had to tackle during development and point out limitations of our approach. v Contents Abstract v Contents vii 1 Introduction 1 2 Fuzz Testing 3 2.1 Naive Protocol Fuzz Testing .