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Intel Advisor for Dgpu Intel® Advisor Workflows
Profile DPC++ and GPU workload performance Intel® VTune™ Profiler, Advisor Vladimir Tsymbal, Technical Consulting Engineer, Intel, IAGS Agenda • Introduction to GPU programming model • Overview of GPU Analysis in Intel® VTune Profiler • Offload Performance Tuning • GPU Compute/Media Hotspots • A DPC++ Code Sample Analysis Demo • Using Intel® Advisor to increase performance • Offload Advisor discrete GPUs • GPU Roofline for discrete GPUs Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 2 Intel GPUs and Programming Model Gen9 Application Workloads • Most common Optimized Middleware & Frameworks in mobile, desktop and Intel oneAPI Product workstations Intel® Media SDK Direct Direct API-Based Gen11 Programming Programming Programming • Data Parallel Mobile OpenCL platforms with C API C++ Libraries Ice Lake CPU Gen12 Low-Level Hardware Interface • Intel Xe-LP GPU • Tiger Lake CPU Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 3 GPU Application Analysis GPU Compute/Media Hotspots • Visibility into both host and GPU sides • HW-events based performance tuning methodology • Provides overtime and aggregated views GPU In-kernel Profiling • GPU source/instruction level profiling • SW instrumentation • Two modes: Basic Block latency and memory access latency Identify GPU occupancy and which kernel to profile. Tune a kernel on a fine grain level Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. 4 GPU Analysis: Aggregated and Overtime Views Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. -
SOL: Effortless Device Support for AI Frameworks Without Source Code Changes
SOL: Effortless Device Support for AI Frameworks without Source Code Changes Nicolas Weber and Felipe Huici NEC Laboratories Europe Abstract—Modern high performance computing clusters heav- State of the Art Proposed with SOL ily rely on accelerators to overcome the limited compute power API (Python, C/C++, …) API (Python, C/C++, …) of CPUs. These supercomputers run various applications from different domains such as simulations, numerical applications or Framework Core Framework Core artificial intelligence (AI). As a result, vendors need to be able to Device Backends SOL efficiently run a wide variety of workloads on their hardware. In the AI domain this is in particular exacerbated by the Fig. 1: Abstraction layers within AI frameworks. existance of a number of popular frameworks (e.g, PyTorch, TensorFlow, etc.) that have no common code base, and can vary lines of code to their scripts in order to enable SOL and its in functionality. The code of these frameworks evolves quickly, hardware support. making it expensive to keep up with all changes and potentially We explore two strategies to integrate new devices into AI forcing developers to go through constant rounds of upstreaming. frameworks using SOL as a middleware, to keep the original In this paper we explore how to provide hardware support in AI frameworks without changing the framework’s source code in AI framework unchanged and still add support to new device order to minimize maintenance overhead. We introduce SOL, an types. The first strategy hides the entire offloading procedure AI acceleration middleware that provides a hardware abstraction from the framework, and the second only injects the necessary layer that allows us to transparently support heterogenous hard- functionality into the framework to enable the execution, but ware. -
Getting Started with Oneapi
ONEAPI SINGLE PROGRAMMING MODEL TO DELIVER CROSS-ARCHITECTURE PERFORMANCE Getting started with oneAPI March 2020 How oneAPIaddresses our Heterogeneous World? DIVERSE WORKLOADS DEMAND DIVERSEARCHITECTURES The future is a diverse mix of scalar, vector, matrix, andspatial architectures deployed in CPU, GPU, AI, FPGA, and other accelerators. Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 4 *Other names and brands may be claimed as the property of others. CHALLENGE: PROGRAMMING IN A HETEROGENEOUSWORLD ▷ Diverse set of data-centric hardware ▷ No common programming language or APIs ▷ Inconsistent tool support across platforms ▷ Proprietary solutions on individual platforms S V M S ▷ Each platform requires unique software investment Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 5 *Other names and brands may be claimed as the property of others. INTEL'S ONEAPI CORECONCEPT ▷ Project oneAPI delivers a unified programming model to simplify development across diverse architectures ▷ Common developer experience across SVMS ▷ Uncompromised native high-level language performance ▷ Support for CPU, GPU, AI, and FPGA ▷ Unified language and libraries for ▷ Based on industry standards and expressing parallelism open specifications https://www.oneapi.com/spec/ Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 6 *Other names and brands may be claimed as the property of others. ONEAPI FOR CROSS-ARCHITECTUREPERFORMANCE Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. Getting started withoneAPI 7 *Other names and brands may be claimed as the property of others. WHAT IS DATA PARALLELC++? WHAT ISDPC++? The language is: C++ + SYCL https://www.khronos.org/sycl/ + Additional Features such as.. -
Michael Steyer Technical Consulting Engineer Intel Architecture, Graphics & Software Analysis Tools
Michael Steyer Technical Consulting Engineer Intel Architecture, Graphics & Software Analysis Tools Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Aspects of HPC/Throughput Application Performance What are the Aspects of Performance Intel Hardware Features Multi-core Intel® Omni Intel® Optane™ Intel® Advanced Intel® Path HBM DC persistent Vector Xeon® Extensions 512 Architecture memory (Intel® AVX-512) processor Distributed memory Memory I/O Threading CPU Core Message size False Sharing File I/O Threaded/serial ratio uArch issues (IPC) Rank placement Access with strides I/O latency Thread Imbalance Vectorization Rank Imbalance Latency I/O waits RTL overhead FPU usage efficiency RTL Overhead Bandwidth System-wide I/O (scheduling, forking) Network Bandwidth NUMA Synchronization Cluster Node Core Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. IntelWhat Parallel are the Studio Aspects Tools covering of Performance the Aspects Intel Hardware Features Multi-core Intel® Intel® Omni Intel® Optane™ Advanced Intel®Path DC persistent Intel® Vector HBM Extensions Architectur Intel® VTune™memory AmplifierXeon® processor 512 (Intel® Tracee Intel®AVX-512) DistributedAnalyzer memory Memory I/O Threading AdvisorCPU Core Messageand size False Sharing File I/O Threaded/serial ratio uArch issues (IPC) Rank placement Access with strides I/O latency Thread Imbalance Vectorization RankCollector Imbalance Latency I/O waits RTL overhead FPU usage efficiency RTL Overhead Bandwidth System-wide I/O (scheduling, forking) Network Bandwidth NUMA Synchronization Cluster Node Core Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. -
Intel® Software Products Highlights and Best Practices
Intel® Software Products Highlights and Best Practices Edmund Preiss Business Development Manager Entdecken Sie weitere interessante Artikel und News zum Thema auf all-electronics.de! Hier klicken & informieren! Agenda • Key enhancements and highlights since ISTEP’11 • Industry segments using Intel® Software Development Products • Customer Demo and Best Practices Copyright© 2012, Intel Corporation. All rights reserved. 2 *Other brands and names are the property of their respective owners. Key enhancements & highlights since ISTEP’11 3 All in One -- Intel® Cluster Studio XE 2012 Analysis & Correctness Tools Shared & Distributed Memory Application Development Intel Cluster Studio XE supports: -Shared Memory Processing MPI Libraries & Tools -Distributed Memory Processing Compilers & Libraries Programming Models -Hybrid Processing Copyright© 2012, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Intel® VTune™ Amplifier XE New VTune Amplifier XE features very well received by Software Developers Key reasons : • More intuitive – Improved GUI points to application inefficiencies • Preconfigured & customizable analysis profiles • Timeline View highlights concurrency issues • New Event/PC counter ratio analysis concept easy to grasp Copyright© 2012, Intel Corporation. All rights reserved. *Other brands and names are the property of their respective owners. Intel® VTune™ Amplifier XE The Old Way versus The New Way The Old Way: To see if there is an issue with branch misprediction, multiply event value (86,400,000) by 14 cycles, then divide by CPU_CLK_UNHALTED.THREAD (5,214,000,000). Then compare the resulting value to a threshold. If it is too high, investigate. The New Way: Look at the Branch Mispredict metric, and see if any cells are pink. -
Intel® Deep Learning Boost (Intel® DL Boost) Product Overview
Intel® Deep Learning boost Built-in acceleration for training and inference workloads 11 Run complex workloads on the same Platform Intel® Xeon® Scalable processors are built specifically for the flexibility to run complex workloads on the same hardware as your existing workloads 2 Intel avx-512 Intel Deep Learning boost Intel VNNI, bfloat16 Intel VNNI 2nd & 3rd Generation Intel Xeon Scalable Processors Based on Intel Advanced Vector Extensions Intel AVX-512 512 (Intel AVX-512), the Intel DL Boost Vector 1st, 2nd & 3rd Generation Intel Xeon Neural Network Instructions (VNNI) delivers a Scalable Processors significant performance improvement by combining three instructions into one—thereby Ultra-wide 512-bit vector operations maximizing the use of compute resources, capabilities with up to two fused-multiply utilizing the cache better, and avoiding add units and other optimizations potential bandwidth bottlenecks. accelerate performance for demanding computational tasks. bfloat16 3rd Generation Intel Xeon Scalable Processors on 4S+ Platform Brain floating-point format (bfloat16 or BF16) is a number encoding format occupying 16 bits representing a floating-point number. It is a more efficient numeric format for workloads that have high compute intensity but lower need for precision. 3 Common Training and inference workloads Image Classification Speech Recognition Language Translation Object Detection 4 Intel Deep Learning boost A Vector neural network instruction (vnni) Extends Intel AVX-512 to Accelerate Ai/DL Inference Intel Avx-512 VPMADDUBSW VPMADDWD VPADDD Combining three instructions into one UP TO11X maximizes the use of Intel compute resources, DL throughput improves cache utilization vs. current-gen Vnni and avoids potential Intel Xeon Scalable CPU VPDPBUSD bandwidth bottlenecks. -
Tips and Tricks: Designing Low Power Native and Webapps
Tips and Tricks: Designing low power Native and WebApps Harita Chilukuri and Abhishek Dhanotia Acknowledgements • William Baughman for his help with the browser analysis • Ross Burton & Thomas Wood for information on Tizen Architecture • Tom Baker, Luis “Fernando” Recalde, Raji Shunmuganathan and Yamini Nimmagadda for reviews and comments 2 tizen.org Power – Onus lies on Software too! Use system resources to provide best User WEBAPPS Experience with minimum power NATIVE APPS RUNTIME Interfaces with HW components, DRIVERS / MIDDLEWARE Independent device power management Frequency Governors, CPU Power OS Management ACPI/RTPM Provides features for low power HARDWARE Clock Gating, Power Gating, Sleep States 3 tizen.org Power – Onus lies on Software too! • A single bad application can lead to exceeding power budget • Hardware and OS provide many features for low power – Apps need to use them smartly to improve power efficiency • Good understanding of underlying system can help in designing better apps Images are properties of their respective owners 4 tizen.org Agenda Tips for Power Tools General Low Power Q&A & Metrics guidelines Applications 5 tizen.org Estimating Power - Metrics • CPU utilization • Memory bandwidth • CPU C and P state residencies • Device D states - For non-CPU components • S states – system sleep states • Wakeups, interrupts Soft metrics can help tune the application for optimal power 6 tizen.org Estimating Power - Tools • CPU utilization – Vmstat, Top – VTune, Perf for CPU cycles • Memory bandwidth – Vtune • CPU C and P states, Device D states – VTune, Powertop • Wakeups, Interrupts, Timers – Powertop, /proc stats • Tracing tool in Chrome browser ** VTune is an Intel product and can be purchased, others are publicly available Linux tools * Other names and brands may be claimed as the property of others. -
DL-Inferencing for 3D Cephalometric Landmarks Regression Task Using Openvino?
DL-inferencing for 3D Cephalometric Landmarks Regression task using OpenVINO? Evgeny Vasiliev1[0000−0002−7949−1919], Dmitrii Lachinov1;2[0000−0002−2880−2887], and Alexandra Getmanskaya1[0000−0003−3533−1734] 1 Institute of Information Technologies, Mathematics and Mechanics, Lobachevsky State University 2 Department of Ophthalmology and Optometry, Medical University of Vienna [email protected], [email protected], [email protected] Abstract. In this paper, we evaluate the performance of the Intel Distribution of OpenVINO toolkit in practical solving of the problem of automatic three- dimensional Cephalometric analysis using deep learning methods. This year, the authors proposed an approach to the detection of cephalometric landmarks from CT-tomography data, which is resistant to skull deformities and use convolu- tional neural networks (CNN). Resistance to deformations is due to the initial detection of 4 points that are basic for the parameterization of the skull shape. The approach was explored on CNN for three architectures. A record regression accuracy in comparison with analogs was obtained. This paper evaluates the per- formance of decision making for the trained CNN-models at the inference stage. For a comparative study, the computing environments PyTorch and Intel Distribu- tion of OpenVINO were selected, and 2 of 3 CNN architectures: based on VGG for regression of cephalometric landmarks and an Hourglass-based model, with the RexNext backbone for the landmarks heatmap regression. The experimen- tal dataset was consist of 20 CT of patients with acquired craniomaxillofacial deformities and was include pre- and post-operative CT scans whose format is 800x800x496 with voxel spacing of 0.2x0.2x0.2 mm. -
2019-11-20 Intel Profiling Tools
Profiling Using the Intel Performance Profilers Ryan Honeyager November 21, 2019 JEDI Topic Discussion Meeting Intel-Provided Tools • Intel Advisor – Helps optimize programs to use vectorization and shared-memory threading. • Intel Inspector – A memory and thread checking and debugging tool. • Intel VTune Amplifier (Profiler) – Performs many kinds of code profiling. • Only discussing VTune Amplifier today • All tools are free and can be downloaded from Intel’s website. • They all work with C++ and Fortran, support MPI, and work with GCC, Intel compilers, Clang. No special compiler options needed beyond building in Debug and RelWithDebInfo modes. • All are installed on Hera already (module load vtune inspector advisor). VTune Amplifier (soon to be renamed VTune Profiler) • Performs many kinds of code profiling: • Examine code hotspots by CPU utilization • Threading / MPI efficiency • Memory consumption • Can profile using either CPU instructions (mostly Intel processors) or with software emulation. Defaults to polling every 10 ms. • Profiling cost varies – hotspot analysis is <5-10%, memory consumption analysis is 2-5x. • Has both GUI and console interfaces. Supports remote profiling via SSH, and can also save / load profiling results for future analysis. Example: See https://github.com/JCSDA/oops/pull/442. Reduced execution time of test by 45% (1.68 to 0.93 seconds) by rewriting ten lines of code. Console-based usage • amplxe-cl –collect hotspots –result-dir out –quiet -- your_app_here.x arg1 arg2 … • If –quiet is not specified, a summary report is printed to the console. • The results directory is around 5-10 MB per unit test. Can be transferred between computers. • Not restricted to profiling an application. -
Intel® Embedded Software Development Tool Suite for Intel® Atom™ Processor
Intel® Embedded Software Development Tool Suite For Intel® Atom™ processor Turbocharge your code for Intel® Atom™ processor-based Product Brief embedded systems Intel® Embedded Software High Performance Data, Media and Signal Powerful Application and JTAG-based Development Tool Suite Processing Libraries Debug for Intel® Atom™ processor High Performance C/C++ Compiler Advanced Performance Analysis Tool Benefit from a comprehensive software development tools solution for your Intel® Atom™ processor- based embedded system designs and application software development. Coding, compiling, debugging and performance tuning made simple. The Intel® Embedded Software Development Tool Suite for Intel® Atom™ processor is a complete solution that addresses embedded software development requirements for Intel® Atom™ processor- powered platforms such as embedded systems, tablets, netbooks, smartphones, IVI and other CE devices. The Embedded Software Development Tool Suite covers the entire software development cycle: coding, compiling, debugging, and analyzing performance. All included tools are Linux* hosted, are compatible with GNU tools, and support multiple Linux* OS based targets. Intel® C++ Compiler for Linux* Intel® Integrated Performance Primitives for Linux* Intel® Application Debugger for Intel® Atom™ processor Intel® JTAG Debugger for Intel® Atom™ processor Intel® VTune™ Amplifier XE for Linux* Compatibility and support for Linux* based targets e.g. Yocto Project* Features and Benefits Feature Benefits Intel® C++ Compiler Boost -
Accelerate Scientific Deep Learning Models on Heteroge- Neous Computing Platform with FPGA
Accelerate Scientific Deep Learning Models on Heteroge- neous Computing Platform with FPGA Chao Jiang1;∗, David Ojika1;5;∗∗, Sofia Vallecorsa2;∗∗∗, Thorsten Kurth3, Prabhat4;∗∗∗∗, Bhavesh Patel5;y, and Herman Lam1;z 1SHREC: NSF Center for Space, High-Performance, and Resilient Computing, University of Florida 2CERN openlab 3NVIDIA 4National Energy Research Scientific Computing Center 5Dell EMC Abstract. AI and deep learning are experiencing explosive growth in almost every domain involving analysis of big data. Deep learning using Deep Neural Networks (DNNs) has shown great promise for such scientific data analysis appli- cations. However, traditional CPU-based sequential computing without special instructions can no longer meet the requirements of mission-critical applica- tions, which are compute-intensive and require low latency and high throughput. Heterogeneous computing (HGC), with CPUs integrated with GPUs, FPGAs, and other science-targeted accelerators, offers unique capabilities to accelerate DNNs. Collaborating researchers at SHREC1at the University of Florida, CERN Openlab, NERSC2at Lawrence Berkeley National Lab, Dell EMC, and Intel are studying the application of heterogeneous computing (HGC) to scientific prob- lems using DNN models. This paper focuses on the use of FPGAs to accelerate the inferencing stage of the HGC workflow. We present case studies and results in inferencing state-of-the-art DNN models for scientific data analysis, using Intel distribution of OpenVINO, running on an Intel Programmable Acceleration Card (PAC) equipped with an Arria 10 GX FPGA. Using the Intel Deep Learning Acceleration (DLA) development suite to optimize existing FPGA primitives and develop new ones, we were able accelerate the scientific DNN models under study with a speedup from 2.46x to 9.59x for a single Arria 10 FPGA against a single core (single thread) of a server-class Skylake CPU. -
Intel Threading Building Blocks
Praise for Intel Threading Building Blocks “The Age of Serial Computing is over. With the advent of multi-core processors, parallel- computing technology that was once relegated to universities and research labs is now emerging as mainstream. Intel Threading Building Blocks updates and greatly expands the ‘work-stealing’ technology pioneered by the MIT Cilk system of 15 years ago, providing a modern industrial-strength C++ library for concurrent programming. “Not only does this book offer an excellent introduction to the library, it furnishes novices and experts alike with a clear and accessible discussion of the complexities of concurrency.” — Charles E. Leiserson, MIT Computer Science and Artificial Intelligence Laboratory “We used to say make it right, then make it fast. We can’t do that anymore. TBB lets us design for correctness and speed up front for Maya. This book shows you how to extract the most benefit from using TBB in your code.” — Martin Watt, Senior Software Engineer, Autodesk “TBB promises to change how parallel programming is done in C++. This book will be extremely useful to any C++ programmer. With this book, James achieves two important goals: • Presents an excellent introduction to parallel programming, illustrating the most com- mon parallel programming patterns and the forces governing their use. • Documents the Threading Building Blocks C++ library—a library that provides generic algorithms for these patterns. “TBB incorporates many of the best ideas that researchers in object-oriented parallel computing developed in the last two decades.” — Marc Snir, Head of the Computer Science Department, University of Illinois at Urbana-Champaign “This book was my first introduction to Intel Threading Building Blocks.