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Sequential Equivalence Checking for Clock-Gated Circuits Hamid Savoj, Alan Mishchenko, and Robert Brayton, Fellow, IEEE

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Sequential Equivalence Checking for Clock-Gated Circuits Hamid Savoj, Alan Mishchenko, and Robert Brayton, Fellow, IEEE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 2, FEBRUARY 2014 305 Sequential Equivalence Checking for Clock-Gated Circuits Hamid Savoj, Alan Mishchenko, and Robert Brayton, Fellow, IEEE Abstract—Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence checking (CEC) problem. It shows how the theory can be applied when sequential transforms are used, such as sequential clock gating, retiming, and redundancy removal. The legitimacy of such transforms is typically justified intuitively, Fig. 1. Sequential circuit A. by the designer or software developer believing that the two circuits reach the same state after a finite number of cycles, and no difference is observed at the outputs due to fanin non- these functions can be completely restructured. In this case, controllability and fanout non-observability effects. equivalence checking consists of checking the equivalence of A method based on these theorems was applied to 12 large the combinational parts of the two circuits. industrial examples, which had been combinationally and se- In contrast, sequential synthesis additionally uses informa- quentially clock-gated by a commercial clock-gating tool. These examples lead to SEC problems, which are problematic for a gen- tion about the states unreachable from the initial state to eral, state-of-the-art SEC engine. The new approach completed modify the combinational logic further. This can consist of: verification of all examples and was about 30 times faster on the 1) using the unreached states as don’t cares; 2) using the 3 cases where the conventional SEC engine was able to prove the fact that two states are equivalent; 3) using a different state- problem within one hour. encoding for the reachable states; 4) retiming the FFs; or 5) Index Terms—Formal verification, logic synthesis, sequential merging two signals in the circuit if in all reachable states the synthesis, synthesis for low power. signals have the same values. These two types of synthesis lead to different kinds of I. Introduction problems when comparing the original circuit against the synthesized circuit. While combinational equivalence checking SEQUENTIAL circuit, depicted in Fig. 1, is composed (CEC) is NP-complete, sequential equivalence is PSPACE- of a combinational logic part (A1) and a set of memory A complete. This paper considers a particular type of sequential elements [called flip-flops (FF), or flops]. synthesis in which the NS combinational functions can be It also has a set of primary inputs (PIs) and a set of primary changed using state equivalence reasoning. We show that the outputs (POs). The combinational logic has inputs composed corresponding SEC problem is only NP-complete and give of the PIs plus the current state (CS) of the FF’s, and has methods for reducing the SEC problem to a CEC problem in outputs composed of the POs plus the next state (NS), which these cases. Such synthesis transformations arise frequently in is stored in the FF’s on the next clock edge. commercial software packages that perform clock gating to We assume that the FF’s start in a known initial state at time reduce power. 0. Two sequential circuits are said to be equivalent if, starting To initially motivate this paper, we look at one method for from their respective initial states, for any given (infinite) sequential synthesis that is quite practical but not obviously sequences of PIs, the two generated (infinite) sequences of valid. Consider a sequential circuit, A, which is to be optimized the associated POs are identical. by a k-step unrolling process as indicated in Fig. 2. The Combinational synthesis changes only the combinational combinational part of A (called A1) is copied k times and logic but keeps the PO and NS functions (as functions of these are cascaded so that the NS outputs of one copy are PIs and CSs) unchanged, although the network computing feeding into the CS inputs of the following copy, resulting in 1 Manuscript received June 30, 2013; accepted September 23, 2013. Date of the combinational circuit C shown in the top part of Fig. 2. 1 current version January 16, 2014. This work was supported in part by SRC Note that the outputs of C are (PO1, ... ,POk, and NS). contract 1875.001 and in part by NSA Grant Enhanced Equivalence Checking We use the notation C1 =(A1)k to denote this circuit, which in Crypto-Analytic Applications. This paper was recommended by Associate 1 Editor W. Kunz. has k copies of A . Now suppose combinational synthesis is The authors are with the Electrical Engineering and Computer Sci- applied to the logic of the first copy while the other k-1 copies ences Department, University of California at Berkeley, Berkeley, CA are left untouched, resulting in the circuit C2 = B1(A1)k−1 94720 USA (e-mail: [email protected]; [email protected]; [email protected]). shown at the bottom of Fig. 2. Although the NS outputs of Digital Object Identifier 10.1109/TCAD.2013.2284190 the final copy are necessarily preserved by the combinational 0278-0070 c 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications standards/publications/rights/index.html for more information. 306 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 33, NO. 2, FEBRUARY 2014 Section III demonstrates instances where theorem 1 can be applied while Section IV demonstrates instances where theorem 2 or 3 can be applied. The emphasis is on those scenarios where sequential clock gating methods are used to save power. Such synthesis methods are often used in commercial clock-gating software. In addition, new inductive techniques for removing sequential redundancies are discussed in Sections III and IV. Section V discusses the simultaneous use of both theorems, and gives a counterexample to item four above. Section VI discusses literature related to this paper, in- cluding ATPG methods for sequential redundancy removal. Section VII shows experimental results where the proposed methods are used to formally verify equivalence after se- Fig. 2. k-step unrolling, ODC optimization of A1, and the combinational part of FSM A. quential clock gating is applied to industrial circuits. The experiments illustrate how the new methods make sequential equivalence checking (SEC) more efficient and practical for such problems. Finally, Section VIII summarizes the paper and poses open questions for future research. Fig. 3. Derived sequential circuit B. II. Sequential Equivalence 1 1 Let A be a sequential circuit and A denote the combina- synthesis, the internal NS output of B as well as the successive 1 k 1 1 2 tional part of A. Instead of using (A ) to denote A cascaded NS outputs of the k-2 copies of A in C may be different from k 1 k times, we just use A to denote the combinational circuit the corresponding internal NS outputs in C . 1 1 obtained by connecting k copies of A at the NS outputs and The purpose of the last k-1 copies of A in this scenario CS inputs. This is shown on top of Fig. 2. The outputs of Ak is to produce observability don’t cares (ODCs) [13] used for 1 1 are the set of k POs of A, one set for each time-frame plus transforming the first copy of A into B , which forms the the final NS signals at the output of the kth frame. The inputs combinational part of a new sequential circuit B. of Ak are the k sets of PIs of each frame, plus the initial CS Now consider the sequential circuit shown in Fig. 3. signals of the first frame. Several questions arise regarding this. Let A and B be two sequential circuits with the same 1) Is the derived circuit B sequentially equivalent to A? PIs and POs, and the same number of FFs. BnAk denotes 1 This question cannot be answered by just comparing A the combinational circuit where the NS outputs of Bn are 1 with B because they are not combinationally equivalent. connected to the CS inputs of Ak. The connection is based 1 Also, the fact that C is combinationally equivalent to on the 1-1 mapping between the FFs of A and B given by the 2 C does not constitute a proof of sequential equivalence. user. The circuit, B1Ak−1, is shown in Fig. 2. 1 k 1 k 2) Would comparing (A ) with (B ) suffice for a SEC In this paper, it is always assumed that a single initial state proof? is given for a sequential machine. We are not concerned with 1 n 3) Suppose A is unrolled n times creating (A ) and the initializing sequences and so on, but follow the philosophy last copy of A is synthesized using satisfiability don’t articulated in [1]. Two machines are sequentially equivalent if cares (SDCs) [13] provided by the first n-1 copies starting in their initial states, and their POs produce identical 1 1 n−1 1 of A , creating (A ) B . Are A and the resulting B sequences when identical sequences are applied to the PIs. sequentially equivalent? For reasons similar to those For two sequential circuits A and B, A = B denotes that the listed in Question 1, this is not obvious. circuits are sequentially equivalent starting from the two given 4) More generally, suppose A is unrolled n+k times and initial states. If C and D are combinational circuits, then C = D th 1 the n copy of A is synthesized, using both ODCs from denotes that they are combinationally equivalent, i.e., for any 1 k 1 n−1 1 n−1 1 1 k (A ) and SDCs from (A ) , to produce (A ) B (A ) input, their outputs are identical.
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