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IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 731 Controlled Intersymbol Interference Design Techniques of Conventional Interconnect Systems for Data Rates Beyond 20 Gbps Wendemagegnehu T. Beyene, Senior Member, IEEE, and Amir Amirkhany, Member, IEEE Abstract—This paper presents a new design technique of high- of a channel. Some of these band-limiting structures are not part speed interconnects with controlled intersymbol interference (ISI) of the signal path and they exist merely because of manufac- to create efficient signaling over a band-limited channel. Perfor- turing artifacts or mechanical requirements. For example, the mance of high-speed electrical links is limited by conductor loss, di- electric dispersion, and reflections in the board, package, and con- via stubs in a conventional backplane and the plating stubs in a nector. These nonidealities result in significant ISI. In current sys- wirebond plastic ball grid array (PBGA) package do not serve tems, the effect of ISI is either mitigated through complex equaliza- any electrical purpose [1]. These via and plating stubs signifi- tion, signal conditioning, and coding techniques, or through costly cantly reduce the operating bandwidth of the channel by intro- impedance control and manufacturing processes. In the proposed approach, instead of eliminating ISI, we shape the response of the ducing resonances, as shown in Fig. 1(b). As a result, the traces channel into a set of channel characteristics with controlled ISI with long stubs show significant reduction in their bandwidth. using simple passive structures in the board and the package. The The increase in data rate over an interconnect is currently resulting controlled ISI is exploited at the transmitter and receiver made possible by designing controlled impedance interconnect to simplify the architecture of the system and to achieve high data rates. The techniques to design interconnects with controlled ISI systems. In addition, the discontinuities created by connectors, are reasonably simple to implement in conventional interconnect solder balls, and stubs have been mitigated so far by careful technologies. Simulation examples are given to demonstrate the va- compensation techniques [2]. However, as the data rate in- lidity and advantages of the design technique using duobinary and creases, the compensation effect diminishes because of the analog multitone (AMT) signaling methods. narrow band nature of the techniques and the increase in the Index Terms—Analog multitone (AMT) signaling, doubinary overall channel attenuation. Improved packaging, connector, signaling, intersymbol interference (ISI), partial response sig- via technologies, and better materials can further improve naling. transmission characteristics of the channel. However, the cost of the channel will increase significantly. I. INTRODUCTION Another approach to mitigate the effect of ISI is the use of IGH-SPEEDdatatransmissionoverpassiveinterconnects equalization techniques [3], [4]. Unfortunately, for low-cost in- H is required to support the high-bandwidth demand of cur- terconnect technologies with long stubs, the frequency charac- rent computing and communication systems. The bandwidth of teristics have nulls that can be problematic for simple equal- current chip-to-chip and backplane links is limited by the band- ization techniques. This requires complex on-chip digital signal widthofthepassivecomponents(package,board,connector),and processing circuitry. An alternative approach is to use multilevel not by the operating speeds of the active circuitry in the trans- signaling and pack the data into a small bandwidth [5]. Mul- mitter and receiver. The interconnect systems are band-limited tilevel signaling, however, sacrifices the signal-to-noise ratio due to the loss and dispersive mechanism inherent to the inter- (SNR) and adds to the complexity of the timing recovery cir- connects and its surroundings. These nonidealities are more pro- cuits and to the power consumption of the system. nounced in low-cost packaging, printed circuit board (PCB), and An alternative to these techniques, which all try to eliminate connectortechnologies.Theinsertionlossofvariouslengthchan- ISI, is to control ISI and shape it to specific known patterns that nels in conventional interconnect systems are shown in Fig. 1(a). can be exploited at the receiver for efficient signal detection [6]. Thereceivedsignalenergyinlongchannelssuchasthoseinlegacy In this alternative approach, the design goal of an interconnect backplanes is very small when the operating frequency exceeds system is to shape the response of the channel using trace and via 5 GHz. For medium and short channels, the detectable signal en- stubs (contrary to impedance matching), so that the system has ergy is limited to the frequency ranges of up to 10 GHz. the desired characteristics to transmit higher data rates or has In addition to the attenuation, the discontinuities due to vias, simpler transmitter or receiver. Signal transmission technique connectors, solder balls, and stubs severely limit the bandwidth over controlled ISI channels are well studied in the literature and a number of algorithms exist to choose from [7]–[9]. Manuscript received September 11, 2007; revised February 19, 2008. First In Sections II, the state of the art link systems with transmit published May 16, 2008; current version published November 28, 2008. This and receive equalizers are briefly described. Then, two classes work was recommended for publication by Associate Editor P. Franzon upon evaluation of the reviewers comments. of signaling techniques over controlled ISI channel, partial sig- The authors are with Rambus Inc., Los Altos, CA 94022 USA (e-mail: naling, and analog multitone (AMT) signaling are introduced in [email protected]; [email protected]) Section III. Controlled ISI channel engineering is presented in Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Section IV. In Section V, a design example of a high data rate Digital Object Identifier 10.1109/TADVP.2008.924224 signaling and system is presented. Implementation details and 1521-3323/$25.00 © 2008 IEEE Authorized licensed use limited to: Texas A M University. Downloaded on June 23, 2009 at 13:07 from IEEE Xplore. Restrictions apply. 732 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 31, NO. 4, NOVEMBER 2008 time or frequency domains. The preemphasis filter can be im- plemented using analog techniques by integrating the filter into each driver module as a parallel transmitter. The decision feedback equalizer (DFE) is a nonlinear equal- izer that employs previous decisions to eliminate ISI caused by previous detected symbols on the current symbol to be detected. The single-bit response (SBR) of a high-speed interconnect with DFE is shown in Fig. 4. The DFE is not able to cancel the pre- cursor ISI as it is causal. Consequently, the DFE often needs to be paired with a FFE. DFE is the most effective way to cancel postcursor ISI because as opposed to a transmit FFE it does not reduce the transmit peak voltage budget and unlike a receive FFE it does not amplify channel noise. However, a major cir- cuit design challenge in the design of the first (few) postcursor DFE taps is closing the timing for feedback loop in one (or few) unit intervals, as shown in Fig. 5(a). This problem is particularly more pronounced for the first DFE tap, as the received signal has to be detected, multiplied by the appropriate weight coeffi- cient, and subtracted from the incoming signal, all in only one unit interval. A unit interval can be as small as 50 ps in 20-Gbps 2-PAM link. As a result the first DFE tap is often not removed in high-speed links, or look-ahead computation is used to unroll the loop and increase the delay in the feedback loop [10]–[12]. In one-tap loop-unrolled DFE, two decisions are made at each cycle. One comparator decides the received signal as if the previous received signal was a one, and the other comparator decides the received signal as if the previous bit was a zero. Once we know the previous bit, the correct comparator output Fig. 1. Insertion loss of lossy and discontinues conventional low-cost intercon- nects. (a) Insertion loss of typical signal nets with varying length. (b) Insertion is chosen. A one-tap loop-unroll DFE is shown in 5(b). The loss of wirebond PBGA package nets with 2.6 to 4.5-mm-long plating stubs. loop-unroll DFE makes two decisions on two conditioned eyes using samplers that are offset by the first postcursor ISI tap magnitude [10]. The lower and upper eye diagrams, are shown comparisons of various signaling techniques including duobi- in Fig. 6(a) and (b), respectively. The two eyes are split by nary and AMT are discussed. Finally, the conclusion is given in the amount proportional to the first post-cursor ISI tap. The Section VII. timing constraint in a loop-unrolled DFE is to accommodate a flip-flop and a multiplexer in one unit interval, which could II. STATE OF THE ART LINK DESIGN still be a challenge at 20-Gbps. The number of samplers re- In high-speed link design, equalization and signal processing quired for loop-unrolling for more than one tap increases as techniques are used to mitigate the effects of ISI. Equalization . As a result, loop-unrolling for more than one can compensate channel frequency-dependent loss and disper- tap is generally avoided. sion of long traces in boards and packages, and dispersion due to device loadings [3]. Fig. 2 shows a block diagram of a state of III. CONTROLLED-ISI LINK DESIGN the art link. Both linear and decision feedback equalizers often The equalization techniques described in the previous sec- exist in current systems. The linear equalizer is a feed-forward tion are targeting arbitrary forms of ISI. However, for the cases equalizer (FFE) that uses linear filters with adjustable param- where the communication channel has a well-defined pattern, eters to compensate for channel distortion.

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