CALIFORNIA STATE UNIVERSITY,NORTHRIDGE DIGITAL SIGNAL PROCESSING INTEGRATED CIRCUITS (DSP ICS) A project submitted in partial satisfaction of requirements for the degree of Master of Science in Electrical Engineering by Trung Dien Vo January 1988 The Project of Trung Dien Vo is approved: California State University, Northridge :'. j_ i i TABLE OF CONTENTS List of Figures ...................................... iv List of Tables ...................................... vii Abstract . .......................................... viii Chapter 1 INTRODUCTION . ......•..........•..•..••.•.• 1 Chapter 2 THE NEC 7 7 2 0 .........................•.... 3 Chapter 3 THE TEXAS INSTRUMENTS TMS320XX DSP FAMILY . ...•..................•..•••...... 15 Chapter 4 THE ANALOG DEVICES ADSP-2100 ............. 30 Chapter 5 THE ZORAN ZR34161 VECTOR SIGNAL PROCESSOR • •••••.••••••••••••••••••••••••• 4 7 Chapter 6 THE MOTOROLA DSP56000 ........•........... 57 Chapter 7 THE AT&T WE-DSP32 ................•....... 92 Chapter 8 THE TEXAS INSTRUMENTS TMS320C30 .......•. 104 Chapter 9 THE ZORAN ZR34325 ....................... 117 Chapter 10 THE EFFECTS OF WORD LENGTH ON DYNAMIC RANGE • .•••••••••.•••..•..•••.•••..•.•.•• 129 Chapter 11 COMPARISONS OF DIFFERENT DSP ICS ..•..... 151 Chapter 12 APPLICATIOt-~S . ............. e ••••••••••••• 166 Chapter 13 CONCLUSION ..........•........•...•....•. 172 References . ......................................... 17 4 Appendix A THE PIPELINE AND HARVARD ARCHTITECTURES •.............•........... 178 Appendix B THE REDUCED-INSTRUCCTION-SET-COMPUTING (RISC) ARCHITECTURE •••.•••••••.••..••..• 185 Appendix C FLOATING-POINT VERSUS FIXED-POINT ARITHMETIC . .................•...•.•.••.. 188 Appendix D TERMINOLOGY ..••...••..••...••.•.•••••••• 197 Appendix E LIST OF VENDORS ..........•.....•.....••• 201 iii LIST OF FIGURES ChaEter ~ Figure 2.1 NEC 7720 Block Diagram ..••...•••••••••••• 4 Figure 2.2 Data RAM & Peripherals ..•••••••••••••••.• 6 Figure 2.3 ALU Block Diagram ..••.••..•.••.•••.•••••• s Figure 2.4 Serial Input ............................ 11 Figure 2.5 Serial Output ........................... 11 Figure 2.6 Parallel I/0 .........•...•..........•..• 13 Cha12ter 3 Figure 3.1a TMS320 Family Generation •.•••••.••••••.• 16 Figure 3.1b TMS320 Family Generation (Technology) .•• 17 Figure 3.2 TMS320C25 Block Diagram .•••••••••••••••• 25 ChaEter .! Figure 4.1 ADSP-2100 Block Diagram ..•••.•••.••.•.•• 31 Figure 4.2 ALU Architecture ..•.•...•...•.••.•.•.••• 33 Figure 4.3 MAC Block Diagram ...•..•...•..••......•. 39 Figure 4.4 Shifter Block Diagram .•••••••.•.•..••••• 41 Figure 4.5 Data Address Generator (DAG) .•.••.••.••• 42 Figure 4.6 Program Sequencer •••••..••••..•••••.••.• 44 Figure 4.7 PMD-DMD Bus Exchange Unit (BEU) ..••••••• 46 ChaEter 5 Figure 5.1 ZR34161 VSP Block Diagram .••••••••••.••• 48 Figure 5.2 VSP Execution Unit Block Diagram .•.••••. 52 ChaEter 6 Figure 6.1 DSP56000 Block Diagram •••••••••••••••••• 59 Figure 6.2 Program Controller ••....•..••••••••••••• 63 iv Figure 6.3 Status Register ..••..•.••••.•.•.•.••..•• 70 Figure 6.4 Operating Mode Register •..•••••••••••••• 70 Figure 6.5 Stack Pointer (SP) Format ..••••••••••••. 72 Figure 6.6 Stack Pointer Values ..••..•••••••••••••• 72 Figure 6.7 Data ALU . .............•............•.... 77 Figure 6.8 Address ALU . .•.••.•....••.•.••..•••.••.• 84 Cha}2ter 2 Figure 7.1 WEDSP-32 Block Diagram •.••...••...•.••.• 93 Figure 7.2 Control Arithmetic Unit ...•.•...•...•••• 95 Figure 7.3 Memory Configuration ...•..•••.•.••••••• 101 Cha12ter !!_ Figure 8.1 TMS320C30 Block Diagram .••••.•.•.••••.• 105 Figure 8.2 Central Processing Unit (CPU) •.• o.oo •• o107 Figure 8.3 DMA Controller •.••.••..••••.•••• o • o • o •• 109 Figure 8.4 Memory Organization .•.•••••••.•.•.••.•• 111 Figure 8.5 Peripherals . .......................... 113 Cha12ter ~ Figure 9.1 ZR34325 Block Diagram .•.•.••••.••••.••• 118 Figure 9.2 Execution Unit ••••••••.•.•••••••••••••• 12 3 Figure 9.3 Internal Memory •••••••••••.•••• o•o•••••123 Figure 9.4 Internal Registers •.•.••.•••••• o •..• o •• 124 Cha}2ter 10 Figure 10.1 Truncation Effect on Frequency Response . ••••..•.••.••.•••.••••••••.••• 13 2 Figure 10.2 Sampling Process ••••••••••••••••••••••• 135 Figure 10.3 Additive Errors Due to Quantization.o •• 137 Figure 10.4 Dynamic Range Versus Data Word Length •• 141 v Figure 10.5 Mse Versus Word Length (d, t, k) •..••.• 145 Figure 10.6a Mse Versus Data Word Length (d) .•••••.• 146 Figure 10.6b Mse Versus Intermediate Word Length (t) •..••••..••••••••••.•••• 14 7 Figure 10.6c Mse Versus Kernel Word Length (k) •••••• 148 Appendix ~ Figure A.1 Pipeline Operation of Floating-point Addition ............................... 180 Figure A.2 Von Neumann Operation ...••.•.••.....•.. 182 Figure A. 3 Harvard Operation ..•••..••••.•.•••.•••. 182 Figure A.4 3-Bus Harvard Operation .••.•..•.••••••. 184 Figure A. 5 Pipelined Harvard Operation ..•••....••• 184 Appendix ~ Figure C.1 Dynamic Range Versus Word Length •.••••. 194 Figure C.2 Precision Versus Word Length •.••••••••• 196 vi LIST OF TABLES Chapter ..§. Table 6.1 Accumulator Shifter Functions •••••••••••• 81 Chapter 10 Table 10.1 Dynamic Range Limiting Factor .•••.•••••• 150 Chapter 11 Table 11.1 Comparison of Benchmark Performance of 16-bit DSP ICs •••••...•.•.•••...•••.•.•• 157 Table 11.2 Comparison of 16-bit DSP ICs' Features .. 159 Table 11.3 Comparison of Benchmark Performance of 24- and 32-bit DSP ICs .•••••.••.•••••••• 164 Table 11.4 Comparison of 24- and 32-bit DSP ICs' Features . .............................. 165 vii ABSTRACT DIGITAL SIGNAL PROCESSING INTEGRATED CIRCUITS (DSP ICS) by Trung D. Vo Master of Science in Engineering Digital signal processing integrated circuits (DSP ICs), a new breed of microelectronic device has changed the picture of signal processing. Advances in VLSI (Very Large Scale Integrated) circuit density and speed have been so successful in the past few years, that today a single-chip digital signal processor can perform the tasks that previously required bulky circuit boards full of power-hungry devices. These DSP chips are readily available from many vendors, with the more advanced ones currently in the development cycle. This paper discusses and compares certain popular DSP ICs in relation to their architectures, performances and applications. viii CHAPTER 1 INTRODUCTION The single~chip digital signal processing IC is a very significant development for digital signal processing. currently, there are over 20 manufacturers competing in this DSP IC market. Most of these manufacturers are major, well~established IC makers that have been successful with general-purpose microprocessors. This paper covers eight DSP ICs from six different vendors: the NEC 7720, the Analog Devices ADSP-2100, the Texas Instruments TMS320XX family, the Zoran ZR34161, the Motorola DSP56000, the AT&T WE-DSP32, the Texas Instruments TMS320C30, and the Zoran ZR34325. The first four of the group are 16-bit devices. The Motorola DSP56000 is 24-bit, and the last three are 32-bit. The TI TMS320XX family is the largest DSP IC family consisting of about fourteen versions. The other more-than-16-bit devices, except the AT&T WE-DSP32, are still in the development stages and have not been in production at the time of this writing. They are, however, expected to be available in the very near future. Most of these DSP res employ CMOS technology which offer very low power consumption. They are fast, with instruction cycles as low as 50 ns and their operations are general-purpose microprocessor-like. This means that the chips fetch and execute instructions from memory just like any other computer. However, the detailed internal 1 2 architectures of DSP ICs are significantly different from the architectures of microprocessors. Most DSP ICs employ a Harvard architecture [See Appendix A], in which the data and program memories are separate, thus allowing data and program instructions to be fetched simultaneously. Also, to maximize the operation speed, these DSP ICs are based largely on reduced-instruction set computing (RISC) [See Appendix B] and pipeline architectures [Appendix A]. The eight DSP ICs are classified into two groups for comparisons. One group consists of the 16-bit devices and the other consists of devices having more than 16-bit data wordlength. Detailed architectures of the devices are discussed to provide a means for comparison and selection guidelines for a suitable DSP IC are developed. Since the data word lengths of these devices vary (16-, 24-, and 32-bit), the effects of data word lengths on system dynamic range are studied in detail and results from simulations on these effects are included. A chapter is devoted to comparing the DSP ICs based on their architectures and performances. Typical applications using these DSP res are also discussed in another chapter to provide some examples. Finally, it is concluded that: technically, all of the eigth DSP res are suitable for most DSP applications. The selection of the best one for a particular application is dependent on its unique requirements. CHAPTER 2 THE NEC 7720 1. Introduction The NEC 7720 (sometimes as uPD7720) is a 16-bit microprogrammable device designed to be a flexible, versatile number cruncher able to function as a stand- alone processor. It is aimed mainly for telecommunications, where accuracy, speed, and interface compatibility with existing systems is of great importance. The NEC 7720, however, has more general features that make it suitable for a broader range of applications. 2. Architecture