BSDL Syntax Specifications

Appendix A BSDL Syntax Specifi cations This Appendix is a condensed listing of 2001 BSDL lexicography and syntax. It does not include the myriad semantic rules found in the BSDL specifi cation as provided by the IEEE [ IEEE01 ]. This information may be helpful to someone contemplating writing a BSDL parser, or to someone needing a quick reference guide for BSDL syntax when writing a BSDL description. It is assumed the reader is familiar with formalized specifi cation of language. A.1 Conventions All reserved words, predefi ned words, and punctuation are shown in Courier New type within this document. VHDL reserved and predefi ned words will be shown in lowercase letters, and BSDL reserved words will be shown in UPPERCASE letters. (BSDL itself is case-insensitive; this convention is adopted for descriptive clarity.) A.2 Lexical Elements of BSDL The lexical elements of BSDL are a subset and standard practice of those of VHDL as defi ned in IEEE Std 1076-1993. The following sections enumerate the lexical elements needed to understand the BSDL language defi nition. A.2.1 Character Set • Upper- and lowercase letters: A to Z and a to z (the language is not case sensitive). © Springer International Publishing Switzerland 2016 491 K.P. Parker, The Boundary-Scan Handbook, DOI 10.1007/978-3-319-01174-5 492 A BSDL Syntax Specifi cations • Digits: 0 –9. • Special characters: " & ‘ ( ) * , - . : ; < = > • Logical separators: The space character, horizontal tabulation, vertical tabulation, carriage return, line feed, and form feed. A.2.2 Identifi ers Identifi ers are user-supplied names and reserved words functioning as names. Identifi ers start with a letter and may contain letters, digits, or the underscore character. For example, the following are valid identifi ers: Boundary_Scan IEEE_Std_1149_1 There is no limit to the number of characters in an identifi er. The underscore character ( _ ) is not allowed as the last character in an identifi er (by VHDL). IEEE_STD_1149_ -- This is not a legal identifi er. Adjacent underscore characters ( _ _ ) are not allowed. A.2.3 BSDL Reserved Words The identifi ers listed in this section are BSDL reserved words with a fi xed signifi - cance in the language. These identifi ers cannot be used for any other purpose in a BSDL description. For example, a reserved word cannot be used as an explicitly declared identifi er. BC_0 to BC_99 are variable names used in the Standard VHDL Package. Names BC_0 through BC_ 10 are used today, while BC_11 through BC_99 are reserved for future use. Similarly, the names STD_1149_1_1990 , STD_1149_1_1993 , STD_1149_1_1994 and STD_1149_1_2001 have been reserved, with the potential for new names to be added later. Therefore, avoid using identifi ers that start with “STD_1149_ ”. AT_PINS INTERNAL BC_0 to BC_99 INTEST BIDIR INTEST _ EXECUTION BIDIR_IN KEEPER BIDIR_OUT LOW BOTH OBSERVE_ONLY BOUNDARY OBSERVING BOUNDARY_ LENGTH ONE BOUNDARY_ REGISTER OUTPUT2 A.2 Lexical Elements of BSDL 493 BSCAN_INST OUTPUT3 BSDL_EXTENSION PHYSICAL_PIN_ MAP BYPASS PI CAP PIN_ MAP CAP_DATA PIN_ MAP _STRING CAPTURES PO CELL_DATA PORT_ GROUPING CELL_INFO PRELOAD CELL_TYPE PULL0 CLAMP PULL1 CLOCK REGISTER_ ACCESS CLOCK_INFO RUNBIST CLOCK_LEVEL RUNBIST _ EXECUTION COMPLIANCE_ PATTERNS SAMPLE COMPONENT_ CONFORMANCE STD_1149_1_1990 CONTROL STD_1149_1_1993 CONTROLR STD_1149_1_1994 DESIGN_ WARNING STD_1149_1_2001 DEVICE_ID TAP_SCAN_ CLOCK DIFFERENTIAL_CURRENT TAP_SCAN_ IN DIFFERENTIAL_VOLTAGE TAP_SCAN_ MODE EXPECT_DATA TAP_SCAN_ OUT EXTEST TAP_SCAN_ RESET HIGHZ UPD ID_BITS USERCODE ID_STRING USERCODE _ REGISTER IDCODE WAIT_DURATION IDCODE _ REGISTER WEAK0 INPUT WEAK1 INSTRUCTION_ CAPTURE X INSTRUCTION_ LENGTH Z INSTRUCTION_ OPCODE ZERO INSTRUCTION_ PRIVATE A.2.4 VHDL Reserved and Predefi ned Words The identifi ers listed below are called VHDL ( IEEE Standard 1076 -1993) reserved and predefi ned words with a fi xed signifi cance in the language. These identifi ers may not be used for any other purpose in a BSDL description. For example, a reserved word cannot be used as an explicitly declared identifi er. Reserved words shown in the list below in lowercase letters are part of the BSDL subset of VHDL. Those in uppercase letters are not part of BSDL, but should not be used as 494 A BSDL Syntax Specifi cations identifi ers. The latest edition of the VHDL standard [ IEEE93b ] shall be consulted as the fi nal authority . ABS GUARDED REGISTER ACCESS IF REJECT AFTER IMPURE REM ALIAS in REPORT all INERTIAL RETURN AND inout ROL ARCHITECTURE is ROR array LABEL SELECT ASSERT LIBRARY SEVERITY attribute linkage SHARED BEGIN LITERAL signal bit LOOP SLA bit_vector MAP SLL BLOCK MOD SRA body NAND SRL buffer NEW string BUS NEXT subtype CASE NOR THEN COMPONENT NOT to CONFIGURATION NULL TRANSPORT constant of true DISCONNECT ON type downto OPEN UNAFFECTED ELSE OR UNITS ELSIF OTHERS UNTIL end out use entity package VARIABLE EXIT port WAIT false positive WHEN FILE POSTPONED WHILE FOR PROCEDURE WITH FUNCTION PROCESS XNOR GENERATE PURE XOR generic range GROUP record A.2.5 Strings A string is defi ned as a sequence of zero or more characters enclosed between quotation marks. A quotation mark character is not allowed within a string in BSDL. For example, A.3 Notes on Syntax Defi nition 495 "Mary had a little lamb" -- Allowed "Fred said ""HELP""" -- Not allowed Strings are used extensively in BSDL. Because many of the BSDL strings are potentially much longer than a single line, the concatenation operator & is used to break them into manageable pieces. For example, "Jack be nimble," & " Jack be quick." is a single string, identical to "Jack be nimble, Jack be quick." BSDL does not permit replacement of the quotation mark with any other character. A string literal must fi t on one line since it is a lexical element. A.2.6 Comments Any text between a double dash (-- ) symbol and the end of a line is treated as a comment. The text is allowed to contain any characters allowed by VHDL. Comments syntactically terminate a line of a description. Comments may be interspersed with lexical elements. For example, the following represents a single VHDL string: "This is" & -- An example of a string split by a comment " a single string" A.3 Notes on Syntax Defi nition A.3.1 BNF Conventions • Any item enclosed in chevrons (i.e., between the character “<” and the character “>”) is the name of a syntax item that will be defi ned in this appendix. • Items enclosed by braces (i.e., between the character “{” and the character “}”) may be omitted or included one or more times. • Items enclosed between square brackets (i.e., between the character “[” and the character “]”) may be omitted or included only one time. • Items enclosed between the symbols “→” and “←” may appear in any order. • Except with regard to case, text shown in Courier New type font has to be included exactly as it is presented in this appendix. • Alternative syntaxes are separated by a vertical bar (“|” ). • The symbol “::=” should be read as “is defi ned as.” Note that the non-boldface “::=” is only part of a BNF description; in the BSDL fi le, the boldface characters “:= ” are used to indicate assignment. 496 A BSDL Syntax Specifi cations • White space (spaces, tabulation, carriage returns, etc.) is used in these BNF descriptions to enhance readability and is not part of the syntax. However, white space needed for resolving lexical ambiguity is required. A.3.2 Lexical Atoms • A <VHDL identifi er> is a valid identifi er, chosen as a name for an item. • An <integer> is an unsigned VHDL integer made up of an unsigned numeric character sequence not containing an underscore (_) character and not using an exponent fi eld. • A <real number> is a VHDL real number of the form <integer> . <integer> or <integer>. <integer>E <integer> all written contiguously without spaces or for- mat effectors. Note 1E3 is not real because it does not contain a decimal point. The number 20.0E6 is real, as is 20000000.0 . • A <pattern> is a contiguous sequence of one or more 0 , 1 , and X characters containing no spaces. For example, 001X00 and XX010X are legal. However, 100 X00 is not legal because of the embedded space. A low state is denoted by 0 , a high state is denoted by 1 , and a don’t-care value is denoted by X . • A <32-bit pattern> is a <pattern> with exactly 32 characters in its character sequence. • A <left bracket> is the left bracket character ([ ). • A <right bracket> is the right bracket character (] ). Lexical ambiguity exists in certain situations and has to be resolved by context. For example, a <pattern> that starts with an X has to be differentiated from a <VHDL identifi er> by context derived from the syntax. Similarly, a <pattern> that does not contain an X has to be differentiated from an integer such as 100 (one hundred). A.3.3 Commonly Used Syntactic Elements • A <port ID> identifi es a component signal that may be used to interface to exter- nal signals. A port may be dimensioned as a bit or a bit_vector . Subscripted names are allowed only when bit_vector -dimensioned port signals are used. <port ID>::= <port name> | <subscripted port name> <port name>::= <VHDL identifi er> <subscripted port name>::= <VHDL identifi er> ( <subscript> ) <subscript>::= <integer> • An <instruction name> is an instruction name defi ned in this standard or a name given to an instruction by the manufacturer of a component. <instruction name>::= BYPASS | CLAMP | EXTEST | HIGHZ | IDCODE | INTEST | PRELOAD | RUNBIST | SAMPLE | USERCODE | <VHDL identifi er> A.4 BSDL Syntax 497 A.4 BSDL Syntax The BSDL entity description must have the following

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