BSDL Syntax Specifications

Appendix A BSDL Syntax Speciﬁ cations

This Appendix is a condensed listing of 2001 BSDL lexicography and syntax. It does not include the myriad semantic rules found in the BSDL speciﬁ cation as provided by the IEEE [IEEE01 ]. This information may be helpful to someone contemplating writing a BSDL parser, or to someone needing a quick reference guide for BSDL syntax when writing a BSDL description. It is assumed the reader is familiar with formalized speciﬁ cation of language.

A.1 Conventions

All reserved words, predeﬁ ned words, and punctuation are shown in Courier New type within this document. VHDL reserved and predeﬁ ned words will be shown in lowercase letters, and BSDL reserved words will be shown in UPPERCASE letters. (BSDL itself is case-insensitive; this convention is adopted for descriptive clarity.)

A.2 Lexical Elements of BSDL

The lexical elements of BSDL are a subset and standard practice of those of VHDL as deﬁ ned in IEEE Std 1076-1993. The following sections enumerate the lexical elements needed to understand the BSDL language deﬁ nition.

A.2.1 Character Set

• Upper- and lowercase letters: A to Z and a to z (the language is not case sensitive).

• Digits: 0 –9. • Special characters: " & ‘ ( ) * , - . : ; < = > • Logical separators: The space character, horizontal tabulation, vertical tabulation, carriage return, line feed, and form feed.

A.2.2 Identiﬁ ers

Identifi ers are user-supplied names and reserved words functioning as names. Identifi ers start with a letter and may contain letters, digits, or the underscore character. For example, the following are valid identifi ers:

Boundary_Scan IEEE_Std_1149_1

There is no limit to the number of characters in an identiﬁ er. The underscore character (_ ) is not allowed as the last character in an identiﬁ er (by VHDL).

IEEE_STD_1149_ -- This is not a legal identiﬁ er.

Adjacent underscore characters (_ _ ) are not allowed.

A.2.3 BSDL Reserved Words

The identifi ers listed in this section are BSDL reserved words with a fi xed signifi - cance in the language. These identifi ers cannot be used for any other purpose in a BSDL description. For example, a reserved word cannot be used as an explicitly declared identifi er. BC_0 to BC_99 are variable names used in the Standard VHDL Package. Names BC_0 through BC_ 10 are used today, while BC_11 through BC_99 are reserved for future use. Similarly, the names STD_1149_1_1990 , STD_1149_1_1993 , STD_1149_1_1994 and STD_1149_1_2001 have been reserved, with the potential for new names to be added later. Therefore, avoid using identifi ers that start with “STD_1149_ ”.

AT_PINS INTERNAL BC_0 to BC_99 INTEST BIDIR INTEST _ EXECUTION BIDIR_IN KEEPER BIDIR_OUT LOW BOTH OBSERVE_ONLY BOUNDARY OBSERVING BOUNDARY_ LENGTH ONE BOUNDARY_ REGISTER OUTPUT2 A.2 Lexical Elements of BSDL 493

BSCAN_INST OUTPUT3 BSDL_EXTENSION PHYSICAL_PIN_ MAP BYPASS PI CAP PIN_ MAP CAP_DATA PIN_ MAP _STRING CAPTURES PO CELL_DATA PORT_ GROUPING CELL_INFO PRELOAD CELL_TYPE PULL0 CLAMP PULL1 CLOCK REGISTER_ ACCESS CLOCK_INFO RUNBIST CLOCK_LEVEL RUNBIST _ EXECUTION COMPLIANCE_ PATTERNS SAMPLE COMPONENT_ CONFORMANCE STD_1149_1_1990 CONTROL STD_1149_1_1993 CONTROLR STD_1149_1_1994 DESIGN_ WARNING STD_1149_1_2001 DEVICE_ID TAP_SCAN_ CLOCK DIFFERENTIAL_CURRENT TAP_SCAN_ IN DIFFERENTIAL_VOLTAGE TAP_SCAN_ MODE EXPECT_DATA TAP_SCAN_ OUT EXTEST TAP_SCAN_ RESET HIGHZ UPD ID_BITS USERCODE ID_STRING USERCODE _ REGISTER IDCODE WAIT_DURATION IDCODE _ REGISTER WEAK0 INPUT WEAK1 INSTRUCTION_ CAPTURE X INSTRUCTION_ LENGTH Z INSTRUCTION_ OPCODE ZERO INSTRUCTION_ PRIVATE

A.2.4 VHDL Reserved and Predeﬁ ned Words

The identifi ers listed below are called VHDL ( IEEE Standard 1076 -1993) reserved and predefi ned words with a fi xed signifi cance in the language. These identifi ers may not be used for any other purpose in a BSDL description. For example, a reserved word cannot be used as an explicitly declared identifi er. Reserved words shown in the list below in lowercase letters are part of the BSDL subset of VHDL. Those in uppercase letters are not part of BSDL, but should not be used as 494 A BSDL Syntax Specifi cations identifi ers. The latest edition of the VHDL standard [IEEE93b ] shall be consulted as the fi nal authority .

ABS GUARDED REGISTER ACCESS IF REJECT AFTER IMPURE REM ALIAS in REPORT all INERTIAL RETURN AND inout ROL ARCHITECTURE is ROR array LABEL SELECT ASSERT LIBRARY SEVERITY attribute linkage SHARED BEGIN LITERAL signal bit LOOP SLA bit_vector MAP SLL BLOCK MOD SRA body NAND SRL buffer NEW string BUS NEXT subtype CASE NOR THEN COMPONENT NOT to CONFIGURATION NULL TRANSPORT constant of true DISCONNECT ON type downto OPEN UNAFFECTED ELSE OR UNITS ELSIF OTHERS UNTIL end out use entity package VARIABLE EXIT port WAIT false positive WHEN FILE POSTPONED WHILE FOR PROCEDURE WITH FUNCTION PROCESS XNOR GENERATE PURE XOR generic range GROUP record

A.2.5 Strings

A string is deﬁ ned as a sequence of zero or more characters enclosed between quotation marks. A quotation mark character is not allowed within a string in BSDL. For example, A.3 Notes on Syntax Deﬁ nition 495

"Mary had a little lamb" -- Allowed "Fred said ""HELP""" -- Not allowed

Strings are used extensively in BSDL. Because many of the BSDL strings are potentially much longer than a single line, the concatenation operator & is used to break them into manageable pieces. For example,

"Jack be nimble," & " Jack be quick."

is a single string, identical to

"Jack be nimble, Jack be quick."

BSDL does not permit replacement of the quotation mark with any other character. A string literal must ﬁ t on one line since it is a lexical element.

A.2.6 Comments

Any text between a double dash (-- ) symbol and the end of a line is treated as a comment. The text is allowed to contain any characters allowed by VHDL. Comments syntactically terminate a line of a description. Comments may be interspersed with lexical elements. For example, the following represents a single VHDL string:

"This is" & -- An example of a string split by a comment " a single string"

A.3 Notes on Syntax Deﬁ nition

A.3.1 BNF Conventions

• Any item enclosed in chevrons (i.e., between the character “<” and the character “>”) is the name of a syntax item that will be defi ned in this appendix. • Items enclosed by braces (i.e., between the character “{” and the character “}”) may be omitted or included one or more times. • Items enclosed between square brackets (i.e., between the character “[” and the character “]”) may be omitted or included only one time. • Items enclosed between the symbols “→” and “←” may appear in any order. • Except with regard to case, text shown in Courier New type font has to be included exactly as it is presented in this appendix. • Alternative syntaxes are separated by a vertical bar (“|” ). • The symbol “::=” should be read as “is defi ned as.” Note that the non-boldface “::=” is only part of a BNF description; in the BSDL fi le, the boldface characters “ := ” are used to indicate assignment. 496 A BSDL Syntax Specifi cations

• White space (spaces, tabulation, carriage returns, etc.) is used in these BNF descriptions to enhance readability and is not part of the syntax. However, white space needed for resolving lexical ambiguity is required.

A.3.2 Lexical Atoms

• A is a valid identiﬁ er, chosen as a name for an item. • An is an unsigned VHDL integer made up of an unsigned numeric character sequence not containing an underscore (_) character and not using an exponent ﬁ eld. • A is a VHDL real number of the form . or . E all written contiguously without spaces or format effectors. Note 1E3 is not real because it does not contain a decimal point. The number 20.0E6 is real, as is 20000000.0 . • A is a contiguous sequence of one or more 0 , 1 , and X characters containing no spaces. For example, 001X00 and XX010X are legal. However, 100 X00 is not legal because of the embedded space. A low state is denoted by 0 , a high state is denoted by 1 , and a don’t-care value is denoted by X . • A <32-bit pattern> is a with exactly 32 characters in its character sequence. • A is the left bracket character ([ ). • A is the right bracket character (] ). Lexical ambiguity exists in certain situations and has to be resolved by context. For example, a that starts with an X has to be differentiated from a by context derived from the syntax. Similarly, a that does not contain an X has to be differentiated from an integer such as 100 (one hundred).

A.3.3 Commonly Used Syntactic Elements

• A identiﬁ es a component signal that may be used to interface to external signals. A port may be dimensioned as a bit or a bit_vector . Subscripted names are allowed only when bit_vector -dimensioned port signals are used.

::= | ::= ::= ( ) ::=

• An is an instruction name deﬁ ned in this standard or a name given to an instruction by the manufacturer of a component.

A.4 BSDL Syntax

The BSDL entity description must have the following structure:

::= entity is {} [] [] [] [] [] [] {} [] end ;

::=

::= generic (PHYSICAL_PIN_ MAP : string); | generic (PHYSICAL_PIN_ MAP : string := ); ::= " " ::= port ( {; } ); ::= : ::= { , } ::= in | out | buffer | inout | linkage ::= bit | bit_vector ( ) ::= to | downto ::= ::= ::= use .all ; ::= STD_1149_1_1990 | STD_1149_1_1994 | STD_1149_1_2001 | ::= 498 A BSDL Syntax Speciﬁ cations

::= use .all ; ::= ::= attribute COMPONENT_CONFORMANCE of : entity is ; ::= " " ::= STD_1149_1_1990 | STD_1149_1_1993 | STD_1149_1_2001 ::= ::= attribute PIN_MAP of : entity is PHYSICAL_PIN_ MAP ; ::= {} ::= constant : PIN_MAP _STRING:= ; ::= ::= " { , } " ::= : ::= | ( { , } ) ::= | ::= attribute PORT_GROUPING of : entity is ; ::= " " ::= { , } ::= ( ) ::= DIFFERENTIAL_VOLTAGE | DIFFERENTIAL_CURRENT ::= { , } ::= ( , ) ::= ::= ::= → [] ← ::= attribute TAP_SCAN_CLOCK of : signal is ( ); ::= attribute TAP_SCAN_IN of : signal is true; ::= attribute TAP_SCAN_MODE of : signal is true; ::= attribute TAP_SCAN_OUT of : signal is true; A.4 BSDL Syntax 499

::= attribute TAP_SCAN_RESET of : signal is true; ::= , ::= LOW | BOTH ::= attribute COMPLIANCE_PATTERNS of : entity is ; ::= " ( ) ( )" ::= { , } ::= { , } ::= [] ::= attribute INSTRUCTION_LENGTH of : entity is ; ::= attribute INSTRUCTION_OPCODE of : entity is ; ::= attribute INSTRUCTION_CAPTURE of : entity is ; ::= attribute INSTRUCTION_PRIVATE of : entity is ; ::= " { , } " ::= " " ::= { , } ::= " " ::= { , } ::= ( ) ::= → [] ← ::= attribute IDCODE _ REGISTER of : entity is <32-bit pattern list string> ; ::= attribute USERCODE _ REGISTER of : entity is <32-bit pattern list string> ; <32-bit pattern list string>::= " <32-bit pattern list> " 500 A BSDL Syntax Speciﬁ cations

<32-bit pattern list>::= <32-bit pattern> {, <32-bit pattern>} ::= attribute REGISTER_ACCESS of : entity is ; ::= " { , } " ::= ( ) ::= { , } ::= [ CAPTURES ] ::= BOUNDARY | BYPASS | DEVICE_ID | ::= ::= ::= attribute BOUNDARY_LENGTH of : entity is ; ::= attribute BOUNDARY_REGISTER of : entity is ; ::= " " ::= { , } ::= ( ) ::= ::= [ , ] ::= , , , ::= ::= | * ::= INPUT | OUTPUT2 | OUTPUT3 | CONTROL | CONTROLR | INTERNAL | CLOCK | BIDIR | OBSERVE_ONLY ::= 0 | 1 | X ::= , , ::= ::= 0 | 1 ::= Z | WEAK0 | WEAK1 | PULL0 | PULL1 | KEEPER ::= attribute RUNBIST _ EXECUTION of A.5 User Package Syntax 501

: entity is " "; ::= , , ::= WAIT_DURATION ( ) ::= | [ , ] ::= { , } ::= ::= ::= OBSERVING AT_PINS ::= HIGHZ | BOUNDARY ::= EXPECT_DATA ::= { } ::= 0 | 1 ::= attribute INTEST _ EXECUTION of : entity is " "; ::= , ::= { } ::= | ::= attribute : BSDL_EXTENSION; ::= attribute of : entity is ; ::= | ::= ::= ::= ::= attribute DESIGN_WARNING of : entity is ;

A.5 User Package Syntax

::= package is { } { } end ;

::= package body is 502 A BSDL Syntax Speciﬁ cations

{ } end ;

::= ::= constant : CELL_INFO; ::= ::= constant : CELL_INFO := ( ) ; ::= ::= { , } ::= ( , , ) ::= INPUT | OUTPUT2 | OUTPUT3 | INTERNAL | CONTROL | CONTROLR | CLOCK | BIDIR_IN | BIDIR_OUT | OBSERVE_ONLY ::= EXTEST | SAMPLE | INTEST ::= PI | PO | CAP | UPD | ZERO | ONE | X

A.6 1149.6 Extention Attribute Syntax

The 1149.6 extension contains some new attributes with a speciﬁ c syntax that needs to be recognized by tools that support 1149.6. An example is shown in Sect. 8.6.3 on page 331. This syntax is listed here:

::= → [] [] ← []

:: = attribute AIO_Component_Conformance of : entity is ; ::= " " ::= STD_1149_6_2003

:: = attribute AIO_EXTEST_Pulse_Execution of : entity is ; ::= " " A.6 1149.6 Extention Attribute Syntax 503

::= wait_duration ::= | ::=

:: = attribute AIO_EXTEST_Train_Execution of : entity is ; ::= " " ::= [ , ] ::= train ::= maximum_time ::=

:: = attribute AIO_Pin_Behavior of : entity is ; ::= " " ::= { ; } :: = [ : [ ][ ]] ::= { , } ::= [ ] [ ] ::= [ ] ::= ::= { , } ::= AC_Select = ::= LP_time = ::= HP_time = [ On_chip ] ::=

Appendix B 2013 BSDL Syntax Revisions

This Appendix is a compendium of changes to the 2001 version of BSDL lexicography and syntax which were introduced in the 2013 version of the 1149.1 standard. It does not include the myriad semantic rules found in the BSDL speciﬁ cation as provided by the IEEE [IEEE13 ]. This information supplements that found in Appendix A and follows the same conventions. It also completes the introductory information in Chap. 11 which serves to motivate why these changes exist.

B.1 Reserved Word Changes

There are two categories of reserved words in BSDL; ﬁ rst are those inherited from VHDL (see Sect. A.2.4 ) and second are those deﬁ ned by BSDL itself (see Sect. A.2.3 ).

B.1.1 VHDL Reserved Words

In Sect. A.2.4 there is a table of VHDL reserved words. These are divided into two groups with one group (in lowercase letters) being a set of reserved words from VHDL that have speciﬁ c meaning in BSDL. The second group (in uppercase letters) were other VHDL reserved words not adopted by BSDL. These were considered reserved anyway and BSDL code was not to use them, since that would prevent

© Springer International Publishing Switzerland 2016 505 K.P. Parker, The Boundary-Scan Handbook, DOI 10.1007/978-3-319-01174-5 506 B 2013 BSDL Syntax Revisions such code from being parsed by a VHDL tool. That is no longer the case with the 2013 release, so the only VHDL reserved words are shown in this abbreviated table.

All Entity Positive Array Generic Range Attribute In Record Bit Inout Signal Bit_vector Is String Body Of Subtype Buffer Others To Constant Out True Downto Package Type End Port Use

B.1.2 BSDL Reserved Words

In Sect. A.2.3 there is a table of BSDL reserved words. This list has been lengthened by adding the following 66 reserved words.

Broadcastfi eld Open0 Broadcastvalues Open1 Clamp_hold OpenX Clamp_release Power_0 Default Power_pos DelayPO Power_neg Domain Power_port_association Domain_external Pulse0 Domctrl Pulse1 Dompor Register_access ECID Register_assembly ECIDcode Register_association Expect0 Register_constraints Expect1 Register_fi elds Hierreset Register_mnemonics IC_reset Reset_select Init_data Resetval Init_run Segment Init_setup Segmux Init_setup_clamp Segsel Init_Status Segstart Linkage_buffer Selectmux Linkage_in Selectfi eld Linkage_inout Selectvalues Linkage_mechanical Shared B.1 Reserved Word Changes 507

Linkage_out TAPreset Mon Tie0 NoPI Tie1 NoPO TMP_Status Noretain TRSTreset NoUPD User One_hot Vref_in Open Vref_out

B.1.3 Numeric Literals

Appendix A lists several numeric literals: , , and <32-bit pattern> (see Sect. A.3.2 ). The 2013 revision of BSDL adds three new numeric literal types: • is a contiguous string starting with 0b or 0B , followed by one character from the set [01xX] and zero or more characters from the set [01xX_] . No spaces or format effectors1 may be embedded. • is a contiguous string starting with 0x or 0X , followed by one character from the set [0-9a-fA-F] followed by zero or more characters from the set [0-9a-fA-F_] . No spaces or format effectors may be embedded. • is an unsigned contiguous string of characters from the set [0-9] , that does not have ‘0 ’ for the most signifi cant (leftmost) digit of a multi- digit number, contains no spaces or format effectors, and has a binary representa- tion that fi ts within a 32-bit binary fi eld. 2

B.1.4 Identiﬁ ers

Identiﬁ ers are user-supplied names with the syntax token of (see Sect. A.2.2 ). The 2013 revision of BSDL adds the concept of a and it is formed according a list of requirements. It also deﬁ nes . A any combination of alphabetic characters (case insensitive), digits and certain special characters such that: • It contains at least one alphabetic character. • It cannot be resolved to a , , , or value. • It is not the single character “U” (or “u”).

1 Format effectors include carriage returns, tab characters, line feeds, page ejects, etc. 2 This means the decimal number must be less than or equal to 2 32 -1, which is 4,294,967,295. 508 B 2013 BSDL Syntax Revisions

• It cannot start with, or contain the BSDL comment characters, that is, double- dash “--”. • It may include these special characters: – At-sign (@) – Asterisk (*) – Underscore (_) – Minus sign (−) – Plus sign (+) – Vertical bar (|) – Percent sign (%) – Tilde (~) – Period (.) • It may be a valid . A is any combination of letters (case insensitive), digits and the underscore character, not starting with a digit. A valid may serve as a . (With the exception of case insensitivity, a follows the rules for Verilog identifi ers. 3 ) Prefi x identifi ers are used in descriptions (see Sect. 11.4.20) and certain PDL statements (see Sect. 11.5 ).

B.1.5 Information Tags

An is a nearly free-form string of zero or more characters with very few restrictions. They are used to convey descriptive information, more like comment text rather than strict syntax. An is: • Zero or more characters contained between enclosing chevrons (< >). • The enclosed characters may not include the right chevron (>), quotation mark (“), double-dash (--) or format effectors. An cannot contain a BSDL comment and though it appears in BSDL strings, it cannot itself contain a quotation mark. Since BSDL strings can be expressed as concatenated smaller strings, a long information tag can be broken up with the string concatenation method.

B.1.6 Port Types

The deﬁ nition of is greatly expanded. These new types were added to replace the LINKAGE type: LINKAGE_BUFFER , LINKAGE_IN , LINKAGE_ INOUT , LINKAGE_MECHANICAL , LINKAGE_OUT , POWER_0 ,

3 Verilog is a hardware description language alternative to VHDL in common use. B.2 BSDL Syntax 509

POWER_NEG , POWER_POS , VREF_IN and VREF_OUT . See 11.4.7 for a discussion of what these terms mean.

B.1.7 Pin Description

In Sect. A.4 you will see pins identiﬁ ed by tokens, and these can be either values, or values, reﬂ ecting pins that are numbered (33, 52, etc.), or have alphanumeric names like G13 or B7. This has been expanded in the 2013 revision so has been recast as and we see this syntax:

::= | OPEN | TIE0 | TIE1 ::= |

These keywords allow a bit more descriptive information to be associated with ports that touch the Boundary register, but are not bonded out of the package in some of the packaging options. The details of pin descriptions are given in Sect. 11.4.11 .

B.1.8 Instructions

In Sect. A.3.3 we see a deﬁ nition of . This has been expanded with the 2013 release of BSDL.

The new instructions are only deﬁ ned for the 2013 release, so the conformance identiﬁ cation must be STD_1149_1_2013 for them to appear.

B.2 BSDL Syntax

A BSDL entity description documents an IC at the die level, and also includes information about one or more packaging alternatives, including just a bare die, if it is ever operated as such.4 The 2013 revision of BSDL added a number of new descriptive attributes to the language, and made some other changes. Those are shown

4 For example, if the Boundary-Scan circuitry is tested on an IC tester before packaging, the die pad mapping will be needed. 510 B 2013 BSDL Syntax Revisions below and are commented on the right side of the page. The comments are not part of the description. The BSDL entity description must have the following structure:

::= entity is --changed at 2013 {} --changed at 2013 [] [] [] [] --changed at 2013 --changed at 2013 [] [] [] --added at 2013 {} --added at 2013 {} --added at 2013 {} --added at 2013 {} --added at 2013 {} --added at 2013 {} --added at 2013 {} [] end ;

The changed or added syntax structures are described in the remainder of this section.

B.2.1 Logical Port Description

The syntax has undergone a few simple changes, in the area of :

::= port { } ::= ::= { } B.2 BSDL Syntax 511

The pin type assignments are expanded. See Sect. 11.4.7 for their meanings.

B.2.2 Device Package Mappings

Some new detail is provided by the area of BSDL. This is information and is described in Sect. 11.4.11 .

::= ::= attribute PIN_MAP of entity is PHYSICAL_PIN_MAP ::= { } ::= constant PIN_MAP_STRING := ::= ::= { } ::= ::= | ::= { } ::= | OPEN | TIE0 | TIE1 ::= |

B.2.3 Register Access Description

The original

::= attribute REGISTER_ACCESS of entity is 512 B 2013 BSDL Syntax Revisions

::= { } ::= ::= { } ::= [ CAPTURES ] :: = | | ::= BOUNDARY | BYPASS | DEVICE_ID | TMP_STATUS :: = [ ] ::= ECID | INIT_DATA | INIT_STATUS | RESET_SELECT ::= [ ] ::= |

B.2.4 Boundary-Scan Register Description

The Boundary-Scan register syntax has been expanded to describe both the pre- 2013 “static” or “ﬁ xed” register and the new “segmented” register form. More descriptive detail for individual cells is also included, as discussed in Sect. 11.4.13 . The syntax of Boundary register description starts out like this:

::= <fi xed boundary stmts> | <fi xed boundary stmts> ::= ::= Here we see the two forms, fi xed and segmented. Each has a length statement followed by the register description, either fi xed or segmented. First let’s look at the fi xed form, discussed in Sect. 11.4.14 .

::= attribute BOUNDARY_LENGTH of entity is ::= ::= attribute BOUNDARY_REGISTER of entity is ::= ::= { } B.2 BSDL Syntax 513

::= ::= ::= [ ] ::= ::= ::= | ::= INPUT | OUTPUT2 | OUTPUT3 | CONTROL | CONTROLR | INTERNAL | CLOCK | BIDIR | OBSERVE_ONLY ::= 0 | 1 | X ::= | :: = EXTERN0 | EXTERN1 | PULL0 | PULL1 | OPEN0 | OPEN1 | KEEPER | OPENX | EXPECT1 | EXPECT0 ::= ::= ::= 0 | 1 ::= WEAK0 | WEAK1 | PULL0 | PULL1 | OPEN0 | OPEN1 | KEEPER | Z Note above that both and have expanded lists of keywords, as discussed in Sect. 11.4.13 . Also note that a token called has been inserted into the syntax. This accounts for the new that may appear in a cell entry. Next, here is the syntax for segmented Boundary register description, discussed in Sect. 11.4.15 . ::= attribute ASSEMBLED_BOUNDARY_LENGTH of entity is ::= ::= { } ::= attribute BOUNDARY_SEGMENT of entity is ::= { } ::= < boundary segment name > ::= ::= 514 B 2013 BSDL Syntax Revisions

Note that and deﬁ nitions are given up in the ﬁ xed register syntax, and is the same. The length statement differs in that it gives two numbers for the Boundary register length, a “reset length” followed by a “register length”. This is also discussed in Sect. 11.4.15 .

B.2.5 System Clock Description

In some cases, an instruction will not work without a system clock being supplied for its operation. The 1149.1 working group has provided a way in BSDL to describe where such clocking is needed. This is the new SYSCLOCK_REQUIREMENTS attribute. Here is the syntax:

::= attribute SYSCLOCK_REQUIREMENTS of is ::= { < system clock requirement> } ::= ::= ::= ::= { } ::= RUNBIST | INTEST | INIT_SETUP | INIT_RUN | INIT_SETUP_CLAMP | ECIDCODE | IC_RESET |

The must refer to a port with an input capability (IN, INOUT, LINKAGE_IN or LINKAGE_INOUT) and if it is a differential clock input pair, the representative port is identiﬁ ed. Note that if the compliance level of the device is pre-2013, then only RUNBIST or INTEST may be the clocked instruction. If the device is a 2013-compliant device, then more standard instructions are allowed (see above) but not those like EXTEST, BYPASS, SAMPLE, PRELOAD, etc. These instructions use only TCK for clocking. Designer-speciﬁ ed instructions that require clocking are provided by their . See more discussion and an example in Sect. 11.4.17 .

B.2.6 Register Mnemonics Description

Register Mnemonics are a way in BSDL to associate names (called , see Sect. A.1.4) with numeric bit patterns (binary, hexadecimal, or decimal) and also attach an optional descriptive (see Sect. A.1.5) with them. See usage detail and examples in Sect. 11.4.18 . B.2 BSDL Syntax 515

This is the register mnemonic description syntax:

::= attribute REGISTER_MNEMONICS of is ::= | ::= entity ::= package ::= { } ::= ::= ::= { } ::= [ ] ::= | | | others

A terms, each consisting of a group name followed by a parentheses-enclosed list of comma-separated terms. Each such associates a with a followed, optionally, with an . All elements must be unique within its containing entity or package description. All elements that appear in a must be unique within that list, but duplicates could appear across multiple elements if more than one exists. Each must contain at least one containing a , or . This means you cannot have a containing only one which contains the keyword others . When listing patterns in a , regardless of their being expressed in binary, hex or decimal, they must be unique; however, all possible patterns do not need to be speciﬁ ed. Note that “X” bits may exist in (only) a binary pattern. This indicates that bit position may have either a ‘0’ or ‘1’ bit present, implying multiple patterns. When such a binary pattern is used, all of its implied patterns belong to the associated and must not be found in another portion of the . Unused pattern values may be referenced with the others keyword, and if this keyword is listed in a , it must be the last one listed. When a is associated with the others keyword, then all the patterns not otherwise speciﬁ ed earlier in the list have that and that (optional) . 516 B 2013 BSDL Syntax Revisions

B.2.7 Register Fields Description

The register fi elds description is used to describe a data register and any segments that make it up. The overall length of a register is given, followed by a listing of its segments, also named and with lengths provided. Note that not all bits of the data register may be described within some segment, that is, some may be left undefi ned. The syntax is given next, but, is divided into two portions. The fi rst portion is unique to the register fi elds attribute. The second is used by both the register fi elds and register assembly attribute (see Sect. A.2.8) and it provides defi nitions of items like , and . The fi rst syntax portion is:

::= attribute REGISTER_FIELDS of is ::= { } ::= ::= | ::= BOUNDARY | BYPASS | DEVICE_ID | TMP_STATUS | ECID | INIT_DATA | INIT_STATUS | RESET_SELECT | ::= ::= ::= ::= { } ::= | ::= <fi eld length> is ::= <fi eld name> ::= { } <fi eld name>::= <fi eld length>::= ::= { <fi eld options> } <fi eld options> ::= | | ::= [ { } ] ::= | ::= PREFIX ::= |

The defi nition of is found in Sect. A.4 . The defi nition of is found in Sect. A.1.4. When a is that defi ned by the stan- B.2 BSDL Syntax 517 dard (e.g., DEVICE_ID, BOUNDARY, etc.) then the value of must equal the length of the register as already provided. Any bit number listed in a must be less than the for that . The bit number zero is closest to TDO. When one or more elements are fi rst found in a , then they must be listed in numerical order starting with Prefi x 0. If a is found in a subsequent , then it will overwrite the previous with the same number and erase all statements with larger numbers. If a is given with a name of that will erase all previously defi ned prefi xes. When an is encountered and there are defi ned prefi xes, then that name will have all of the prefi xes prepended in their numerically ascending order, separated with ‘.’ characters. All elements must be unique within a BSDL entity or package. When a <fi eld length> is zero, then the associated must be empty “()”. A test register bit number may be referenced in more than one , but within a given , it may only appear once. See examples in Sect. 11.4.20 . Next is the second portion of syntax, shared with the register assembly attribute:

B.2.8 Register Assembly Description

The register assembly description is used to defi ne registers or segments of registers by the concatenation of segments and/or fi elds in a specifi ed order. Yes, this attribute is complex. The syntax for this is as follows:

::= attribute REGISTER_ASSEMBLY of is ::= { } ::= ::= { } ::= | <fi eld and options> | | | | ::= { <fi eld assignments> } ::= is [ PACKAGE ] ::= | ::= ::= ARRAY ::= <fi eld assignments> ::= <fi eld value assignment> | <fi eld reset assignment> | <fi eld domain assignment> | <fi eld selection assignment> <fi eld value assignment> ::= [ <fi eld ident> ] <fi eld reset assignment> ::= [ <fi eld ident> ] <fi eld domain assignment> ::= [ <fi eld ident> ] <fi eld ident> ::= { } <fi eld name> ::= | ::= <fi eld and options>::= <fi eld name> <fi eld length> { <fi eld options> } ::= | ::= ::= B.2 BSDL Syntax 519

::= SELECTMUX { } <fi eld selection assignment> ::= | <fi eld selection assignment> ::= [ ] ::= SELECTFIELD <fi eld reference> <fi eld reference> ::= { } <fi eld name> ::= SELECTVALUES { } ::= <fi eld value> { <fi eld value> } <fi eld value> ::= | | | ::= BROADCASTFIELD <fi eld reference> ::= BROADCASTVALUES { } ::= { } <fi eld value> { <fi eld value> } ::= is [ PACKAGE ] < boundary segment name > ::= USING ::= | ::= { }

The are ordered with the fi rst being closest to TDI and the last being closest to TDO. If the is that of a standard register (e.g., Device_ID) then the length must be what is specifi ed in the standard (e.g., 32) or what has been described before in a register access statement. In the case of the Boundary register, it must match either the length given in or the minimum length given in an . Otherwise, the specifi ed length is used for a register that has a deferred length specifi cation [*]. For user registers specifi ed in a the length shall be the sum of the lengths of the non-excludable segments in the . 520 B 2013 BSDL Syntax Revisions

In a <fi eld and options> segment, the <fi eld name> must be unique in any . Also, all and elements within a must be unique within an entity or package. A in an must be defi ned in a or contained in the current entity or package, or in a package the given by the most recent “USING” statement. Between a SEGSEL (or SEGSTART5 ) element and a SEGMUX element that are associated with the same segment , all register assembly elements listed are excludable as a unit. Between a SELECTMUX element and a SELECTFIELD element, all register assembly elements listed are members of a parallel group of segments, of which only one is selected by the SELECTVALUES element to drive out towards TDO. Optionally, following the selection elements there may be a BROADCASTFIELD and BROADCASTVALUES element pair that enumerate which of the parallel segments, receive TDI data in parallel for a given selection value. In both cases, all segments mentioned between SELECTMUX and SELECTFIELD must appear as selectable segments in the SELECTVALUE and BROADCASTVALUE lists. When multiple statements have the same then all associated specifi cation must not have any duplicated indices, and all indices must be present or implied within the total range specifi cation. The defi nition of the <fi eld reference> register used in a SELECTFIELD or BROADCASTFIELD element must have a RESETVAL specifi cation, so the selected segment upon reset is known. When the register being assembled is the Boundary register, then it must be com- posed only of instances of DOMCTRL, SEGSEL, SEGSTART or SEGMUX register fi elds, which are defi ned in the standard package STD_1149_1_2013 (see Sect. A.3 ), or defi ned elements defi ned found in a Boundary_Segment attribute (see Sect. A.2.4 ). Note that any excludable segment in a Boundary register must have a DOMCTRL and SEGSEL fi eld associated with that segment in the same register assembly list. This does not preclude having other such controls in (say) the Init_Data register, but these are duplicates.6 Any excludable segments in the Init_Data register must be controlled by DOMCTRL and SEGSEL fi elds in the Init_Data register. All excludable segments in a public TDR (standard or design-specifi c) must have DOMCTRL and SEGSEL fi elds in that same TDR, or, in another public TDR that is not the Boundary register. This means all such exclusion controls for public registers must be visible (public).

5 SEGSEL represents a 1-bit register cell that directly precedes an excludable segment, In the case where this bit exists in a different register, then SEGSTART, a zero-length segment indicator starts the excludable segment. All must have the same < association name > . 6 In effect, the duplicate bits are OR-ed with those in the Boundary register to control the power/ exclusion mechanism. Thus, to exclude a segment, you should be aware of any duplicate bits else- where and manage them along with the bits in the Boundary register. B.2 BSDL Syntax 521

The construct is used to point to a specifi c name (, , or ) to remove any ambiguity when there may be identical names a more than one hierarchical level. A is available to shorten name references by being a prefi x prepended to a name. The “USING (-)” form erases an existing prefi x. Note that the 2013 revision of BSDL can be used to describe an older component, but since the concept of domains and excludable segments were not supported before 2013, a register assembly for a pre-2013 component may not contain DOMCTRL, SEGSEL, SEGSTART or SEGMUX fi elds. This is known from the statement (see Sect. A.4 referring to a pre-2013 level of conformance.

B.2.9 Register Constraints Description

The register constraints attribute allows the description of register contents that should be avoided—for example, where two domain control cells that turn on power to two domains should not be both turned on at the same time (see example in Sect. 11.4.22) because the hardware itself cannot support this. Here is the register constraints syntax:

::= attribute REGISTER_CONSTRAINTS of is ::= { } ::= ::= | entity | package ::= { } ::= error | warning | info ::= | ::= | | <ﬁ eld reference> | ::= ::= | | ::= ::= ::= ::= 522 B 2013 BSDL Syntax Revisions

::= | | | | | | | | | | | | | | | | | | ::= | | | ::= [ [ PACKAGE ] ]

The logical expression formulation is a subset adopted from section Sect. 11.2 of SystemVerilog [IEEE12a ]. The defi nition of is found in Sect. A.2.6. A of PACKAGE or ENTITY must match the type of . The <fi eld reference> must be a previously defi ned register or register fi eld, as provided by the standard (e.g., Boundary or ECID) or by a register access, register fi elds or register assembly defi nition. A must resolve to previously defi ned mnemonic value given in a register mnemonics defi nition. A must contain at least one <fi eld reference>. (For example, the expression “2 < 3” does not meet this requirement.) The fi eld length of a <fi eld reference> must be greater than zero. Operator meanings, precedence and symbols are given in below in Table A.1 . The logical value of zero if FALSE, and the logical value of a non-zero number is TRUE. Note a binary number with ‘x’ bits is considered non-zero. Arithmetic operators do not operate on ‘x’ bits, only ‘1’ and ‘0’ bits are allowed in operands. Operators of higher precedence (that is, lower precedence number) are evaluated before those of lower precedence. Operators of the same precedence are evaluated left-to-right.

B.2.10 Register and Power Port Association Description

These two new optional attributes are described together since they share some syntax deﬁ nitions and rules of use. These attributes allow ports of an IC to have associated information that may be quite helpful during test debugging or defect diagnosis.

::= attribute REGISTER_ASSOCIATION of is ::= B.2 BSDL Syntax 523

Table A.1 Constraint operator deﬁ nitions Precedence Operator token Operator Type (comments) 1 ! Logical ~ Bit-wise One_hot Logical result, true if exactly one operand bit is ‘1’ (Binds to nested expression on its right) 2 ** Arithmetic 3 * Arithmetic / % 4 + Arithmetic − 5 << Arithmetic (Right operand is the >> number of shifts) 6 < Arithmetic > (Result is logical) <= => 7 == Bit-wise (Result is logical) != 8 & Bit-wise 9 ^ Bit-wise 10 | Bit-wise 11 && Logical 12 || Logical

{ } ::= { } ::= <ﬁ eld or instance name> [ < index > ] <ﬁ eld or instance name> ::= | | | ::= | | | | ::= port ::= { } ::= info { } ::= sysclock { } ::= user 524 B 2013 BSDL Syntax Revisions

::= ::= | ::= { } ::= { } ::= unit ::= [ ] [ ] ::= ::= ::= ::= ::= attribute POWER_PORT_ASSOCIATION of is ::= { } ::= ::=

Any fi eld reference must be a previously defi ned register or register fi eld, as provided by the standard (e.g., Boundary or ECID) or by a register access, register fi elds or register assembly defi nition. A <fi eld or instance name> must appear only once in a . The value of an integer associated with a <fi eld name> must be less than the <fi eld length> of the register fi eld (see Sect. A.2.7). When an is associated with a , it must be a valid index into the of an described in a Register_ Assembly attribute. An can only be associated with a when that was defi ned as a bit_vector and the index is a valid member of the of the . All elements listed in a must be previously defi ned in a (see Sect. A.4 ), and shall appear only once in that list. An contains, within parenthesis, either a single entry which is associated with all of the bits contained in a , or it must contain a comma-separated list of entries with length equal to the number of bits contained in the , associated with those bits in TDI-to-TDO order. Any in a must have been identifi ed as a system clock in a SYSCLOCK_REQUIREMENTS attribute (see Sect. A.2.5 ). Each must be unique within a . B.3 The STD_1149_1_2013 Standard Package 525

A appearing in an allows the naming of a , which is a of 22 characters as defi ned in section Sect. 4.11 of IEEE Std 1451.0-2007 [IEEE07 ]. Any supplied must be a valid fi le (fi le://…) or Internet (http://…) URL locating a transducer electronic data sheet (TED) as defi ned in IEEE Std 1451. A must be a in the with a of POWER_POS, POWER_NEG, POWER_0 or VREF_IN.

B.3 The STD_1149_1_2013 Standard Package

The 2013 BSDL standard package has some changes from the previous (2001) version. The package comes in two sections, the “package” and then the “package body”. The 2013 package body contains cell descriptions that are very similar to the previous package body so to conserve space, refer to the 2001 package body seen in Sect. 2.6.1 for those cell descriptions. The ﬁ rst section in the standard package is essentially a set of data and type declarations. These were used to support VHDL compilers so that they could understand data structures in BSDL. There are additions that come with the 2013 version. These are shown next. Those statements that have been added by the 2013 revision are commented at the right side of the page.

-- STD_1149_1_2013 BSDL Package and Package Body -- -- source : IEEE Std 1149.1-2013, B.9 -- -- NOTE-Where ﬁ gures from the standard are cited, -- the sufﬁ x ‘c’ denotes a control cell, and ‘d’ -- denotes a data cell. -- package STD_1149_1_2013 is -- Give component conformance declaration. attribute COMPONENT_CONFORMANCE : string; -- Give pin mapping declarations attribute PIN_MAP : string; subtype PIN_MAP_STRING is string; -- Give TAP control declarations type CLOCK_LEVEL is (LOW, BOTH); type CLOCK_INFO is record FREQ : real; LEVEL: CLOCK_LEVEL; end record; attribute TAP_SCAN_IN : boolean; attribute TAP_SCAN_OUT : boolean; 526 B 2013 BSDL Syntax Revisions

attribute TAP_SCAN_CLOCK: CLOCK_INFO; attribute TAP_SCAN_MODE : boolean; attribute TAP_SCAN_RESET: boolean; -- Give instruction register declarations attribute INSTRUCTION_LENGTH : integer; attribute INSTRUCTION_OPCODE : string; attribute INSTRUCTION_CAPTURE : string; attribute INSTRUCTION_PRIVATE : string; -- Give ID and USER code declarations type ID_BITS is ('0', '1', 'x', 'X'); type ID_STRING is array (31 downto θ) of ID_BITS; attribute IDCODE_REGISTER : ID_STRING; attribute USERCODE_REGISTER: ID_STRING; -- Give register declarations attribute REGISTER_ACCESS : string; attribute REGISTER_MNEMONICS : string; attribute REGISTER_FIELDS : string; attribute REGISTER_ASSEMBLY : string; attribute REGISTER_CONSTRAINTS : string; attribute POWER_PORT_ASSOCIATION : string; attribute REGISTER_ASSOCIATION : string; -- Give boundary cell declarations type BSCAN_INST is (EXTEST, SAMPLE, INTEST); type CELL_TYPE is (INPUT, INTERNAL, CLOCK, OBSERVE_ONLY, CONTROL, CONTROLR, OUTPUT2, OUTPUT3, BIDIR_IN, BIDIR_OUT); type CAP_DATA is (PI, PO, UPD, CAP, X, ZERO, ONE); type CELL_DATA is record CT : CELL_TYPE; I : BSCAN_INST; CD : CAP_DATA; end record; type CELL_INFO is array (positive range <>) of CELL_DATA; -- Boundary cell deferred constants (see package body) constant BC_0 : CELL_INFO; constant BC_1 : CELL_INFO; constant BC_2 : CELL_INFO; constant BC_3 : CELL_INFO; constant BC_4 : CELL_INFO; constant BC_5 : CELL_INFO; -- BC_6 omitted in 2013 constant BC_7 : CELL_INFO; constant BC_8 : CELL_INFO; constant BC_9 : CELL_INFO; constant BC_10 : CELL_INFO; -- Boundary-scan register declarations attribute BOUNDARY_LENGTH : integer; B.3 The STD_1149_1_2013 Standard Package 527

attribute BOUNDARY_REGISTER : string; attribute ASSEMBLED_BOUNDARY_LENGTH : array (0 to 1) of integer; -- added 2013 attribute BOUNDARY_SEGMENT : string; -- added 2013 -- Miscellaneous attribute PORT_GROUPING : string; attribute RUNBIST_EXECUTION : string; attribute INTEST_EXECUTION : string; attribute SYSCLOCK_REQUIREMENTS : string; -- added 2013 subtype BSDL_EXTENSION is string; attribute COMPLIANCE_PATTERNS : string; attribute DESIGN_WARNING : string; end STD_1149_1_2013; -- End of 1149.1-2013 Package

The standard package body follows here. The cell descriptions are substantially unchanged from 2001 (see Sect. 2.6.1 ). These are omitted for brevity.

package body STD_1149_1_2013 is --Standard boundary cells

… cell descriptions omitted … … the next two attributes added at 2013 …

attribute REGISTER_MNEMONICS of STD_1149_1_2013:package is "STD_MUX(Include (1) ,"& "Exclude (0) ),"& "STD_POWER(On (1) , " & " Off (0) ), " & "STD_DOMSET(Override (1) , " & "Normal (0) ) ";

attribute REGISTER_FIELDS of STD_1149_1_2013:package is "DOMCTRL[1] ((DOMCTRL[1] IS (0) MON " & " DEFAULT(STD_DOMSET(Normal)) " & " RESETVAL(STD_DOMSET(Normal))) "& -- A reset type must be speciﬁ ed where this -- is instantiated ")," & "SEGSEL[1] ((SEGSEL[1] IS (0) DELAYPO " & " DEFAULT(STD_MUX(Exclude)) "& " RESETVAL(STD_MUX(Exclude)) "& -- A reset type must be speciﬁ ed where this -- is instantiated " CAPTURES(STD_POWER(-)) ))," & "SEGMUX[0] ((SEGMUX [0] IS ()) )," & "SEGSTART[0] ((SEGSTART [0] IS ()) )"; end STD_1149_1_2013; -- End of IEEE STD 1149.1-2013 -- Package Body 528 B 2013 BSDL Syntax Revisions

B.4 User Package Syntax

The syntax for a user package is expanded to account for nesting of IP packages and register mnemonics, ﬁ elds, assembly, constraints and association descriptions. The syntax below has comment in the right sides of lines that are added by the 2013 revision. (These comments are not part of the description.)

::=

::= package is { } { } end ; ::= package body is { } --added 2013 { } { } --added 2013 { } --added 2013 { } --added 2013 { } --added 2013 { } --added 2013 [ ] --added 2013 end ;

The various register descriptions used above are deﬁ ned in this Appendix. The addition of a design warning inside a user package will allow IP providers to alert their users to any special considerations their IP requires. B.5 Modiﬁ ed 1149.6 Extention Attribute Syntax 529

B.5 Modiﬁ ed 1149.6 Extention Attribute Syntax

The 1149.6 extension contains syntax that defi nes 1149.6 attributes. This syntax may appear in the extension area of an entity (chip) description, or in the extension area of a user package. Note that the two extensions differ in that for an entity extension, the syntax may not appear, and in a user package extension, a may not appear. Both of these items appear in the following syntax description since they make use of some common elements. Three of the fi ve statements are identical to the 2003 version and the comments point to their defi nition in Sect. A.6 .

::= (see Sect. A.6 ) [] (see Sect. A.6 ) [] (see Sect. A.6 ) [] (see Sect. A.5.1) [] (see Sect. A.5.2)

The value of a conformance identiﬁ cation has been expanded in 2015 to have two values: STD_1149_6_2003 and STD_1149_6_2015 . Note that when conformance is claimed for the 2015 level, then the conformance attribute of the entity BSDL must be STD_1149_1_2013 or later. There is a restriction for Extest_Pulse descriptions that appear in a user package; the clock speciﬁ cation refers to a time only, not a , since ports are not known at the package level.

B.5.1 Pin Behavior Description (Entity)

AIO Pin behavior at the entity level is described by an AIO_Pin_Behavior attribute. The documentation of the AC parameters of a pin are given in Sect. A.5.3. Note that a pin behavior description may reference “port links”, which are described by a port link behavior description (see Sect. A.5.2) in a package referenced in a BSDL use statement. Here is the syntax for pin behavior description.

:: = attribute AIO_Pin_Behavior of < entity target > is < quote > < quote > < semicolon > ::= { } ::= < colon > [ ] ::= { < comma > } ::= [ ] 530 B 2013 BSDL Syntax Revisions

::= < port name > | | ::= < port name > < left paren > < intege r> < right paren > ::= < port name > < left paren > < range > < right paren > ::= < left bracket > < right bracket > ::= { < comma > < cell number > } ::= [ < boundary segment name > < colon > ] < cell number > ::= AC_Select ::= | NOTE— The deﬁ nition of is given in A.5.3.

::= [ PACKAGE < package hierarchy > ] ::= { < comma > } ::= [ ] NOTE— The element is deﬁ ned in A.5.3

::= | | ::= < left paren > < integer > < right paren > ::= < left paren > < range > < right paren > ::= < VHDL identiﬁ er >

See discussion about Pin Behavior Description in Sect. 12.3.5 .

B.5.2 Port Link Behavior Description (Package)

AIO Port Link behavior at the package level is described by an AIO_Port_Behavior attribute. The documentation of the AC parameters of a port link is given in Sect. A.5.3. Here is the syntax for port link behavior description.

:: = attribute AIO_Port_ Behavior of is ::= port_link_list { } ::= B.5 Modiﬁ ed 1149.6 Extention Attribute Syntax 531

::= { } ::= ::= in | buffer | out | inout ::= { } ::=

NOTE— The deﬁ nition of is given in Sect. A.5.3.

::= { } ::= | |

NOTE – The deﬁ nitions of , and were given above in Sect. A.5.1. See discussion about Port Behavior Description in Sect. 12.3.6 .

B.5.3 AC Parameters Description

AC parameters document the characteristics of AC pin drivers or test receivers that may be important to board test debugging and efﬁ cacy, and diagnostic processing. In the pre-2015 years, we did not have this information in machine readable form and if a test engineer was having trouble debugging a test, it may have been due to a mismatch of AC parameters that he might have found out about by reading some obscure data sheet. Now these are brought out into view in BSDL, and in principle, some debugging can even be enhanced automatically, with software able to look at drivers and attached receivers and see if any problematic AC parameter mismatches are possible. This is even more important as we see more driver/receiver parameters than are programmable—are they programmed to be compatible? AC parameter syntax appears below. Note the numerous keywords—these are explained in Sect. 12.3.2 .

[Agra88] “Test Generation for VLSI Chips”, V. D. Agrawal and S. C. Seth, IEEE Computer Society Press , Los Alamitos CA, 1988 [Albe01] “A Practical Guide to Combining ICT and Boundary-Scan Testing”, A. Albee, Proceedings, International Test Conference , Baltimore MD, pp 487–494, Oct 2001 [AMD91] “Am29030 and Am29035 Microprocessors User's Manual and Data Sheet”, Advanced Micro Devices, Inc. 1991 [Avra87] “A VHSIC ETM-Bus Compatible Test and Maintenance Interface”, L. Avra, Proceedings, International Test Conference , pp 964–971, Washington DC, 1987 [Ball89] “Board-Level Boundary-Scan: Regaining Observability with an Additional IC”, W. D. Ballew and L. Streb, Proceedings, International Test Conference, pp 182–189, Washington DC, Aug 1989 [Barr00] “End-to-End Testing for Boards and Systems Using Boundary-Scan”, R. Barr and E. Wallace, Proceedings, International Test Conference, Atlantic City NJ, pp 585– 591, Oct 2000 [Been85] “Systematic and Structured Methods of Digital Board Testing”, F. P. M. Beenker, Proceedings, International Test Conference , pp 380–385, Philadelphia, Nov 1985 [Blee93] “Boundary-Scan Test: A Practical Approach”, H. Bleeker, P. van den Eijnden and F. de Jong, Kluwer Academic Publishers, Norwell MA, 1993 [Breu88] “A Test and Maintenance Controller for a Module Containing Testable Chips”, M. A. Breuer and J. C. Lien, Proceedings, International Test Conference, Washington DC, pp 502–513, 1988 [Bruc91] “Implementing 1149.1 on CMOS Microprocessors”, W. C. Bruce, M. G. Gallup, G. Giles and T. Munns, Proceedings, International Test Conference, Nashville TN, pp 879–886, Oct 1991 [Bull87] “Designing SMT Boards for In-Circuit Testability”, M. Bullock, Proceedings, International Test Conference , pp 606–613, Washington DC, Sept 1987 [Bush84] “Measuring Thermal Rises Due to Digital Device Overdriving”, G. S. Bushanam et al, Proceedings, International Test Conference , pp 400–407, Philadelphia PA. Oct 1984 [Cald92] “Is IEEE 1149.1 Boundary-Scan Cost Effective: A Simple Case Study”, B. Caldwell, T. Langford, Proceedings, International Test Conference, pp 106–109, Baltimore MD, Sept 1992 [Chil91] “Using Boundary-Scan Description Language in Design”, D. Chiles and J. DeJaco, Proceedings, International Test Conference , pp 865–868, Nashville TN. Oct 1991 [Chun01] “AC-JTAG: Empowering JTAG Beyond Testing DC Nets”, S. Chung, S. Baeg, Proceedings, International Test Conference , pp 30–37, Baltimore MD, Oct 2001

[Clar10] “Solutions for Undetected Shorts on IEEE 1149.1 Self-Monitoring Pins”, Clark, C. J., Dubberke, D., Parker, K. P., Tuthill, B., Proceedings, International Test Conference , Paper 19.1, Austin TX, Oct 2010 [Cogs02] “A Structured Graphical Tool for Analyzing Boundary-Scan Violations”, M. Cogswell, S. Mardhani, K. Melocco and H. Arora, Proceedings, International Test Conference , Baltimore MD, 755–762, Oct 2002 [Coom95] “Printed Circuits Handbook, 5th Edition”, C. F. Coombs, Editor, McGraw-Hill, New York, 2001 [Covi92] “Boundary-Scan Testing with ATEs”, R. R. Covington, R. C. Goodwin, T. A. Reed, Proceedings, ATE&I Conference , pp 32–37, Anaheim CA. Jan 1992 [Croo79] “Analog In-Circuit Component Measurements: Problems and Solutions”, D. T. Crook, Hewlett-Packard Journal , vol 30, No. 3, March 1979 [Crou94] “Low Power Mode and IEEE 1149.1 Compliance: A Low Power Solution”, A. L. Crouch, R. Ramus, C. Maunder, Proceedings, International Test Conference, pp 660– 669, Washington DC, Oct 1994 [Dahb89] “An Optimal Test Sequence for the JTAG Boundary-Scan Controller”, A. Dahbura, M. U. Uyar and C. W. Yau, Proceedings, International Test Conference , Washington DC, pp 55–62, Aug 1989 [DeJo91] “Testing the Integrity of the Boundary-Scan Test Infrastructure”, F. de Jong and F. van der Heyden, Proceedings, International Test Conference , Nashville TN, pp 106– 112, Oct 1991 [DeJo00] “Power Pin Testing: Making the Test Coverage Complete”, F. de Jong and R. Schuttert, Proceedings, International Test Conference , Atlantic City NJ, pp 575–584, Oct 2000 [DeJo01] “Testing and Programming Flash Memories on Assemblies During High Volume Production”, F. de Jong, A. S. Biewenga, D. van Geest and T. F. Waayers, Proceedings, International Test Conference , Baltimore MD, 470–479, Oct 2001 [Derv88] “Using Scan Technology for Debug and Diagnostics in a Workstation Environment”, B. I. Dervisoglu, Proceedings, International Test Conference, Washington DC, pp 976–986, 1988 [Dubb08] “Solving In-Circuit Defect Coverage Holes with a Novel Boundary-Scan Application”, D. Dubberke, J. J. Grealish, B. van Dick, Proceedings, International Test Conference , paper 11.2, Santa Clara, CA, Oct 2008 [EDIF91] “EDIF Test Technical Subcommittee Test Extension”, Version 2 0 32, EDIF Test Technical Subcommittee , Oct 1991 [Eklo01] “Unsafe Board States During PC-Based Boundary-Scan Testing”, B. Eklow, R. Sedmak and D. Singletary, Proceedings, International Test Conference , Baltimore MD, pp 615–623, Oct 2001 [Eklo02] “IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks”, B. Eklow, C. F. Barhart, K. P. Parker, Proceedings, International Test Conference , pp 1056–1065, Baltimore MD, Oct 2002 [Eklo05] "An update on IEEE 1149.6 - successes and issues", B. Eklow, Proceedings, International Test Conference, Austin TX, Nov 2005 [Fasa89] “ASIC Testing in a Board/System Environment”, F. P. Fasang, IEEE Custom Integrated Circuits Conference , New York NY, pp 22.4.1–22.4.4, 1989 [Fout06] “Automation of IEEE 1149.6 Boundary Scan Synthesis in an ASIC Methodology”, B. Foutz, V. Chickermane, B. Li, H. Linzer, G. Kunzelman, 15 th Asian Test Symposium , Fukuoka Japan, Nov 2006 [Gall90] “The Testability Features of the 68040”, M. Gallup et al, Proceedings, International Test Conference , pp 749–757, Washington DC, Sept 1990 [Gree93] “Beneﬁ ts of Boundary-Scan to In-Circuit Test”, D. A. Greene, Proceedings, International Test Conference , p 263, Baltimore MD, Oct 1993 [Gols00] “Test and On-Line Debug Capabilities of IEEE Std 1149.1 in UltraSparc(TM)-III Microprocessor”, F. Golshan, Proceedings, International Test Conference , Atlantic City NJ, pp 141–150, Oct 2000 References 535

[Hall89] “Prototype Testing Simpliﬁ ed by Scannable Buffers and Latches”, A. Halliday, G. Young and A. Crouch, Proceedings, International Test Conference, pp 174–181, Washington DC, Aug 1989 [Hans89a] “The Impact of Boundary-Scan on Board Test Strategies”, P. Hansen, Proceedings, ATE&I Conference , Boston MA. pp 35–40, June 1989 [Hans89b] “Testing Conventional Logic and Memory Clusters Using Boundary-Scan Devices as Virtual ATE Channels”, P. Hansen, Proceedings, International Test Conference , Washington DC, pp 166–173, Aug 1989 [Harr01] “Hierarchical Boundary-Scan: A Scan Chip-Set Solution”, S. Harrison, G. Noeninckx, P. Horwood and P. Collins, Proceedings, International Test Conference , Baltimore MD, pp 480–486, Oct 2001 [Hawk85] “Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs”, C. F. Hawkins and J. M. Soden, Proceedings, International Test Conference , pp 544–555, Philadelphia, Nov 1985 [Hill92] “Boundary-Scan Testing for Multichip Modules”, S. C. Hilla, Proceedings, International Test Conference , pp 224–231, Baltimore MD, Sept 1992 [Hird02] “Test Coverage: What Does It Mean When a Board Test Passes?”, K. Hird, K. P. Parker and B. Follis, Proceedings, International Test Conference, Baltimore MD, 1066–1074, Oct 2002 [Hewl85] “SAFEGUARD In-Circuit, a Description of HP's Safe Implementation of Digital In-Circuit Test”, Product Note 3065-2, Hewlett-Packard Manufacturing Test Division, Loveland CO. Sept 1985 [Huan97] “Analog Fault Diagnosis for Unpowered Circuit Boards”, J. L. Huang and K. T. Cheng, Proceedings, International Test Conference, pp 640–648, Washington DC, Nov 1997 [IEEE90] “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1–1990, IEEE Standards Board , 345 East 47th St. New York NY 10017, May 1990 [IEEE92] “Extended Digital Serial Subset”, Proposed IEEE Standard P1149.2/D0.2, IEEE Standards Board , 345 East 47th St. New York NY 10017, Feb 1992 [IEEE93a] “IEEE Standard 1149.1 Draft Supplement”, IEEE Standard 1149.1a-1993, IEEE Standards Board , 345 East 47thSt. New York NY 10017, 1993 (Now included in [IEEE01]) [IEEE93b] “IEEE Standard VHDL Language Reference”, IEEE Standard 1076-1987, IEEE Standards Board , 345 East 47th St. New York NY 10017, 1993 [IEEE94] “IEEE Standard 1149.1 Draft Supplement”, IEEE Standard 1149.1b-1994, IEEE Standards Board , 345 East 47thSt. New York NY 10017, 1994 (Now included in [IEEE01]) [IEEE95] “IEEE Standard Module Test and Maintenance (MTM) Bus Protocol”, IEEE Standard 1149.5-1995, IEEE Standards Board, 345 East 47th St. New York NY 10017, 1995 [IEEE99] “IEEE Standard for a Mixed Signal Test Bus”, IEEE Standard 1149.4-1999, IEEE Standards Board , 345 East 47th St. New York NY 10017, 1999 [IEEE01] “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1-2001, IEEE Standards Board , 345 East 47th St. New York NY 10017, 2001 [IEEE02] “IEEE Standard for In-System Conﬁ guration of Programmable Devices”, IEEE Standard 1532-2002, IEEE Standards Board , 345 East 47th St. New York NY 10017, 2003 [IEEE03] “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks”, IEEE Standard 1149.6-2003, IEEE Standards Board, 345 East 47th St. New York NY 10017, 2003 [IEEE07] “IEEE Standard for a Smart Transducer Interface for Sensors and Actuators— Common Functions, Communication Protocols, and Transducer Electronic Data Sheet (TEDS) Formats”, IEEE Standard 1451.0-2007, IEEE-SA Standards Board, 3 Park Avenue, New York, NY 10016-5997, 2007 536 References

[IEEE12] “IEEE Standard for Boundary-Scan-Based Stimulus of Interconnections to Passive and/or Active Components”, IEEE Standard 1149.8.1-2012, IEEE-SA Standards Board , 3 Park Avenue, New York, NY 10016-5997, 2012 [IEEE12a] “IEEE Standard for SystemVerilog--Unifi ed Hardware Design, Specifi cation, and Verifi cation Language”, IEEE Standard 1800-2012 , IEEE-SA Standards Board, 3 Park Avenue, New York, NY 10016-5997, 2012 [IEEE13] “IEEE Standard Test Access Port and Boundary-Scan Architecture”, IEEE Standard 1149.1–2013, IEEE Standards Board, 3 Park Avenue, New York NY 10016-5997, 2013 [IEEE15] “IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks”, IEEE Standard 1149.6-2015, IEEE Standards Board, 345 East 47th St. New York NY 10017, 2015 [Inte91] “Intel486 DX Microprocessor Data Book”, Intel Corporation, June 1991 [Jaco03] “The In-System Confi guration Handbook: A Designer’s Guide to ISC”, N. Jacobson, Kluwer Academic Publishers, Norwell MA, (to appear 2003) [Jarw89] “A Unifi ed Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects”, N. Jarwala and C. W. Yau, Proceedings, International Test Conference , pp 71–77, Washington DC, Aug 1989 [Jarw94] “Designing ‘Dual Personality’ IEEE 1149.1 Compliant Multi-Chip Modules”, N. Jarwala, Proceedings, International Test Conference , pp 446–455, Washington DC, Oct 1994 [JEDE86] “Standard Manufacturer's Identifi cation Code”, Joint Electron Device Engineering Council , JEDEC Publication 106-A, Washington DC, 1986 [Jose93] “Test Features of the HP PA7100LC Processor”, D. D. Josephson, D. J. Dixon and B. J. Arnold, Proceedings, International Test Conference , pp 764–772, Baltimore MD, Oct 1993 [Kaji92] “Practical Test Generation with IEEE 1149.1 Boundary-Scan”, H. Kajitani, H. Sato, H. Saito and S. Oresjo, Proceedings, ATE&I Conference, pp 10–17, Anaheim CA. Jan 1992 [Kaut74] “Testing of Faults in Wiring Interconnects”, W. K. Kautz, IEEE Transactions on Computers , vol C-23, No. 4, pp 358–363, April 1974 [Ke96] “Backplane Interconnect Test in a Boundary-Scan Environment”, W. Ke, Proceedings, International Test Conference , Washington DC, pp 717–724, Oct 1996 [Kim01] “Frequency Detection-Based Boundary-Scan Testing of AC Coupled Nets”, Y. Kim, B. Lai, K. P. Parker, J. Rearick, Proceedings, International Test Conference, pp 46–53, Baltimore MD, Oct 2001 [Kris02] “Improved Digital I/O Ports Enhance Testability of Interconnections”, A. Kristof, Proceedings, International Test Conference , Baltimore MD, 763–772, Oct 2002 [Lage89] “Testing Multiple Power Connections with Boundary-Scan”, D. van de Lagemaat, Proceedings, European Test Conference , pp 127–130, Paris Fr., April 1989 [Lang93] “Utilizing Boundary-Scan to Implement BIST”, T. Langford, Proceedings, International Test Conference , pp 167–173, Baltimore MD, Oct 1993 [Lavo00] “A Good Excuse for Reuse: 'Open' TAP Controller Design”, D. Lavo, Proceedings, International Test Conference , Atlantic City NJ, pp 1090–1099, Oct 2000 [Lefe90] “Functional Test and Diagnosis: A Proposed JTAG Sample Mode Scan Tester”, M. F. Lefebvre, Proceedings, International Test Conference, pp 294–303, Washington DC, Sept 1990 [Lofs96a] “A Demonstration IC for the P1149.4 Mixed-Signal Test Standard”, K. Lofstrom, Proceedings, International Test Conference , pp 92–98, Washington DC, Oct 1996 [Lofs96b] “Early Capture for Boundary-Scan Timing Measurements”, K. Lofstrom, Proceedings, International Test Conference , pp 417–422, Washington DC, Oct 1996 [Liu91] “Testing and Diagnosis of Analog Circuits and Systems”, R. Liu, Van Nostrand Reinhold, New York, 1991 References 537

[Maun87] “Boundary-Scan — A Framework for Structured Design for Test”, C. M. Maunder and F. P. M. Beenker, Proceedings, International Test Conference , pp 714–723, Washington DC, Sept 1987 [Maun90] “The Test Access Port and Boundary-Scan Architecture”, C. M. Maunder and R. E. Tulloss, IEEE Computer Society Press , Los Alamitos CA, Sept 1990 [McDe98a] “Limited Access Testing: Ability and Requirements”, J. McDermid, Proceedings, NEPCON 1998 , Anaheim CA, Feb 1998 [McDe98b] “Solving Limited Access Constraints in ICT”, J. McDermid, Electronics Engineer , July 1998 [McDe98c] “Limited Access Testing: 1149.4 Instrumentation and Methods”, J. McDermid, Proceedings, International Test Conference , Washington DC, Oct 1998 [Milo95] “Success with Boundary-Scan, A Case Study”, P. Milo, Evaluation Engineering , pp 72–74, Feb 1995 [Muri90] “Integrating Boundary-Scan Test into an ASIC Design Flow”, M. Muris, Proceedings, International Test Conference , pp 472–477, Washington DC, Sept 1990 [Muri93] “Using Boundary-Scan to Test Random Access Memory Clusters”, M. Muris and A. Biewenga, Proceedings, International Test Conference , pp 174–179, Baltimore MD, Oct 1993 [Nade95] “A New Hardware Fault Insertion Scheme for System Diagnostics Veriﬁ cation”, B. Nadeau-Dostie, H. Hulvershorn and S. M. I. Adham, Proceedings, International Test Conference , pp 994–1002, Washington DC, Oct 1995 [Nadi77] “Signature Analysis - Concepts, Examples and Guidelines”, H. J. Nadig, Hewlett- Packard Journal, pp 15–21, May 1977 [Norr08] “Augmenting Boundary-Scan Tests for Enhanced Defect Coverage”, D. Norrgard and K.P. Parker, Proceedings International Test Conference , paper 11.3, Oct 2008 [Nuri97a] “The Trend of Technology and Standardization in Boundary-Scan Test Technology”, K. Nuriya, K. Hirayama, K. P. Parker, and M. Kawai, Journal of Japan Institute for Interconnecting and Packaging Electronic Circuits, Vol. 12, No. 1, pp 4–5, Jan 1997 (In Japanese) [Nuri97b] “Moving Towards 100% Manufacturing Defect Coverage for Mixed-Signal Boards”, K. Nuriya, A. Kukutsu, A. Matsuzawa, K. Hirayama, and K. P. Parker, Nikkei Electronics No. 685, pp 183–198, March 1997 [In Japanese] [Oakl00] “Considerations for Implementing IEEE 1149.1 on System-on-a-Chip Integrated Circuits”, S. Oakland, Proceedings, International Test Conference, Atlantic City NJ, pp 628–637, Oct 2000 [Ores92] “Board Test Issues when Implementing Boundary-Scan IEEE 1149.1”, S. Oresjo and J. Stoltman, Proceedings, ATE&I Conference , pp 207–213, Anaheim CA. Jan 1992 [Osse99] “The 1149.4 Mixed-Signal Test Bus”, A. Osseiran Ed., Kluwer Academic Publishers, Norwell MA, 1999 [Park87] “Integrating Design and Test: Using CAE Tools for ATE Programming”, K. P. Parker, IEEE Computer Society Press , Los Alamitos CA, 1987 [Park89] “The Impact of Boundary-Scan on Board Test”, K. P. Parker, IEEE Design and Test of Computers , vol 6, pp 18–30, August 1989 [Park90a] “Production Board Testing in a Boundary-Scan Environment”, K. P. Parker, Proceedings, ATE&I Conference , Anaheim CA. pp 11–18, Jan 1990 [Park90b] “A Language for Describing Boundary-Scan Devices”, K. P. Parker and S. Oresjo, Proceedings, International Test Conference, pp 222–234, Washington DC, Sept 1990 [Park91] “A Language for Describing Boundary-Scan Devices”, K. P. Parker and S. Oresjo, Journal of Electronic Testing; Theory and Applications, vol 2, no. 1, pp 43–75, March 1991 [Park93] “Structure and Metrology for an Analog Testability Bus”, K. P. Parker, J. E. McDermid, S. Oresjo, Proceedings, International Test Conference , pp 309–322, Baltimore MD, Oct 1993 538 References

[Park97] “Design, Fabrication and Use of Mixed-Signal IC Testability Structures”, K. P. Parker, J. E. McDermid, R. A. Browen, K. Nuria, K. Hirayama, A. Matsuzawa, Proceedings, International Test Conference , pp 489–498, Washington DC, Nov 1997 [Park00] “System Issues with Boundary-Scan Board Test”, K. P. Parker, Proceedings, International Test Conference , pp 724–728, Atlantic City NJ, Oct 2000 [Park03] "Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary- Scan Test Passes?", Parker, K. P., Proceedings, International Test Conference , Charlotte NC, Sep 2003 [Park04] “A New Probing Technique for High-Speed/High-Density Printed Circuit Boards”, Parker, K. P., Proceedings, International Test Conference, paper 13.1, Charlotte NC, Oct 2004 [Park05] "The Effects of Defects on High-Speed Boards", Parker, K. P., Proceedings, International Test Conference , Austin TX, Nov 2005 [Park05a] “Bead Probes in Practice”, Parker, K. P., Proceedings, International Test Conference, Austin TX, Nov 2005 [Park08] "Boundary-Scan Testing of Power/Ground Pins", Parker, K. P. and Jacobson, N. G., Proceedings, International Test Conference , Santa Clara CA, Oct 2008 [Park10] “Surviving State Disruptions Caused by Test: the “Lobotomy Problem”, Parker, K. P., Proceedings, International Test Conference , paper 19.2, Austin TX, Oct 2010 [Park11] “Surviving State Disruptions Caused by Test: A Case Study”, Parker, K. P., Kameyama, S., Dubberke, D., Proceedings, International Test Conference , Paper 5.2, Anaheim CA, Sept 2011 [Park12] “Capacitive Sensing Testability in Complex Memory Devices”, Parker, K. P., Proceedings, International Test Conference , Paper 13.1, Anaheim CA, Nov 2012 [Poss91] “A Design-For-Testability Architecture for Multichip Modules”, K. E. Posse, Proceedings, International Test Conference , pp 113–121, Nashville TN, Oct 1991 [Pyro95] “Implementing 1149.1 in the PowerPCTM RISC Microprocessor Family”, C. Pyron and W. C. Bruce, Proceedings, International Test Conference, pp 844–850, Washington DC, Oct 1995 [Raym95] “Algorithmic Extraction of BSDL from 1149.1-Compliant Sample ICs”, D. W. Raymond, D. E. Wedge, P. J. Stringer, H. W. Ng, S. T. Jennings, C. T. Pynn, W. Soule, Proceedings, International Test Conference , pp 561–568, Washington DC, Oct 1995 [Reed95] “Improving Board and System Test: A Proposal to Integrate Boundary-Scan and

IDDQ ”, D. Reed, J. Doege and A. Rubio, Proceedings, International Test Conference , pp 577–585, Washington DC, Oct 1995 [Robi83] “Investigation of Potential Damage Resulting from Digital In-Circuit Testing”, R. Robinson, Proceedings, ATE East Conference , Boston MA. Jan 1983 [Robi90] “Interconnect Testing of Boards with Partial Boundary-Scan”, G. D Robinson, J. G. Deshayes, Proceedings, International Test Conference, pp 572–581, Washington DC, Sept 1990 [Robi93a] “Technology-Independent Boundary-Scan Synthesis (Design Flow Issues)”, M. F. Robinson, Proceedings, European Design Automation Conference , Hamburg Germany, Sept 1993 [Robi93b] “Technology-Independent Boundary-Scan Synthesis (Technology and Physical Issues)”, M. F. Robinson, F. Mailhot and J. Konsevich, Proceedings, International Test Conference , pp 157–166, Baltimore MD, Oct 1993 [Shar92] “Test Generation for Structural Testing with Boundary-Scan”, R. Sharma, Proceedings, ATE&I Conference , pp 194–205, Anaheim CA. Jan 1992 [Sing97] “A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator”, H. Singh, G. Patankar, J. Beausang, Proceedings, International Test Conference , pp 256–264, Washington DC, Nov 1997 [Sobo82] “The Effects of Backdriving Digital Integrated Circuits During In-Circuit Testing”, L. J. Sobotka, Proceedings, International Test Conference , pp 269–286, Philadelphia PA. Oct 1982 References 539

[Stan02] “An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-compliance Improvements”, D. Stang and R. Dandapani, Proceedings, International Test Conference , Baltimore MD, 746–753, Oct 2002 [Sunt95] “The P1149.4 Mixed-Signal Test Bus: Costs and Benefi ts”, Proceedings, International Test Conference , pp 444–450, Washington DC, Oct 1995 [Sunt96] “Cost/benefi t Analysis of the P1149.4 Mixed-Signal Test Bus”, S. Sunter, IEEE Proceedings, Circuits, Devices, and Systems , December 1996, pp 393–398. [Sunt01] “A General Purpose 1149.4 IC with HF Analog Test Capabilities”, S. Sunter, K. Filliter, J. Woo, P. McHugh, Proceedings, International Test Conference , Baltimore MD, Oct. 2001, pp 38–45 [Sunt02] “Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost”, S. Sunter, B. Nadeau-Dostie, Proceedings, International Test Conference , Baltimore MD, Oct 2002 [Sunt09] "Testing Bridges to Nowhere - Combining Boundary-Scan and Capacitive Sensing", Sunter, S. and Parker, K. P., Proceedings, International Test Conference, Austin TX, Nov 2009 [Swee88] “JTAG Boundary-Scan: Diagnosing Module Level Functional Failures”, J. Sweeney, National Communications Conference , 1988, pp 1801–1804 [Swen86] “Thermal Analysis of Backdriven Output Transistors”, R. L. Swent and M. J. Ward, Proceedings , International Test Conference, pp 295–303, Washington DC, Sept 1986 [Tege96] “Opens Board Test Coverage: When is 99% Really 40%?”, M. V. Tegethoff, K. P. Parker and K. Lee, Proceedings, International Test Conference , pp 333–339, Washington DC, Oct 1996 [Tell52] “A General Network Theorem with Applications”, B. D. H. Tellegen, Phillips Research Report No. 7, pp 259–269, 1952 [Texa90] “ASSET Diagnostic System Overview”, (Literature SATT113), Texas Instruments, Inc., 1990 [Texa91a] “54BCT8244/74BCT8244 Octal Buffer with Boundary-Scan”, Texas Instruments, Inc., 1991 [Texa91b] “54BCT8374/74BCT8374 Octal D Flip-Flop with Boundary-Scan”, Texas Instruments, Inc., 1991 [That93] “Towards a Test Standard for Board and System Level Mixed-Signal Interconnects”, C. W. Thatcher and R. E. Tulloss, Proceedings, International Test Conference , pp 300–308, Baltimore MD, Oct 1993 [USP93] “Powered Testing of Mixed Conventional/Boundary-Scan Logic”, United States Patent 5,260,649, Nov 1993 [Verm02] “IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips”, B. Vermeulen, T. Waayers, S. Bakker, Proceedings, International Test Conference , pp 55–63, Baltimore MD, Oct 2002 [Vinn98] “Analog and Mixed-Signal Test”, B. Vinnakota, Editor, Prentice Hall, Upper Saddle River, NJ, 1998 [Wagn87] “Interconnect Testing with Boundary-Scan”, P. T. Wagner, Proceedings, International Test Conference , pp 52–57, Washington DC, Sept 1987 [Wagn88] “Design for Testability of Mixed-Signal Integrated Circuits”, K. D. Wagner and T. W. Williams, Proceedings, International Test Conference , pp 823–828, Washington DC, Oct 1988 [Wagn91] “Enhancing Board Functional Self-Test by Concurrent Sampling”, K. D. Wagner and T. W. Williams, Proceedings, International Test Conference , pp 633–640, Nashville TN, Oct 1991 [Whet90] “Event Qualifi cation: a Gateway to At-Speed System Testing”, L. Whetsel, Proceedings, International Test Conference, pp 135–141, Washington DC, Sept 1990 [Whet92] “A Proposed Method of Accessing 1149.1 in a Backplane Environment”, L. Whetsel, Proceedings, International Test Conference , pp 206–216, Baltimore MD, Sept 1992 540 References

[Whet95] “Improved Boundary Scan Design”, L. Whetsel, Proceedings, International Test Conference , pp 851–860, Washington DC, Oct 1995 [Whet97] “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores”, L. Whetsel, Proceedings, International Test Conference, pp 69–78, Washington DC, Nov 1997 [Wibl99] “Design a Production and Test Strategy for PLD-based PCBs”, K. Wible, Test and Measurement World , pp 37–44, March 1999 [Will83] “Design for Testability — A Survey”, T. W. Williams and K. P. Parker, Proceedings of the IEEE , vol. 71, No. 1, Jan 1983 [Xili90] “XC 4000 Logic Cell Array Family”, Xilinx Inc. 1990 [Xili92] “Boundary-Scan Emulator for XC 3000”, Application Note XAPP-007.0, Xilinx Inc. 1992 [Xili98] “The Programmable Logic Data Book”, Xilinx Inc, 1998 [Yau89] “A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects”, C. W. Yau and N. Jarwala, Proceedings, International Test Conference , pp 63–70, Washington DC, Aug 1989 Index

A AT2 , 233, 235–237 ABM. See Analog boundary module (ABM) AT1N , 233, 256 AC/DC selection cells , 286–287, 305, 312, AT2N , 233, 256 316, 317 Analog test bus AC EXTEST , 269, 283, 284, 287, 290, 298, AB1 , 234 301, 303, 306, 459 AB2 , 234 AC EXTEST instruction AB1N , 234 EXTEST_PULSE , 283, 284 AB2N , 234 EXTEST_TRAIN , 283, 284 Anti-aliasing PTV , 134 AC EXTEST working group , 269 Application specifi c integrated circuit (ASIC) , AC parameter description , 461–462, 465 46, 118–120, 151 AC pins ATAP. See Analog test access port (ATAP) defi ned , 281 ATE. See Automatic test equipment (ATE) drivers , 283–287 ATPG. See Automatic test program generation test facilities , 282–288 (ATPG) AC test mode , 282, 298, 303 AT&T 479AA , 195 Addressable shadow port , 200 Automatic test equipment (ATE) , 4, 5, 8, 15, 17, Advanced I/O 32, 40, 45, 49, 52, 53, 99, 117–120, AC pins , 282–289, 315–318 122, 125, 130, 131, 141–143, 147, BSDL example , 423 148, 156, 164, 167, 172, 178, 179, DC pins , 281–283, 287, 312 196, 208–212, 215, 218, 226–228, defects , 288–292, 300, 318–320 250, 251, 256, 265, 335, 340, 341, 436 defi nition , 280 Automatic test program generation (ATPG) , example , 270, 273, 274, 277, 279, 280 93, 97, 119, 146 inter-IC communication , 270–275 problem , 270–280 testing , 269–320 B Agilent HDMP-2689 , 45, 377 Ball-grid array (BGA) , 65, 133, 163, 169, 171, Aliasing , 131–134, 176 224, 225 Ambiguity Class , 221, 223 Basic test algorithm , 115–116, 120, 122, 129, Am29035 , 163 130, 353 Analog boundary module (ABM) , 231, 232, 234, BILBO. See Built-in logic block 242–250, 253, 254, 257, 262, 376 obser(BILBO) Analog boundary-scan , 203, 227–267 Blind interrogation , 35, 199 Analog test access port (ATAP) Boundary register , 4, 50, 112, 151, 173, 231, AT1 , 233, 236, 237 282, 330, 347, 382, 456

Boundary register cell self-monitoring output , 89, 101, 182, 239, ABM , 231, 234, 242–247 310, 311, 357 abstraction of , 90, 91 shift in , 23, 168, 305 AC_1 , 306, 309, 310, 315, 466 shift out , 23, 338 AC_2 , 306, 309, 310, 466 signal inversion , 25 AC_7 , 306, 307, 309, 310 single-cell bidirectional , 182, 331 AC_8 , 306, 308–310 ST_10 , 357 AC_9 , 308–310 test receiver , 304 AC_10 , 309, 311, 466, 467 three-cell bidirectional , 359 AC_40 , 460, 466, 467 two-cell bidirectional , 182, 245 AC_41 , 460, 466, 467 Boundary-scan description language (BSDL) AC_SelU , 305, 309, 310, 315, 466 attribute (see Boundary-scan description AC_SelX , 305, 309, 310, 466 language (BSDL) attribute) BC_0 , 86, 87 automated creation , 201 BC_1 , 73, 80, 81, 84, 86, 87, 90, 92–93, boundary-scan register descriptions 101, 106, 168 boundary register assembly , 412–486 BC_2 , 81, 86, 309, 310 fi xed boundary register description , BC_3 , 86, 88 409–410 BC_4 , 86, 88, 460, 466 segmented boundary register BC_5 , 86, 88, 96, 97, 184 description, 410–412 BC_6 , 86, 88, 106 cell description constants , 89–92 BC_7 , 86, 89, 309, 310, 331, 409 certifying , 187 BC_8 , 86, 89, 92, 99–102, 306, 309, 310, 351 comment , 49, 58–60, 89, 105, 315, 404 BC_9 , 86, 89, 92, 101, 181, 308–310 component conformance, 64–65, 83, 85, 105 BC_10 , 86, 89, 92, 99–101, 106, 308, 309, damaged by electronic mail , 60 311, 356–358 design warnings , 61, 78, 84, 87, 106 BC_99 , 92 device package pin mapping , 61, 65–66, 313 bidir , 80 entity , 59, 480–486 bidir_in , 91, 92 extensions , 61, 64, 77, 84, 87, 104, 106, bidir_out , 91, 92 304–318, 459, 460, 466 capture data , 90, 91, 102, 114, 124, 180, extensions for 1149. , 304–318 437, 438, 450 generic parameter , 58, 61–62, 65, 66, 105, 312 cell count , 23, 79, 99, 182 grouped port identifi cation , 61, 66–67, 83, clock , 41–42 314 constant “0/1” capture , 70, 102, 287 identifi er , 58, 61, 62, 65, 105, 403, 415–417 control , 30, 39, 42 IEEE version , 50, 51, 64, 107 controlr , 74, 411–413 information tag , 404, 415, 416, 418, 432, 433 DBM , 31, 231, 247–248 initial (1990) version , 50 fl awed design , 25 instruction register description , 61, 69–70, 314 general design , 53 INTEST execution description , 76–77 hardware fault insertion , 167–168 ISC algorithms , 322 input , 25, 27, 93 linkage , 62, 63, 66, 75, 83, 312 internal , 26, 29, 32 logical port , 61–63, 66, 312, 405 internal cell , 26, 32, 90, 92, 94, 102, 286, mnemonic identifi ers , 403, 415–417 305, 316 numeric literals , 403 logical symbol , 27, 28, 41 pad-to-pin mapping , 57 merged cells , 78–81 PHYSICAL_PIN_MAP , 61, 62, 65, 83, observe_only , 74, 86, 88, 460 312, 313, 407, 481, 485 optimizing , 28–29 pin description , 62–63 output2 , 80, 88 PIN_MAP , 61, 62, 65, 83, 85, 312, 313, output3 , 81 407, 481, 485 parallel in , 20, 23, 91, 120 port types , 66, 404–407 parallel out , 23, 37, 91, 92, 94, 182, 334, 420 power port association description , reversible cell , 88, 92 433–434 Index 543

pre-defi ned constants , 85 INSTRUCTION_OPCODE , 69–71, 83, 86, prefi x identifi ers , 403 105, 314 register assembly description , 407, 410, INSTRUCTION_PRIVATE , 69, 70, 72, 86, 412, 421, 424–431 106 register association description , 433–434 INTEST_EXECUTION , 77, 87 register constraint description , 431–433 PIN_MAP , 65, 83, 85, 313, 407, 481, 485 register fi elds description , 416–425, 489 PORT_GROUPING , 66, 87, 160, 314, 481 register mnemonics description , 415–417 REGISTER_ACCESS , 71, 72, 76, 84, 86, 2013 revisions , 57, 377 106, 314, 421 RUNBIST execution description , 76 RUNBIST_EXECUTION , 76, 87 safe bit , 81 TAP_SCAN_CLOCK , 67, 83, 86, 314 scope , 51–57 TAP_SCAN_IN , 67, 83, 86, 314 standard use statement , 61, 63–64, 105, TAP_SCAN_MODE , 67, 83, 86, 314 309, 405, 406 TAP_SCAN_OUT , 67, 68, 83, 86, 314 STD_1149_1_2013 standard package , 405 TAP_SCAN_RESET , 67, 86 string , 58, 59 USERCODE_REGISTER , 71, 84, 86 structure , 57–60 Boundary-Scan master , 15, 16, 190, 195–197 subset and standard practice of VHDL , 50, 57 Buffer. See Boundary-scan description system clock requirements attribute , 414 language (BSDL), logical port syntax , 505–532 Built-in logic block observer (BILBO) , 172 TAP port identifi cation , 67–68, 315 Bus , 9, 10, 39, 42, 48, 62, 63, 135, 136, 138, to/from synthesis systems , 57 139, 151, 162, 188, 189, 196, 200, type CELL_INFO , 86, 89 208, 227, 234, 237–242, 246, 250, use as test driver , 52 251, 256, 258, 261, 263, 266, user defi ned boundary cells , 101–104 270–272, 274–276, 351, 383, user defi ned package , 64, 85, 102, 104, 105 461–463, 465, 468, 489 user extensions , 77 single-ended , 271, 276 user package syntax (2013) , 461 Bypass register , 12, 22, 31, 34, 40–42, 52, use statements , 58, 63–64, 73, 85, 104–106, 112, 125, 162, 186, 199, 234, 252, 181, 309, 312, 315, 402, 405, 406, 336, 407 456, 464, 481 capture bit , 125 verifi cation , 186, 187 verifi cation test , 186, 187 version control , 107 C Version 0.0 parser , 107 Capture fl ip-fl op (CAP) , 23, 27, 28, 36, 37, 78, VHDL package , 58, 63, 85, 181, 304 86, 90, 91, 93, 94, 102, 112, 152, 153, VHDL package body , 58 167, 184, 186, 303, 353, 358, 419 writing , 53, 105–107 Chains Boundary-scan description language (BSDL) analog busing , 234 attribute broken , 124, 290, 397 BOUNDARY_LENGTH , 72, 73, 80, 84, chain ordering , 190 86, 314, 409 confi gurations , 33, 187–190 BOUNDARY_REGISTER , 73, 79, 80, 84, conjoined , 33, 123, 188, 189 86, 91, 116, 120, 181, 186, 314, 409 dynamically reconfi gurable , 188 BSDL_EXTENSION , 77, 87, 104, 310, 466 extra shift stages (pad bits) , 197 COMPLIANCE_PATTERNS , 68, 87 integrity , 22, 124–126, 143, 173, 201 COMPONENT_CONFORMANCE , 64, linked , 123, 188, 197 83, 85, 310, 313, 315, 481, 485 multidrop system , 198–200 DESIGN_WARNING , 78, 87, 106 multiple simple , 33, 123 IDCODE_REGISTER , 71, 86, 184, 314 simple , 32, 33, 123, 124, 187, 188, INSTRUCTION_CAPTURE , 69, 70, 84, 190–192, 196–198, 236 86, 106, 112, 124, 179, 314 testing , 123–145 INSTRUCTION_LENGTH , 69, 70, 83, 86, Chip-on-board (COB) , 171, 225 105, 314 Chip-scale packaging , 225 544 Index

Common mode noise , 66, 257, 273 missing capacitor , 290, 291 Comparator , 292, 293, 295, 296, 298–300 model , 110, 148, 288–291 Complex programmable logic device (CPLD) , open circuit , 292 118, 164, 201, 334 open solder joint , 291 Compliance enable pins , 43, 51, 56, 68, 69, shorted capacitor , 319, 458–459 75, 105, 117, 194, 195 shorted driver , 132, 133, 291 Compliance limit shorted receiver , 459 current , 206, 207 Designated driver , 130–132, 134–136, 139 voltage , 206, 207 Design for testability (DFT) Concurrent programming , 322, 338–340 board level , 187–198, 263, 319, 375 Confounding , 131–134 built-in logic block observer , 172 Counting sequence , 127, 131, 133, 134, 142 device programming , 14, 31, 335, 341 CPLD. See Complex programmable logic integrated circuit level , 173–187, 263, 318, device (CPLD) 374 Crosstalk , 263, 295 LSSD , 172 system level , 173, 186, 189, 198–200 Device identifi cation register , 12, 13, 20, 22, D 34–36, 52, 70 Data register capture pattern , 106, 178, 179, 184, 186 boundary register , 22 Device under test (DUT) , 5, 7, 144, 207, bypass , 22, 34 343–345, 348, 366 capture data , 20, 90, 91, 437, 450 DFT. See Design for testability (DFT) device identifi cation , 22 Differential dynamic data register , 385, 397–401 AC coupled , 269, 277 ECID , 23 current balancing , 273 halt shifting , 15 driver , 66, 159, 161, 178, 257, 258, 273, Init_data , 384, 392, 394–395, 397, 400, 274, 282, 291, 316, 354–356, 360, 415, 416, 424–427, 432, 433, 441, 361, 363, 364, 408, 435, 469–471 452, 453, 456–458, 469, 471, 473, receiver , 161, 257, 258, 273, 282, 288, 292, 478, 481, 486, 488, 489 295, 296, 312, 408, 435, 460, 472 init_status signals , 66, 105, 159–161, 256–258, 266, busy/done bit , 395 273, 277, 278, 281, 282, 287, 288, pass/fail bit , 123 297, 318, 319, 348, 353–356, 375, mode of operation , 12 383, 384 parallel hold latches , 20 testing , 256, 367 reset selection transmission , 269, 271 reset-control bit , 396 unbalancing , 354–356 reset-enable bit , 396 Differential signaling reset-hold bit , 396, 397 EXTEST paradox , 258 segmented data register , 400 noise rejection , 257, 258 shift portion , 17, 112 Digital boundary module (DBM) , 31, 231, shift ripple , 18 233, 247–248 target register , 112, 113 DRAM. See Dynamic random access memory TMP_status (DRAM) bypass-escape bit , 386, 392, 395, 396 Drive confl icts TMP-status bit , 392, 395, 396, 417 board level , 136 toggle_control , 354, 358, 366 duration , 129 user-defi ned , 22, 42, 72, 106, 429 Driver DBM. See Digital boundary module (DBM) asymmetrical , 40, 75, 78, 81 DC pins , 281–283, 287, 312, 350 clear the throat , 303 DC test mode , 282 damage resistant , 179–180 Defects disabling , 78, 471 detectable with 1149.6 , 290 ECL open emitter , 40, 75 masking , 421 “Keepers” , 75 Index 545

single-ended , 161, 272, 275 analog , 209, 218, 226 TTL open collector , 40, 75 digital , 41 Dual-slope integrator , 213–216 errors , 209–212 DUT. See Device under test (DUT) Dynamic random access memory (DRAM) , 344, 365, 375 H Hardware description language verilog , 56 E VHDL , 50, 401 Electronic design automation , 47, 172 Hardware fault insertion , 167–168 Electrostatic discharge (ESD) , 109, 125, 207, High-pass ﬁ lter , 292–294, 296, 299–301, 463 247, 263 Homing sequence , 157 Emulation , 9, 42, 163, 232, 266 Hyper-text markup language (HTML) , 185 Entity pin behavior description , 463–464 Hysteresis ESD. See Electrostatic discharge (ESD) delay , 299, 301 Extended interconnect , 229–232, 242, 244, voltage , 295, 298 249, 257, 267 Hysteretic comparator , 298 EXTEST paradox , 258 Hysteretic memory , 296, 300, 302–304, 459 initializing and capturing , 302–304

F Fault I detected , 408 ICT. See In-circuit test (ICT) dictionary , 120 IEEE/ANSI standard 1149.1-1990 failure mechanism , 5 supplement A , 4 model , 5 supplement B , 4 Field-programmable gate array (FPGA) , 26, IEEE standard 1076 , 50 118, 164, 189, 201, 334, 390, 391, IEEE standard 1149 , 25, 48, 58, 63, 64, 73, 83, 394, 458 85–89, 103, 104, 106, 305, Field-programmable IC 309–313, 315, 322, 405, 406, 424, blank page , 31 440, 441, 455, 457, 460, 466, 471, in chains , 189 474, 478, 479, 482, 485, 486 cook time , 165 IEEE standard 1149.1 hard-wired , 31, 32 architecture summary , 19 input/output blocks (IOBs) , 31 automation , 46, 49, 382, 388, 389, 422 parallel programming , 32 basic architecture , 10–33 programming , 31, 32, 43, 189 beneﬁ ts , 43–48 Fine-pitch , 7 conformance and documentation Fixed system pins , 323 requirements, 49 FLASH RAM , 165–167, 321 costs , 43–48 programming , 166–167 critical mission , 38 FPGA. See Field-programmable gate array ensuring compliance , 53 (FPGA) extensibility , 85 Framescan , 343 gate overhead , 44 increased design time , 45 inserted delay , 44, 45 G lack of discipline , 45 Gallium arsenide , 180 lack of hierarchy , 162 Garbage In, Garbage Out , 3, 267 non-invasive mode , 9, 151, 183 3GIO , 272 pad overhead , 44 Grandfathering , 64, 65 pin-permission mode , 9, 10, 183 Ground-bounce , 174, 175, 178, 295 private instructions , 69 Guardband , 205 public instructions , 42 Guarding reuse of tests , 46 546 Index

IEEE standard 1149.1 (cont.) Intel 80486DX , 187 standardized access , 39 Intellectual property (IP) , 1, 382, 455, 456, 461 subordination , 43 Interconnect trends , 47–48, 381 adjacent nodes , 143 user-defi ned instructions , 42 counting sequence , 134 yield loss , 44 differential , 229 IEEE standard 1149.4 extended , 229–232, 242, 244, 249, analog boundary modules , 231, 242–247 257, 267 analog test access port , 233, 236–237 interaction test , 140–144 contrasted with 1149.6 , 271 logical , 229 digital boundary modules , 233 opens , 365 general architecture , 233–248 physical , 229 TBIC , 234, 237–242 pin-level diagnostic (shorts) , 144 IEEE standard 1149.5 , 9, 48, 189, 199, 200 shorting radius , 143 IEEE standard 1149.6 shorts , 129–130, 135, 136, 138, 142, 182 AC pins , 281–288, 463, 464, 466 testing , 127, 132, 140, 141, 158, 187, 191, compatibility with 1149.1 , 280 228, 232, 257, 279, 441 DC pins , 281, 282, 287, 312 test length , 129 testing differential I/O , 256 undetected opens , 130, 136 IEEE standard 1149.8.1 , 343, 350–352 walking-bit sequence , 131 IEEE Standard 1532 , 4, 14, 31, 165, 286, I/O Pads , 270, 384 321–342, 376–378 ISC. See In-system confi guration (ISC) IEEE 1149 testability bus standards , 48 ISC instruction in bit. See Boundary-scan description language ISC_DISABLE , 165, 325, 326, 328, (BSDL), logical port 338–340 in bit_vector. See Boundary-scan description ISC_ENABLE , 165, 325–330, 333, 334, language (BSDL), logical port 338, 339, 377 In-circuit test (ICT) ISC_NOOP , 339, 340 analog , 203–217 ISC_PROGRAM , 165, 336–340 bed-of-nails , 203, 217, 344 ISC_PROGRAM_SECURITY , 339 fi xturing , 375 ISC_READ , 336–339 multiplexed resources , 120 ISC signals overdrive damage , 40 ISC_Disable_Completing , 326 Inout. See Boundary-scan description ISC_Done , 326–328, 337 language (BSDL), logical port ISC_Enabled , 165, 325–330, 333, 334, In-situ confi guration. See In-system 338, 339, 377 confi guration (ISC) ISC system pins , 323–324 Institute of Electrical and Electronics Engineers (IEEE) , 3, 49, 117, 161, 172, 203, 227, 269, 321, 343, 381, 455 J Instruction mode , 9, 12, 93–95, 97–98, Joint electron device engineering council 100–102, 240 (JEDEC), 35 Instruction register Joint test action group (JTAG) , 3, 117 capture pattern , 69, 106, 175, 178, 186 halt shifting , 15 length , 315 K opcodes , 69 Kelvin measurement , 211 parallel hold rank , 18–20 sample cell design , 21 shifting , 340 L shift rank , 18 Large scale integration (LSI) , 6 shift ripple , 18, 94 Level-sensitive scan design (LSSD) , 68, 172 In-system confi guration (ISC) , 149, 164–166, LFSR. See Linear feedback shift register 321–342 (LFSR) Intel 8008 , 6 Linear feedback shift register (LFSR) , 42, 144 Index 547

Linkage. See Boundary-scan description O language (BSDL), logical port On-chip coupling and bypassing , 459 Lobotomy problem , 9, 37, 183, 386 Opens express , 343 Logic simulator , 5 Operational ampliﬁ er , 212–214 Low-pass ﬁ lter , 281, 293, 298, 301, 317 Out bit. See Boundary-scan description LSSD. See Level-sensitive scan design language (BSDL), logical port (LSSD)

P M P1149.2 , 48 Manufacturing faults P1149.3 , 48 dead component , 172 Package port link description , 464 missing component , 172 Packaging hierarchy , 162, 200, 422, 423, 436, open solder , 291 442, 445, 488 solder shorts , 143 Parallel test vector (PTV) , 115, 116, 130 wrong component , 172, 229 Parasitic devices , 204, 205, 239, 241, 246, Matsushita electric industries , 47 253, 258, 263, 264 MCM. See Multi-chip module (MCM) PCI express , 272 Measurement errors , 212 PDL commands (Level-0) Measuring impedance iApply , 437–439, 442–451, 473, 488, 489 imaginary waveform , 215–217 iCall , 440, 445, 447, 482 reactive devices , 216 iClock , 442, 445 real waveform , 217 iCLockOverride , 442, 445 6-wire measurement , 212 ifEnd, 446 Measuring operational amplifi er (MOA) , 212 ifFalse , 446 Mixed logic families , 191–193 ifTrue , 446 Mixed-signal , 158, 159, 195, 223–226, iLoop , 446 228–231, 267 iMerge , 446–448 Modes of operation iNote , 448 extensible , 10 iPDLLevel , 441 non-invasive , 9, 10 iPrefi x, 442, 448 pin-permission , 9, 10 iProc , 441, 442, 445–449, 467, 482 Monte carlo simulations , 219 iProcGroup , 442 Moore’s law , 48, 270, 272, 274, 275, 334, 359, iRead , 437, 438, 442, 443, 446, 448, 450, 381–382, 384 468, 469 Motorola 68040 , 44 iRelease , 448 Multi-chip module (MCM) , 47, 161–162, 171, iRunLoop , 445, 448, 449 201 iScan , 442, 443, 446, 448 Multidrop systems , 198–200 iSetFail , 448, 450 Multiple IDCODEs , 71 iSetInstruction , 442 iSource , 441 iTake , 448 N iTMSidle , 446, 449 Node voltage analysis , 218–219, 221, 252 iTMSreset , 446, 449 limited access , 217–223 iTRST , 446, 449 Noise iUntil , 446 common mode , 66, 257 iWrite , 437, 439, 442–444, 448, 450, 468, crosstalk , 295 469, 473 ground-bounce , 295 PDL commands (Level-1) immunity , 66, 266, 277 iGet , 449–452 I/O , 273 iGetStatus , 449–451 radiated interference , 273 PDL_CONTEXT_PATH , 473 rejection , 257, 258, 295 PDL use model small signal , 297, 299 data fl ow (iApply) , 437 Normal system pins , 350 PDL scan frame , 437, 438 548 Index

Performance tests , 204 Selective toggle system pins (“ST” system PLD. See Programmable logic device (PLD) pins ) , 349 Power Self-monitoring output , 38, 101, 181, 182, applying , 9, 127, 133, 139 239, 308, 357 cycling (reset) , 34, 38 Self-referenced comparison , 293, 298 distribution , 169, 174, 178, 193, 195, 271, 273 Sentinel bits , 125, 126 removal (safety) , 130, 180, 438, 471 Sequential response vector (SRV) , 116, 129 separate analog and digital , 195 Sequential test vector (STV) , 116, 129, 130, Powered capacitive opens testing , 343, 344, 132, 296, 303, 319 346–350 SERDES , 45, 275–277, 320, 377, 414 Power/ground distribution , 174–178 SERialize/DESerialize. See SERDES Private instructions , 42, 69, 70, 186, 256, 435 Serial vector format (SVF) , 147 Procedural description language (PDL) Shorted capacitor testing , 290, 291, 319, 458, level-0 PDL , 436, 438–440, 449 459 level-1 PDL , 436, 444, 449 Shorting radius , 143 PDL procedures , 440–442, 448, 449, 467, Silicon switches 482 area , 235 TCL , 436, 440, 468 bipolar , 235, 262 Programmable feature description , 462, 463, 467 conceptual , 242, 244 Programmable logic device (PLD) crummy , 236 complex programmable logic device , 118, leakage , 263, 264 164, 334 off-resistance , 235 FPGA , 26, 118, 164, 189, 201, 390, 391, on-resistance , 235 394, 458 parasitic coupling , 264 non-volatile , 31, 165, 190, 321, 326, 328, switching time , 208, 235, 290 334–336, 340 symbols , 235, 236 volatile , 31, 189, 326, 334, 335 “T” switch , 263, 264 PTV. See Parallel test vector (PTV) Simple interconnect , 129, 228, 229, 257 Single-ended , 161, 271, 272, 274–276, 280, 281, 288, 291, 298, 303, 316, 317, R 356, 358–360, 362, 363, 366, 368 Receiver , 5, 109, 161, 182, 257, 273, 361, Single Stuck-at fault model , 5 390, 458 SMT. See Surface-mount technology (SMT) differential , 66, 161, 257, 258, 273, 282, 288, SOC. See System-on-chip (SOC) 292, 295, 296, 312, 408, 432, 460, 472 Source Reed relay current , 141, 206, 207, 218, 250, 252, 355 area , 29, 44, 99, 129, 151, 221, 224, 226, voltage , 206–208, 210, 216, 217, 243, 299 228, 235, 244, 263, 264, 283, 305, S R V. See Sequential response vector (SRV) 357, 375, 386, 399, 408, 418 1149.6 Standard PDL procedures off-resistance , 235 programmable “GetALL” iProcs , 467 on-resistance , 235 programmable “Get” iProcs , 467 switching time , 235 programmable “Set” iProcs , 467 Reference voltages STD_1149_1_1990 , 58, 64 G , 208, 234 STD_1149_1_1993 , 64

VH , 234, 237, 242–245, 249, 257, 262, 264 STD_1149_1_1994 , 58, 59 V L , 234, 237, 242–245, 249, 252, 257, 262, STD_1149_1_2001 , 63, 64, 73, 85–89, 305 264 STD_1149_6_2003 , 305, 309–311, 466

V TH , 237, 242, 264 deﬁ ned , 466 STV. See Sequential test vector (STV) Surface-mount technology (SMT) , 7, 46, 171 S Synchronizing sequence , 12, 111, 449 Scan-path linker , 196, 197 System logic , 9, 30, 32, 34, 36–39, 41, 43, 48, Segmented data register , 394 50, 53, 56, 78, 79, 81, 82, 91, Index 549

120–122, 151, 178–180, 183, 186, update-DR , 16–18, 28, 37–39, 112, 113, 198, 325, 366, 386, 393, 398, 419 129, 155, 167, 168, 174, 175, 278, System modal state 279, 283, 296, 297, 300, 330, 353, ISC accessed , 325, 328–330, 338 387, 393, 396, 420, 421, 436, 445 ISC complete , 325, 326, 328, 330, 340 update-IR , 15–20, 28, 37, 40, 41, 71, operational , 326, 327, 330, 340 112–114, 116, 120, 122, 174, 179, unprogrammed , 326, 330, 337 186, 303, 324, 328, 352, 386, 394 System-on-chip (SOC) , 45, 161, 171, 377 Tape automated bonding (TAB) , 171 TAP instruction BYPASS , 13, 20, 22, 34, 35, 37, 38, 57, T 70, 72, 90, 93–95, 97, 98, 100–102, T A P . See Test access port (TAP) 107, 110, 112, 125, 144, 155, 162, TAP controller 165, 167, 179, 186, 190, 192, 198, asynchronous reset , 10 199, 240, 241, 246, 249, 252, 261, data column states , 12, 13, 113, 144, 199 282, 326, 328, 340, 386, 387, 392 ﬁ nite state machine , 11, 12 CLAMP , 41, 57, 93–95, 97, 98, 100–102, instruction column states , 12, 13, 175 110, 155, 165, 186, 240, 252–254, power-up reset , 420 282, 306, 329, 330, 342, 387, state diagram , 12, 20, 33, 48, 52, 56, 110, 391–393, 442 111, 113, 123, 167, 174, 179, 186, CLAMP_HOLD , 386, 387, 392, 395, 396 223, 283, 385, 444, 449 CLAMP_RELEASE , 386, 387, 392, 395, state transitions , 12, 13 396 synchronizing sequence , 12, 111, 449 ECID_CODE , 389–390, 394, 421, 441, temporary state , 14–17 452 TAP controller state EXTEST , 28, 38, 39, 41, 57, 70, 72, 90, capture-DR , 14, 16–18, 22, 34–40, 52, 70, 93–95, 97–103, 107, 110, 112–115, 72, 90, 112, 122, 142, 143, 152, 121, 151, 155, 157, 166, 167, 175, 154, 155, 181, 186, 279, 297, 303, 179–181, 183, 184, 186, 190, 191, 305, 354, 394, 419, 420, 436 240, 241, 246, 248–252, 258, 261, capture-IR , 14, 17–20, 53, 70, 106, 112, 283, 284, 286, 287, 290, 291, 124, 175, 178, 179 295–297, 301, 306, 319, 329, 330, Exit1-DR , 16–18, 112, 300 342, 347, 352, 353, 358, 366, 369, Exit2-DR , 16, 17, 300, 444 370, 373, 375–377, 386, 387, 390, Exit1-IR , 14, 15, 17, 18, 20, 112, 179 395, 435, 442, 458, 459, 461, 463, Exit2-IR , 15, 20 487, 490 pause-DR , 16, 17, 188, 444, 445 EXTEST_PULSE (see AC EXTEST pause-IR , 15, 20, 188 Instruction) run-test/idle , 13–14, 16, 17, 40, 76, 113, EXTEST_TRAIN (see AC EXTEST 122, 125, 144, 283–285, 291, 300, Instruction) 303, 317, 318, 325–328, 336–340, HIGHZ , 40, 57, 76, 98, 99, 151, 155, 165, 351–353, 357, 358, 444, 445, 449 186, 240, 241, 245, 246, 249, select-DR-scan , 13, 14, 16, 17, 152, 174, 252–254, 261, 282, 306, 329–334, 175, 283, 351, 445 342 select-IR-scan , 14, 113, 175 IC_RESET , 393, 396, 397 shift-DR , 16, 17, 38, 112, 125, 144, 354, IDCODE , 12, 20, 22, 34–37, 70–72, 90, 391, 420, 444 94, 95, 97, 98, 100–102, 107, 110, shift-IR , 14, 15, 17, 18, 20, 111, 112 112, 125, 184, 186, 199, 240, 249, test-logic-reset , 12–14, 20, 33, 35, 37, 57, 282, 315, 326, 387, 389, 452 74, 90, 111, 116, 122, 123, 125, INIT_CLAMP , 390–392, 394 165, 168, 183, 186, 199, 326, 328, INITIALIZE , 366, 379 338–340, 366, 386, 387, 394, 397, INIT_RUN , 390–393, 395, 414, 441, 457, 420, 445, 449, 453 471, 473, 488, 489 550 Index

TAP instruction (cont.) TDO , 10 INIT_SETUP , 390–392, 394, 441, 457, TMS , 10 488, 489 TRST , 10 INTEST , 38–42, 44, 53, 57, 70, 74–77, 81, Test bus interface circuit (TBIC) , 234, 235, 90, 92–102, 106, 110, 120–122, 237–242, 245, 247, 250–253, 256, 165, 179, 240, 244, 248, 249, 259–262 254–256, 258, 264, 266, 282, 288, Test clock (TCK) 303, 306, 308, 316, 329, 460 buffered , 190–192 ISC_DISABLE , 165, 325, 326, 328, cycles in Run-Test/Idle , 326, 336, 337 338–340 falling edge , 12, 13, 16–18, 30, 112, 174, ISC_ENABLE , 165, 325–328, 330, 338, 284, 296–300, 303, 317, 324, 328, 339, 377 330, 351, 353, 393 ISC_PROGRAM , 165, 336–340 ground bounce , 174, 175, 178, 271–273, PRELOAD , 28, 36, 37, 40, 41, 57, 70, 76, 295 93–95, 97, 98, 100–102, 110, 114, level translation , 191 116, 122, 165, 168, 189, 240, 249, maximum clock frequency , 317 282, 303, 306, 330, 352, 353, 358, rising edge , 12–18, 152, 186, 297, 303, 366, 387, 391, 392, 442 305 PROBE , 240, 241, 244, 246, 248, 253, stop state , 68 256, 261, 264 Test data in (TDI) RUNBIST , 14, 39–42, 76, 77, 93–95, pin placement , 173–174 97–102, 106, 122–123, 172, 181, shorted to TDO , 124, 126 183, 186, 187, 240, 248, 253–254, Test data out (TDO) 306, 326, 329, 435 actively driving , 63, 81 SAMPLE , 36, 151, 249, 460 disabled , 15 SELECTIVE_TOGGLE , 352, 353, 355, shifting data , 20 358–360, 366 Testing SHUTDOWN , 378 Ad-Hoc , 3 TMP_STATUS , 387, 392, 395 analog in-circuit , 203–217 TOGGLE_SETUP , 352, 354 background system diagnostics , 168 USERCODE , 22, 36, 70, 93–95, 97, 98, basic BIST test algorithm , 122–123 100–102, 186, 240, 249, 282 basic test algorithm , 115–116, 120, 122, user-deﬁ ned , 12, 42, 71, 72, 106, 144, 185 129, 130, 353 TAP state BIST , 9, 22, 39, 42, 109, 118, 122, 123, capture-DR , 14, 16–18, 22, 34–40, 52, 70, 144–145, 162, 198, 393, 431, 434, 72, 90, 112, 122, 142, 143, 152, 441, 447 154, 155, 181, 186, 279, 297, 303, board-level self-test , 42 305, 354, 394, 419, 420, 436 boundary-scan chains , 32–33, 53, 99, run-test/idle , 13–14, 16, 17, 40, 76, 113, 123–145, 165, 187, 192, 197, 198, 122, 125, 144, 283–285, 291, 300, 365, 488 303, 317, 318, 325–328, 336–340, chain integrity , 22, 124–126, 143, 173 351–353, 357, 358, 444, 445, 449 CMOS IDDQ , 10 update-DR , 16–18, 28, 37–39, 112, 113, concurrent monitoring , 154–155 129, 155, 167, 168, 174, 175, 278, connection , 126, 139–140 279, 283, 296, 297, 300, 330, 353, control of critical nodes , 194–195 387, 393, 396, 420, 421, 436, 445 customized , 230 Target register , 17, 21, 34, 39, 40, 57, 76, 112, DC parametric (IC) , 149–151 175, 336, 337, 435, 436 differential pins , 367 TBIC. See Test Bus Interface Circuit (TBIC) edge connector functional , 4–6, 171 Test access port (TAP) emulation functions , 9 compatibility with 1149.4 , 48 fault dictionary , 120 TCK , 10 hardware development support , 163 TDI , 10 high frequency , 227 Index 551

hot mock-ups , 4, 5 cell mapping , 304 hybrid digital/analog , 42 data capture , 154 IC , 7, 19, 39, 53, 120–122, 159, 354, 382 DC-coupled response , 294 IC BIST , 122–123 DC response , 295–298 In-Circuit , 6–8, 31, 40, 41, 47, 116–120, defect detection , 288 129, 146–148, 164, 171, 179, documented in BSDL , 66, 68 203–218, 226, 280, 344, 347 edge detection , 301 in-circuit boundary-scan , 118–120, 139 edge sensitive , 287 interaction , 140–144, 147 guaranteed AC-coupling , 301 interconnect , 65, 126–141, 144, 148, 158, initial state , 296, 297 187, 191, 194, 198, 228, 230, 232, integrated AC/DC , 302 237, 239–246, 249, 250, 257, 266, low-pass time constant , 300 267, 279, 356, 366, 441 memory , 296, 297, 300, 303 interconnect opens , 134–139 noise rejection , 257, 258, 295 interconnect shorts , 129–130, 135, 136, output , 288, 299, 300 138, 142, 182 self-referenced , 280, 288, 293, 298 limited access , 217–223 silicon overhead , 320 limited access node voltage , 221–223 single-ended , 287 logic analyzer , 36, 151 transparent , 287 mixed digital/analog , 109, 158–161 Test reset (TRST) , 10–13, 20, 33, 44, 57, 67, module , 48, 200 105, 111, 123, 187, 194, 195, 233, multi-chip modules , 161–162 326, 328, 386, 390, 393, 396, 407, node voltage , 220–223 420, 440, 449 noise rejection , 257, 258, 295 assertion , 12, 18, 33, 123, 326 non-digital devices , 158 Texas instruments 74ABT8996 , 200 non-scan ICs , 155–157 Texas instruments 74ACT8990 , 195 parallel impedances , 209 Texas instruments 74ACT8997 , 189, 196, 197, performance , 162, 204 200 personal tester , 117–118 Texas instruments 74ACT8999 , 189, 196, 200 personal tester within ATE , 117–118 Texas instruments 74BCT8244 , 42, 44 printed circuit board, 3, 7, 32, 224, 272, 343 Texas instruments 74BCT8373 , 178 pseudo-random patterns , 42, 144 Texas instruments 74BCT8374 , 58, 61, 78, 82, RAM arrays , 23 178 sample mode , 149, 151–154 Through-hole pin , 7 self-test , 14, 22, 39, 40, 42, 144, 172, 265 Time constant signature analysis , 42, 144, 171 decay , 278, 279, 295, 301 simulator-based functional , 6 high-pass , 293, 300, 301, 317 stop-on-ﬁ rst-fail , 116, 436 low-pass , 293, 300, 301, 317 system level , 148, 189, 198, 266 TMP operational modes undetectable shorts , 157 persistence off , 392, 420 unpowered analog , 209 persistence on , 393, 396, 420 unpowered shorts testing , 119, 126, 139 Toggle control register , 351–354, 358, 366 X-ray laminography , 133, 375 Tolerance TestJet , 343 of component values , 205 Test mode persistence (TMP) , 10, 12, 38, 198, distribution , 205 324, 385–387, 392, 394–397, 420, nominal values , 205 453 Transition Test mode select (TMS) deﬁ ned , 293 buffered , 190, 192 detecting , 283 level translation , 191 edge speed , 285, 286 Test receiver generating , 283 AC-coupled response , 294–295 invalid , 294, 295, 300 AC Response , 298–301 noise , 272, 299 552 Index

Transition (cont.) VHSIC hardware description language use of mission driver , 285 (VHDL), 50, 51, 56–58, 61–63, 65, valid , 295, 298–300, 303, 319 68, 85, 90, 105, 181, 304, 401–403, 405, 419, 440 Vias , 7, 8, 171, 224, 225 U blind , 171 Unpowered capacitive opens detection , 343 Voltage programmability , 458 sense plate , 344–347 Voltage scaling , 458 Update ﬂ ip-ﬂ op (UPD) , 23, 27, 28, 37–39, 41, Voltage variations , 458 74, 91, 96, 112, 167, 180, 181, 283, 303, 353, 358, 387, 389, 398 UUT. See Device Under Test W Walking-bit sequence , 131, 133

V Very large-scan integration (VLSI) , 44, 119, X 171, 174 Xilinx 4005 , 31, 32 VHDL identiﬁ ers. See Boundary-scan Xilinx XC9500 , 31 description language (BSDL), X-ray laminography , 133, 375 identiﬁ er X-Y coordinate location data , 8