TAP Controller with Inputs TCK, TMS, and TRST*

Module 8 Testing of Embedded System Version 2 EE IIT, Kharagpur 1 Lesson 41 Boundary Scan Methods and Standards Version 2 EE IIT, Kharagpur 2 Instructional Objectives After going through this lesson the student would be able to • Explain the meaning of the term Boundary Scan • List the IEEE 1149 series of standards with their important features • Describe the architecture of IEEE 1149.1 boundary scan and explain the functionality of each of its components • Explain, with the help of an example, how a board-level design can be equipped with the boundary scan feature • Describe the advantages and disadvantages of the boundary scan technique Boundary Scan Methods and Standards 1. Boundary Scan History and Family Boundary Scan is a family of test methodologies aiming at resolving many test problems: from chip level to system level, from logic cores to interconnects between cores, and from digital circuits to analog or mixed-mode circuits. It is now widely accepted in industry and has been considered as an industry standard in most large IC system designs. Boundary-scan, as defined by the IEEE Std. 1149.1 standard [1-3], is an integrated method for testing interconnects on printed circuit board that is implemented at the IC level. Earlier, most Printed Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. Recent advances with VLSI technology now enable microprocessors and Application Specific Integrated Circuits (ASICs) to be packaged into fine pitch, high count packages. The miniaturization of device packaging, the development of surface-mounted packaging, double-sided and multi-layer board to accommodate the extra interconnects between the increased density of devices on the board reduces the physical accessibility of test points for traditional bed-of-nails in-circuit tester and poses a great challenge to test manufacturing defects in future. The long-term solution to this reduction in physical probe access was to consider building the access inside the device i.e. a boundary scan register. In 1985, a group of European companies formed Joint European Test Action Group (JETAG) and by 1988 the Joint Test Action Group (JTAG) was formed by several companies to tackle these challenges. The JTAG has developed a specification for boundary-scan testing that was standardized in 1990 by IEEE as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement that contains a description of the boundary-scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers are using boundary-scan. Figure 41.1 gives an overview of the boundary scan family, now known as the IEEE 1149.x standards. Version 2 EE IIT, Kharagpur 3 Number Description Year IEEE 1149.1 Testing of digital chips and interconnections Std 1149.1 – 1990 between chips IEEE 1149.1a Added supplement A. Rewrite of the chapter Std 1149.1a – 1993 describing boundary register IEEE 1149.1b Supplement B - formal description of the Std 1149.1b – 1994 boundary-scan Description Language (BSDL) IEEE 1149.1c Corrections, clarifications and enhancements of Std 1149.1 –2001 IEEE Std 1149.1a and Std 1149.1b. Combines 1149.1a & 1149.1b IEEE 1149.2 Extended Digital Serial Interface. It has merged Obsolete with 1149.1 group. IEEE 1149.3 Direct Access Testability Interface Obsolete IEEE 1149.4 Test Mixed-Signal and Analog assemblies Std. 1149.4 – 1999 IEEE 1149.5 Standard Module Test and Maintenance (MTM) Std. 1149.5 –1995 Bus Protocol. Deals with test at system level, 1149.2 has merged with. IEEE 1149.6 Includes AC-coupled and/or differential nets. Std 1149.6 - 2002 IEEE 1532 It is a derivative standard for in-system 2000 programming (ISP) of digital devices. Fig. 41.1 IEEE 1149 Family The Std. 1149.1, usually referred to as the digital boundary scan, is the one that has been used widely. It can be divided into two parts: 1149.1a, or the digital Boundary Scan Standard, and 1149.1b, or the Boundary Scan Description Language (BSDL) [1,6]. Std. 1149.1 defines the chip level test architecture for digital circuits, and Std. 1149.1b is a hardware description language used to describe boundary scan architecture. The 1149.2 defines the extended digital series interface in the chip level. It has merged with 1149.1 group. The 1149.3 defines the direct access interface in contrast to 1149.2. Unfortunately this work has been discontinued. 1149.4 IEEE Standard deals with Mixed-Signal Test Bus [4]. This standard extends the test structure defined in IEEE Std. 1149.1 to allow testing and measurement of mixed-signal circuits. The standard describes the architecture and the means of control and access to analog and digital test data. The Std.1149.5 defines the bus protocol at the module level. By combining this level and Std.1149.1a one can easily carry out the testing of a PC board. 1149.6 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks is released in 2002. This standard augments 1149.1 for the testing of conventional digital networks and 1149.4 for analog networks. The 1149.6 standard defines boundary-scan structures and methods Version 2 EE IIT, Kharagpur 4 required to test advanced digital networks that are not fully covered by IEEE Std. 1149.1, such as networks that are AC-coupled, differential, or both. 1532 IEEE Standard is developed for In-System Configuration of Programmable Devices [5]. This extension of 1149.1 standardizes programming access and methodology for programmable integrated circuit devices. Devices such as CPLDs and FPGAs, regardless of vendor, that implement this standard may be configured (written), read back, erased and verified, singly or concurrently, with a standardized set of resources based upon the algorithm description contained in the 1532 BSDL file. JTAG Technologies programming tools contain support for 1532-compliant devices and automatically generate the applications. Clearly the testing of mixed-mode circuits at the various levels of integration will be a critical test issue for the system-on-chip design. Therefore there is a demand to combine all the boundary scan standards into an integrated one. 2. Boundary Scan Architecture The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches, to each pin on the device. Figure 41.2 [1] illustrates the main elements of a universal boundary-scan device. The Figure 41.2 shows the following elements: • Test Access Port (TAP) with a set of four dedicated test pins: Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) and one optional test pin Test Reset (TRST*). • A boundary-scan cell on each device primary input and primary output pin, connected internally to form a serial boundary-scan register (Boundary Scan). • A TAP controller with inputs TCK, TMS, and TRST*. • An n-bit (n >= 2) instruction register holding the current instruction. • A 1-bit Bypass register (Bypass). • An optional 32-bit Identification register capable of being loaded with a permanent device identification code. Version 2 EE IIT, Kharagpur 5 1149.1 Chip Architecture Boundary-Scan Register Internal Register Any Digital Chip 1 Bypass Register TDI TDO Identification Register 1 Instruction Register TMS TAP Controller TCK 1 TRST* (optional) Fig. 41.2 Main Elements of a IEEE 1149.1 Device Architecture The test access ports (TAP), which define the bus protocol of boundary scan, are the additional I/O pins needed for each chip employing Std.1149.1a. The TAP controller is a 16-state final state machine that controls each step of the operations of boundary scan. Each instruction to be carried out by the boundary scan architecture is stored in the Instruction Register. The various control signals associated with the instruction are then provided by a decoder. Several Test Data Registers are used to stored test data or some system related information such as the chip ID, company name, etc. 2.1 Bus Protocol The Test Access Ports (TAPs) are genral purpose ports and provide access to the test function of the IC between the application circuit and the chip’s I/O pads. It includes four mandatory pins TCK, TDI, TDO and TMS and one optional pin TRST* as described below. All TAP inputs and outputs shall be dedicated connections to the component (i.e., the pins used shall not be used for any other purpose). • Test Clock Input (TCK): a clock independent of the system clock for the chip so that test operations can be synchronized between the various parts of a chip. It also synchronizes the operations between the various chips on a printed circuit board. As a convention, the Version 2 EE IIT, Kharagpur 6 test instructions and data are loaded from system input pins on the rising edge of TCK and driven through system output pins on its falling edge. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency (up to a maximum of some MHz). It can be even pulsed at varying rates. • Test Data Input (TDI): an input line to allow the test instruction and test data to be loaded into the instruction register and the various test data registers, respectively.

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