Communications Capabilities of Minicomputers and Small Business

Total Page:16

File Type:pdf, Size:1020Kb

Communications Capabilities of Minicomputers and Small Business C13-010-221 Processors Communications Capabilities of Minicomputers and Small Business Computers ( Industrial Infomark Infotecs Infomark Inforex Control Center MANUFACTURER & MODEL Micro Systems OMS-II OMS-III 9000 5000SX II MAIN STORAGE Min.lMax. capacity, words or bytes 512K 256K 512K 256K 1M NO. WORKSTATIONS CONNECTABLE 16 16 24 24 16 COMMUNICATIONS Maximum no. of lines 24 16 24 - 16 Synchronous Optional Opt.; 19.2K bps Opt.; 19.2K bps Std.; 9600 bps Std.; 300-19,200 bps Asynchronous Std.; 9600-19.2K bps Std.; 19.2K bps Std.; 19.2K bps Optional Std.; 300-19,200 bps Protocols supported Async 2780/3780 2780/3780 2780/3780, HASP, - Network architecture supported Turbodos (opt.) - - ULTRANET, ARCNET - RJE terminals emulated - 2780/3780 2780/3780 See Comments - IBM 3270 emulation No - - Yes - PRICING & AVAlLA81L1TY Purchase price of basic system, $ 3,000-12,000 67,000 113,300 44,630 6,995 Purchase price of memory module, $ - - - - - Monthly maint. price of basic system, $ - - - 800 - Discounts available Dealer, OEM - - - - Date of first U.S. delivery May 1979 1976 1976 July 1981 April 1980 Number installed to date 500 110 40 Contact vendor Over 1000 COMMENTS New table-top pack- 8asic system price 8asic system price RJE terminals Programs compatible age; 5.5M-byte includes hardware, includes hardware, emulated include with DEC PDP-8; Winchester drive application software application software, 2770, 2780, 3770, complete systems and available installation, and train- installation, and 3780, RES; System software sold & ser- ing; *600- and 900- training 9000 is a distributed viced nationwide by Ipm printers are information processing Infotecs' dealers optional system, specifically addressing distributed data entry and file management solutions for business MAli Basic Four MAl/Basic Four MAl/Basic Four MAli Basic Four MANUFACTURER & MODEL MAl/Basic Four System 210 System 310 System 510 System 610 System 710 MAIN STORAGE Min.lMax. capacity, words or bytes 64K 256K 256K 192K 256K NO. WORKSTATIONS CONNECTABLE 16 16 16 16 32 COMMUNICATIONS Maximum no. of lines 16 16 16 16 32 Synchronous Opt.; 9600 bps Opt.; 9600 bps Opt.; 9600 bps Opt.; 9600 bps Opt.; 9600 bps Asynchronous Std.; 9600 bps Std.; 9600 bps Std.; 9600 bps Std.; 9600 bps Std.; 9600 bps Protocols supported Bisync Bisync Bisync Bisync Bisync Network architecture supported BFBIN BFBIN BFBIN BFBIN BFBIN. RJE terminals emulated 2780/3780 2780/3780 2780/3780 278013780 2780/3780 IBM 3270 emulation Yes Yes Yes Yes Yes PRICING & AVAILABILITY Purchase price of basic system, $ 25,740 (64K bytes) 55,885 (96K bytes) 50,360 (64K bytes) 51,400 (64K bytes) 69,100 (96K bytes) Purchase price of memory module, $ 2,375 (32K bytes) 2,375 (32K bytes) 2,375 (32K bytes) 2,240 (32K bytes) 2,375 (32K bytes) Monthly maint. price of basic system, $ 270 504 437 424 593.50 Discounts available - - - - - Date of first U.S. delivery 1981 1982 1980 1978 1982 Number installed to date 14,500 (all models) 14,500 (all models) 14,500 (all models) 14,500 (all models) 14,500 (all models) COMMENTS Price includes 64KB Price includes 96KB Price includes 64KB Price includes 64KB Price includes 96KB memory, 10MB fixed memory, 40MB fixed memory, 20MB disk memory, 35MB disk memory, two 35MB disk, 8O-cps printer, disk, 150-lpm printer, drive & pack, op- drive & pack. w/op. disk drives & packs 9.2MB magnetic tape reel-to-reel tape drive, erating system, 120- sys., 1 60 cps pr inter, w/op. sys., 3OO-lpm cartridge drive, and and 2 VDTs cps printer, 1 VOT, and one VDT printer, and one VOT one VDT & 9.2MB magnetic tape unit FEBRUARY 1983 © 1983 DATAPRO RESEARCH CORPORATION, DELRAN, NJ 08075 USA REPRODUCTION PROHIBITED C13-01 0~222 Proc~ssors Communications Capabilities of Minicomputers and Small Business Computers M~rcator Microdata Microdata MAl/Basic Four MCM Business MANUFACTURER & MODEL Computers Systems Reality Series Reality Series System 730 MCM/POWER 2000 4000 System 5000 MAIN STORAGE Min.lMax. capacity, words or bytes 256K 64K 1M 64K 128K NO. WORKSTATIONS CONNECTABLE 32 8 16 8 32 COMMUNICATIONS Maximum no. of lines 32 199 16 8 32 SynChronous Opt.; 9600 bps Opt.; 19.2K bps Optional Opt.; to 9600 bps Opt.; to 9600 bps Asynchronous Std.; 9600 bps Opt.; to 19.2K bps Optional No No Protocols supported Bisync Various Bisync Async, bisync Async, bisync Network architecture supported 8FBIN None - - - RJE terminals emulated 2780/3780 Various 2780/3780 See Comments See Comments IBM 3270 emulation Yes No Optional No No PRICING & AVAILABILITY Purchase price of basic system, $ 95,000 (96K bytes) Contact vendor 35,000 34,500-36,200 42,700 Purchase price of memory module, $ 2,240 (32K bytes) Contact vendor - 2,100 (16K bytes) 2,950 (32K bytes) Monthly maint. price of basic system, $ 766 Contact vendor - 350-340 350 Discounts available - Contact vendor - - - Date of first U.S. delivery 1978 September 1980 January 1982 December 1977 November 1973 Number installed to date 14,500 (all models) - - 4000 (all mod.) 4000 (all mod.) COMMENTS Price includes 96KB MCM/POWER is a Packaged system in- Packaged system in- memory, two 75MB multi-user, hard-disk, cludes 32KB MOS cludes 64KB MOS disk drives & packs upgradeable and up- memoiy, magnetic memory, magnetic w/op. sys., 300 Ipm ward compatible tape, 10MB disk drive, tape, 30MB disk drive, printer, and four VDTs version of the MCMI 165 cps printer, and 165 cps printer, and 900 1 CRT; RJE terminals 1 CRT; RJE terminals emulated inelude emulated include HASP, 2780/3780, HASP, 2780/3780, 2770,3741; 2770,3741; 'SCREENPRO 'SCREENPRO , Microtech Microdata Microdata Microtech Mitsubishi Business Business Electronics MANUFACTURER & MODEL Reality Series Reality Series Systems Systems 6000 8000 America. Inc. 300 Series 400 Series 8028 MAIN STORAGE Min.lMax. capacity, words or bytes 256K 512K 1M 1M 256K NO. WORKSTATIONS CONNECTABLE 32 48 8to 56 16 4 COMMUNICATIONS Maximum no. of lines 32 48 56 56 32 Synchronous Opt.; to 9600 bps Opt.; to 9600 bps - - Opt.; 1200-9600 bps Asynchronous No No Std.; 30-9600 bps Std.; 30-9600 bps Opt.; 300-9600 bps Protocols supported Async. bisync Async, bisync Async Async BSC, BC-l Network architecture supported - - None None - RJE terminals emulated See Comments See Comments None None - IBM 3270 emulation No No No No No PRICING & AVAILABILITY Purchase price of basic system. $ 52,800-67,600 64,975-99,975 11,000 (64K) 11,000 (64K) 38,000 Purchase price of memory module, $ 2,950 (32K bytes) 4,900 (128K bytes) 3,000 (64K), 6,300 3,000 (64K), 6,300 3,800 (128K bytes) Monthly maint. price of basic system, $ 395-515 595-715 Contact vendor Contact vendor 268 Discounts available - - Contact vendor Contact vendor - Date of first U.S. delivery November 1973 October 1 979 October 1979 May 1979 August 1980 Number installed to date 4000 (all mod.) 4000 (all mod.) 100 NA NA COMMENTS Packaged system in- Packaged system in- System 300 W34S, System 400 W158S eludes 64KB MOS cludes 256KB MOS for $23,650, in- includes 158MB memory, magnetic memory, magnetic cludes 34MB Win- Winchester, 'A-in. tape, 48MB disk tape, 128MB disk chester, 'A-in. tape tape drive in 29-in. drive. 165 cps drive, 300 Ipm printer, drive in 29-in. enclosure with printer, and 1 CRT; and 2 CRTs; RJE ter- enclosure with operating system RJE terminals minals emulated in- operating system; emulated include clude HASP, 27801 up to four 34MB HASP. 2780/3780. 3780,2770.3741; or 68MB drives can If 2770,3741; PEP (Performance be attached to sys- 'SCREENPRO Enhanced Processor) tem; $26,650 for 1"< provides improved Sys. 300 W68S CPU time; 'SCREEN- PRO ~ © 1983 DATAPRO RESEARCH CORPORATION, DELRAN, NJ 08075 USA FEBRUARY 1983 REPRODUCTION PROHIBITED Datapro Reports on C13-010-201 cDlapn)- Data Communications Processors ( Communications Processors: Technology Overview In this report: Synopsis Technology Editor's Note physical entity, separate from its par­ Basics ....................... -202 This report examines the technology ticipating hosts and terminals. The of communications processors. For implementation of a physically sepa­ Products ................... -204 information on the market, see rate communications function oc­ "Communications Processors: Mar­ curred through a system of small Selection ket Overview"; for comparison col­ dedicated computers. Users placed Guidelines ................. -206 umns detailing the features of key these communications processors at products, see "Communications Pro­ the front end of a mainframe or al­ cessors: Comparison Columns." lowed them to function indepen­ dently as concentrators and switches Report Highlights within their architectures. The term "communications processor" describes not only a spe­ In most communications processors, cific category of equipment but also under the direction of the CPU, systems that perform communica­ some components perform functions tions processing functions and other for the whole communications pro­ services. Datapro's definition of cessor, while others perform func­ communications processors covers tions for specific groups of lines. multifunctional, intelligent systems Among the former are host inter­ dedicated to communications and faces, input/output (110) processors, serving as nodes in a network. These reference clocks, and operator inter­ systems generally include three basic faces. Among the latter are the pro­ types of products: front-end proces­ cessor's line bases and line sets. sors, intelligent switches, and remote concentrators. There are two kinds of network ar­ chitectures: those for communica­ In the late 1970s, IBM's SNA and tions among computers and the ISO's OSI model advanced data terminals from a specific vendor, communications as a function sepa­ and those for open communications rate from applications processing. regardless of the vendor of the com­ SNA and OSI defined a network as a municating devices. This report discusses communica­ ',- -By Barbara Rinehart tions processor design, evolution, Associate Editor/Analyst and position in modern network ar­ chitectures.
Recommended publications
  • Unisys 2001 Annual Report
    Services and Technology: Helping You Create Business Value. Unisys Unisys Corporation 2001 Annual Report Unisys Unisys is a worldwide information technology ser- vices and solutions company whose 39,000 people Contents help clients in more than 100 countries utilize tech- Letter to Stakeholders 1 nology to seize opportunities, overcome challenges Chairman, President and CEO Larry Weinbach reviews 2001 and succeed in the global economy. and outlines the Unisys strategy for 2002. Chairman’s Q&A 3 Larry Weinbach answers operational questions. Our company offers a rich portfolio of business Our Work: Services and Technology 4 solutions led by our expertise in consulting and What we do. Our Success: Unisys Customers 6 systems integration, outsourcing, network services Who we do it for. and security, coupled with leading enterprise-class Our Strength: Unisys People 11 Who we are. server and related technologies. Primary vertical Our Premise: Educating 12 for Leadership markets for Unisys worldwide are the financial How we innovate. Financial Review 13 services, transportation, communications, media, Corporate Officers 47 commercial and public sectors, including U.S. Board of Directors 48 federal government customers. Investor Information 49 Unisys is headquartered in Blue Bell, Pennsylvania, in the Greater Philadelphia area. For more informa- tion on the company, access the Unisys home page on the World Wide Web at www.unisys.com. Investor information can be found at www.unisys.com/investor. About our cover Unisys provides the solution to the puzzle of how organizations can use technology to create business value. Our cover graphically represents what we do and shows how we intertwine our expertise in the service areas of outsourcing, network services and systems integration, as well as in technology.
    [Show full text]
  • Emerging Technologies Multi/Parallel Processing
    Emerging Technologies Multi/Parallel Processing Mary C. Kulas New Computing Structures Strategic Relations Group December 1987 For Internal Use Only Copyright @ 1987 by Digital Equipment Corporation. Printed in U.S.A. The information contained herein is confidential and proprietary. It is the property of Digital Equipment Corporation and shall not be reproduced or' copied in whole or in part without written permission. This is an unpublished work protected under the Federal copyright laws. The following are trademarks of Digital Equipment Corporation, Maynard, MA 01754. DECpage LN03 This report was produced by Educational Services with DECpage and the LN03 laser printer. Contents Acknowledgments. 1 Abstract. .. 3 Executive Summary. .. 5 I. Analysis . .. 7 A. The Players . .. 9 1. Number and Status . .. 9 2. Funding. .. 10 3. Strategic Alliances. .. 11 4. Sales. .. 13 a. Revenue/Units Installed . .. 13 h. European Sales. .. 14 B. The Product. .. 15 1. CPUs. .. 15 2. Chip . .. 15 3. Bus. .. 15 4. Vector Processing . .. 16 5. Operating System . .. 16 6. Languages. .. 17 7. Third-Party Applications . .. 18 8. Pricing. .. 18 C. ~BM and Other Major Computer Companies. .. 19 D. Why Success? Why Failure? . .. 21 E. Future Directions. .. 25 II. Company/Product Profiles. .. 27 A. Multi/Parallel Processors . .. 29 1. Alliant . .. 31 2. Astronautics. .. 35 3. Concurrent . .. 37 4. Cydrome. .. 41 5. Eastman Kodak. .. 45 6. Elxsi . .. 47 Contents iii 7. Encore ............... 51 8. Flexible . ... 55 9. Floating Point Systems - M64line ................... 59 10. International Parallel ........................... 61 11. Loral .................................... 63 12. Masscomp ................................. 65 13. Meiko .................................... 67 14. Multiflow. ~ ................................ 69 15. Sequent................................... 71 B. Massively Parallel . 75 1. Ametek.................................... 77 2. Bolt Beranek & Newman Advanced Computers ...........
    [Show full text]
  • Efficient Computation of LALR(1) Look-Ahead Sets
    Efficient Computation of LALR(1) Look-Ahead Sets FRANK DeREMER and THOMAS PENNELLO University of California, Santa Cruz, and MetaWare TM Incorporated Two relations that capture the essential structure of the problem of computing LALR(1) look-ahead sets are defined, and an efficient algorithm is presented to compute the sets in time linear in the size of the relations. In particular, for a PASCAL grammar, the algorithm performs fewer than 15 percent of the set unions performed by the popular compiler-compiler YACC. When a grammar is not LALR(1), the relations, represented explicitly, provide for printing user- oriented error messages that specifically indicate how the look-ahead problem arose. In addition, certain loops in the digraphs induced by these relations indicate that the grammar is not LR(k) for any k. Finally, an oft-discovered and used but incorrect look-ahead set algorithm is similarly based on two other relations defined for the fwst time here. The formal presentation of this algorithm should help prevent its rediscovery. Categories and Subject Descriptors: D.3.1 [Programming Languages]: Formal Definitions and Theory--syntax; D.3.4 [Programming Languages]: Processors--translator writing systems and compiler generators; F.4.2 [Mathematical Logic and Formal Languages]: Grammars and Other Rewriting Systems--parsing General Terms: Algorithms, Languages, Theory Additional Key Words and Phrases: Context-free grammar, Backus-Naur form, strongly connected component, LALR(1), LR(k), grammar debugging, 1. INTRODUCTION Since the invention of LALR(1) grammars by DeRemer [9], LALR grammar analysis and parsing techniques have been popular as a component of translator writing systems and compiler-compilers.
    [Show full text]
  • SAKI: a Fortran Program for Generalized Linear Inversion of Gravity and Magnetic Profiles
    UNITED STATES DEPARTMENT OF THE INTERIOR GEOLOGICAL SURVEY SAKI: A Fortran program for generalized linear Inversion of gravity and magnetic profiles by Michael Webring Open File Report 85-122 1985 This report is preliminary and has not been reviewed for conformity with U.S. Geological Survey editorial standards. Table of Contents Abstract ------------------------------ 1 Introduction ---------------------------- 1 Theory ------------------------------- 2 Users Guide ---------------------------- 7 Model File -------------------------- 7 Observed Data Files ---------------------- 9 Command File ------------------------- 10 Data File Parameters ------------------- 10 Magnetic Parameters ------------------- 10 General Parameters -------------------- H Plotting Parameters ------------------- n Annotation Parameters ------------------ 12 Program Interactive Commands ----------------- 13 Inversion Function ---------------------- 16 Examples ------------------------------ 20 References ----------------------------- 26 Appendix A - plot system description ---------------- 27 Appendix B - program listing -------------------- 30 Abstract A gravity and magnetic inversion program is presented which models a structural cross-section as an ensemble of 2-d prisms formed by linking vertices into a network that may be deformed by a modified Marquardt algorithm. The nonuniqueness of this general model is constrained by the user in an interactive mode. Introduction This program fits in a least-squares sense the theoretical gravity and magnetic response of
    [Show full text]
  • Engineering Strategy Overview Preliminary
    March 1982 Engineering Preliminary Strategy Company Overview Confidential If.-t8···· L..4L ~ \:')' j.~.! / .;.' ' 1985 1990 1995 2000 - P,O S SIB L E DEC PRO Due T S - $lJOO cellular radio net discontinouous.100 word ~ lim! ted context HANDHELD speaker independent speaker independent $1.0K speech recogn. • sketchpad , interpretation Glata structures , ' & relat~onsh~ps object filing natural languaqe (invisible, protected structures) $40K I CAB I NET I ,4 (dedicated fixture) ~~~n limited context [:~~~~e~ ~~~:~~i:ti~n ~ ak rind pendent • voice ~tuate~ retrieval spe ~ e _ .. • te1econferenc1ng center cont1nued speechlrecogn~tion " ;., encryption associa tiveJparallel a;;;'e'los (, ..j." .---~ provide CAtt= ASSISTANT -------...--- .. • LIBRARlj\N ~ ?ertified "best match" retrieval ~ (secure) os (holographic? ) $650K BD 1/15/81 PRELIMINARY ENGINEERING STRATEGY OVERVIEW MARCH lYtil SECONIJ IJRAFT PRELIMINARY ENGINEERING STRATEGY OVERVIEW TABLE OF CONTENTS ,Preface Chapter I fhe Product Strategy and Transitioning to the Fifth Generation - Product Strategy Overview - The Transitions - Personal Computer Clusters, PCC, Are An Alternative to Timeshared Computers - The Product Strategy - Fifth and Sixth Computer Technology Generations - Uistributed Processing and Limits to Its Growth Chapter II Essays on the Criteria for Allocation of Engineering Resources - Overview, - Heuristics for Building Great Products, - Proposed Resource Allocation Criteria - UEC's Position in the VAN - Buyout Philosophy/Process/Criteria - Example of a "Make vs Buy" Analysis - Engineering Investment Sieve Chapter III Essays on Strategic Threats and Opportunities - Uverview, - Strategic Threats - Getting Organized in Engineering and Manufacturing to Face Our Future Competitors p - View of Competitors ---~,.~".~.-~ l f;t-1) IPrT Co?"! v. 7U/L, / IJ ...J - Te-Iecommunications Environment ) ;2f e-c.. - Competitive TeChnology Exercise, ltv • Chapter IV TeChnology Managers Committee Report ,MC- .
    [Show full text]
  • Multiple Instruction Issue in the Nonstop Cyclone System
    ~TANDEM Multiple Instruction Issue in the NonStop Cyclone System Robert W. Horst Richard L. Harris Robert L. Jardine Technical Report 90.6 June 1990 Part Number: 48007 Multiple Instruction Issue in the NonStop Cyclone Processorl Robert W. Horst Richard L. Harris Robert L. Jardine Tandem Computers Incorporated 19333 Vallco Parkway Cupertino, CA 95014 Abstract This paper describes the architecture for issuing multiple instructions per clock in the NonStop Cyclone Processor. Pairs of instructions are fetched and decoded by a dual two-stage prefetch pipeline and passed to a dual six-stage pipeline for execution. Dynamic branch prediction is used to reduce branch penalties. A unique microcode routine for each pair is stored in the large duplexed control store. The microcode controls parallel data paths optimized for executing the most frequent instruction pairs. Other features of the architecture include cache support for unaligned double­ precision accesses, a virtually-addressed main memory, and a novel precise exception mechanism. lA previous version of this paper was published in the conference proceedings of The 17th Annual International Symposium on Computer Architecture, May 28-31, 1990, Seattle, Washington. Dynabus+ Dynabus X Dvnabus Y IIIIII I 20 MBIS Parallel I I II 100 MbiVS III I Serial Fibers CPU CPU CPU CPU 0 3 14 15 MEMORY ••• MEMORY • •• MEMORY MEMORY ~IIIO PROC110 IIPROC1,0 PROC1,0 ROC PROC110 IIPROC1,0 PROC110 F11IOROC o 1 o 1 o 1 o 1 I DISKCTRL ~ DISKCTRL I I Q~ / \. I DISKCTRL I TAPECTRL : : DISKCTRL : I 0 1 2 3 /\ o 1 2 3 0 1 2 3 0 1 2 3 Section 0 Section 3 Figure 1.
    [Show full text]
  • Business System 300A
    OPERATOR'S GUIDE ~ Business System 300A Part No. 2240275·9701 * B July 1985 ~rEXAS INSTRUMENTS LIST OF EFFECTIVE PAGES INSERT LATEST CHANGED PAGES AND DISCARD SUPERSEDED PAGES Note: The changes in the text are indicated by a change number at the bottom of the page and a vertical bar in the outer margin of the changed page. A change number at the bottom of the page but no change bar indicates either a deletion or a page layout change. Business System 300A Operator's Guide (2240275-9701) Original Issue ................................... March 1984 Change 1 ..................................... May 1985 Change 2 ..................................... July 1985 Total number of pages in this publication is 128 consisting of the following: PAGE CHANGE PAGE CHANGE PAGE CHANGE NO. NO. NO. NO. NO. NO. Cover ............ , .. 2 1-5 .................. 2 0-1/0-2 .............. 0 Effective Pages ....... 2 1-6 .................. 2 E-1 - E-2 ............. 0 iii ................... 0 1-6A/1-6B ............ 2 F-1 - F-6 ............. 0 iv ................... 2 1-7 - 1-8 .............. 1 G lossary-1 - v ................ , .. 1 2-1-2-8 .............. 0 Glossary-8 ......... 0 vi ................ " .. 2 2-9/2-10 .............. 1 Index-1 .............. 0 vii/viii ............ " .. 0 3-1 - 3-12 ............. 0 Index-2 .............. 1 ix ................ " .. 2 3-13 - 3-15 . .. 1 I ndex-3 - I ndex-4 ...... 0 x - xi ............. " .. 0 3-16 - 3-22 ............ 0 User's Response ...... 2 xii .................. 2 4-1 - 4-12 ............. 0 Business Reply ....... 2 1-1 .................. 2 5-1 - 5-16 ............. 0 I nside Cover ......... 2 1-2 ............... , .. 0 A-1-A-12 ............ 0 Cover ............... 2 1-3 ............... , .. 2 B-1 - B-6 ............
    [Show full text]
  • Michigan Terminal System (MTS) Distribution 3.0 Documentation
    D3.NOTES 1 M T S D I S T R I B U T I O N 3.0 August 1973 General Notes Distribution 3.0 consists of 6 tapes for the 1600 bpi copy or 9 tapes for the 800 bpi copy. All tapes are unlabeled to save space. The last tape of each set is a dump/restore tape, designed to be used to get started (for new installations) or for conversion (for old installations). Instructions for these procedures are given in items 1001 and 1002 of the documentation list (later in this writeup). The remaining tapes are "Distribution Utility" tapes containing source, object, command, data, and print files, designed to be read by *FS or by the Distribution program, which is a superset of *FS. A writeup for this distribution version of *FS is enclosed (item 1003). Throughout the documentation for this distribution, reference is made to the components of the distribution. Generally these references are made by the 3-digit component number, sometimes followed by a slash and a 1- or 2-digit sub- component number. For example, the G assembler (*ASMG) has been assigned component number 066. However, the assembler actually has many "pieces" and so the assembler consists of components 066/1 through 066/60. Component numbers 001 through 481 are compatible with the numbers used in distribution 2.0; numbers above 481 are new components, or in some cases, old components which have been grouped under a new number. Two versions of the distribution driver file are provided: 461/11 for the 1600 bpi tapes, and 461/16 for the 800 bpi tapes.
    [Show full text]
  • Fault Tolerance in Tandem Computer Systems
    1'TANDEM Fault Tolerance in Tandem Computer Systems Joel Bartlett * Wendy Bartlett Richard Carr Dave Garcia Jim Gray Robert Horst Robert Jardine Dan Lenoski DixMcGuire • Preselll address: Digital Equipmelll CorporQlioll Western Regional Laboralory. Palo Alto. California Technical Report 90.5 May 1990 Part Number: 40666 ~ TANDEM COMPUTERS Fault Tolerance in Tandem Computer Systems Joel Bartlett* Wendy Bartlett Richard Carr Dave Garcia Jim Gray Robert Horst Robert Jardine Dan Lenoski Dix McGuire * Present address: Digital Equipment Corporation Western Regional Laboratory, Palo Alto, California Technical Report 90.5 May 1990 Part Nurnber: 40666 Fault Tolerance in Tandem Computer Systems! Wendy Bartlett, Richard Carr, Dave Garcia, Jim Gray, Robert Horst, Robert Jardine, Dan Lenoski, Dix McGuire Tandem Computers Incorporated Cupertino, California Joel Bartlett Digital Equipment Corporation, Western Regional Laboratory Palo Alto, California Tandem Technical Report 90.5, Tandem Part Number 40666 March 1990 ABSTRACT Tandem produces high-availability, general-purpose computers that provide fault tolerance through fail­ fast hardware modules and fault-tolerant software2. This chapter presents a historical perspective of the Tandem systems' evolution and provides a synopsis of the company's current approach to implementing these systems. The article does not cover products announced since January 1990. At the hardware level, a Tandem system is a loosely-coupled multiprocessor with fail-fast modules connected with dual paths. A system can include a range of processors, interconnected through a hierarchical fault-tolerant local network. A system can also include a variety of peripherals, attached with dual-ported controllers. A novel disk subsystem allows a choice between low cost-per-byte and low cost-per-access.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Chapter 12 Computervision
    Chapter 12 Computervision According to a 1994 Wall Street Journal article, Philippe Villers decided to start a technology company shortly after listening to the minister at Concord, Massachusetts’ First Parish Church extol Martin Luther King’s accomplishments a few days after he was murdered in April 1968. Villers felt he needed to do something meaningful with his life and that there were two options – either become a social activist or start a company, make a lot of money and then use that money to change the world. Luckily for what eventually became the CAD/CAM industry, he chose the second path.1 Villers was technically well qualified to start Computervision, Inc. or CV is it was generally known. Born in Paris, France, he came to this country via Canada in the early 1940s to escape the Nazis. Villers had an undergraduate liberal arts degree from Harvard and a masters degree in mechanical engineering from MIT. He worked for several years in General Electric’s management training program followed by stints at Perkin Elmer, Barnes Engineering and the Link Division of Singer-General Precision with increasing levels of project management responsibility. At the time he decided to establish Computervision, Villers was Manager of Advanced Products at Concord Control in Boston. Villers spent much of his spare time in 1968 meeting with a group of business and technical associates including Steve Coons and Nicholas Negroponte (founder of the MIT Media Lab). Realizing that it takes more than good technical ideas to build a successful company, Villers decided to find a partner with more business experience to help jump start the enterprise.
    [Show full text]
  • Comparing UNIX with Other Systems
    Comparing UNIX with other systems Timothy DO' Chase Corporate Computer systems, Inc. 33 West Main Street Holmdel, New Jersey he original concept behind this article was to make a grand comparison between UNIX Tand several other well known systems. This was to beall encompassing and packed with vital information summarized in neat charts, tables and graphs. As the work began, the realization settled in that this was not only difficult to do, but would result in a work so boring as to beincomprehensible. The reader, faced with such awealth ofinformation would be lost at best. Conclusions would be difficult to draw and, in short, the result would be worthless. Mtertearfully filling my waste basket with the initial efforts, I regrouped and began by as­ king myself why would anyone be interested in comparing UNIX with another operating system? There appears to be only two answers. First, one might hope to learn something about UNIX by analogy. IfI understand the file system on MPEN and someone tells me that UNIX is like that except for such and so, then I might be more quickly able to under­ stand UNIX. This I felt was an unlikely motivation. After all, there are much simpler ways to learn UNIX. Instead, the motivation for comparing UNIX to other systems must come from a need to evaluate UNIX. Ifwe are aware of the features or short comings ofother systems, then we can benefit by evaluating UNIX relative to those systems. Choosing an operating system or computer is a major decision which we can benefit from or be stuck with for a long time.
    [Show full text]