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Innovation Drives the Evolution of Semiconductors Innovation Drives the Evolution of Semiconductors TOKYO ELECTRON ANNUAL REPORT 2018 PAGE 9 Innovation Drives the Evolution of Semiconductors Innovation Drives the Evolution of Semiconductors Innovation Drives the Evolution of Semiconductors limits of miniaturization (Figure 3). the aforementioned fins. The use of immersion lithography A well-known example, which is already widely used in mass Semiconductor Production Through the combination of new designs and materials technology, in which exposure is conducted in a liquid medi- production, is multiple patterning technology. This approach —A History of Innovation and the creation of new production methods, semiconduc- um with a high refractive index, helps to improve resolution, uses process technologies—such as deposition, lithography, tors have continued to evolve. Today, production technology but even this is insufficient to achieve the desired results. etch and cleaning—to supplement the resolution of expo- is approaching the physical limits of miniaturization, at the On top of this, aligning photomasks and wafers during sure equipment. Patterns with several times the density In 1965, Dr. Gordon Moore, one of Intel’s founders, made a atomic level. The world’s first commercial microprocessor, patterning is also a challenge. In the latest logic and DRAM achievable by the lithography resolution can now be formed prescient observation that eventually became Moore’s Law. manufactured with 10-micron technology, contained devices, transistors and other logic circuit elements are not by employing the litho-etch method, in which lithography Six years later, Intel released the world’s first commercial approximately 2,300 transistors per chip. In contrast, the only small, but arranged in complex configurations. If expo- and etch processes are performed repeatedly, or self- microprocessor, the Intel 4004. Over the following half cen- latest mass-produced chips—products of 14-nm technol- sure alignment is off by a distance of just ten or so atoms, aligned patterning, in which repeated deposition and etch tury, through repeated technological innovation, semicon- ogy—boast well over a billion transistors per chip. The gate the densely arranged circuit elements will be interconnected processes are performed after lithography. These technol- ductor performance has continued to improve, with steadily length on these chips is approximately 20 nm, and the inaccurately, leading to declines in processing precision. ogies are expected to see continued application in coming higher circuit density realizing improved performance, such width of the fins (the channels) is just 8 nm. Going forward, Furthermore, at high-volume manufacturing sites, noise technology nodes. In addition, technology known as self- as increased capacity, speed and power efficiency. each successive technology node will entail miniaturization that always has a certain probability of occurring is becoming aligned block (SAB), which increases tolerance for place- Figure 1 illustrates the evolution of logic devices since by a few nanometers, or the size of ten or so atoms. a more pronounced issue. The errors caused by such noise ment variance in lithography, is currently being developed. 2000. In early planar poly-gates, strained silicon technology Manufacturing such devices will require atomic-level control. might not be problematic when lithography and etch process- By taking advantage of differences in etch selectivity by was introduced to improve channel mobility. Later, high-k1/ 1 High-k: High dielectric constant film es are conducted just once. However, when lithography and material, this technology is expected to enable the process- metal gate technologies were introduced to reduce current etch processes are conducted multiple times on the same ing only of the desired materials without the need for leakage that arose due to miniaturization. To enhance pattern layer, these errors accumulate, leading to reduced yield. As improved performance from exposure equipment. fidelity, circuit design transitioned from 2D layouts to combi- Technological Barriers to miniaturization advances, these three challenges are expected To realize these patterning technologies, the further nations of simpler 1D layouts (Figure 2). As miniaturization to become even more serious. Solving them will be crucial to refinement of production technologies for each unit process continued beyond 45 nm, multiple patterning technologies Miniaturization advancing to the 5-nm technology node and beyond. is indispensable. These include atomic layer etch (ALE) and were developed to compensate for the limits of lithography atomic layer deposition (ALD), which control etching and resolution, and FinFET structures were adopted to reduce Miniaturization in semiconductor production is now facing deposition at the atomic level (Figure 4), as well as drying short-channel effects. Going forward, with the advent of new hurdles. The first of these is photolithography resolu- Breakthroughs in technologies to prevent pattern collapse caused by clean- 5-nm technology and beyond, logic devices are expected to tion, a challenge that has emerged in recent years. Until now, ing chemicals. In addition, the unit processes that give the evolve into nanowire structures. In memory devices, the use miniaturization has advanced by using shorter wavelength Production Technology best performance individually do not always achieve the of capacitors and transistors with 3D structures in DRAM light sources in exposure equipment to increase resolution. highest yields when combined. This means that integration have driven continued miniaturization, and the switch from Today, however, the shortest wavelength available for use To solve these challenges, a number of breakthrough technology, aimed at optimizing unit processes to one planar NAND flash memory to 3D NAND has sidestepped the in mass production is 193 nm, more than 20 times the width production technologies are beginning to emerge. Figure 1. The Evolution of Logic Device Transistor Structures Figure 2. The Evolution of Logic Device Circuit Design Figure 3. The Evolution of NAND Flash Memory Planar poly-gates Planar metal gates FinFET Nanowire (5 nm and beyond) 2D layout 1D layout (45 nm and beyond) (22 nm and beyond) Structure diagrams Planar NAND flash (down to 15 nm) One unit cell One unit cell (SEM image) (SEM image) Cross section (SEM image) 3D NAND flash One atom T. Ghani, et al., K. Mistry, et al., C. Auth, et al., R. Coquand et al., Illustrations of devices viewed from directly above IEDM 2003 IEDM 2007 VLSI tech. 2012 VLSI tech. 2013 SEM image source: Kelin J. Kuhn, IEDM 2007 Devices evolved through changes in transistor materials and structure. Miniaturization continued The method of increasing density changed Manufacturing requires atomic-level production technology. by changing to simpler, 1D layouts. from planar miniaturization to vertical stacking. TOKYO ELECTRON ANNUAL REPORT 2018 PAGE 10 Innovation Drives the Evolution of Semiconductors Innovation Drives the Evolution of Semiconductors Innovation Drives the Evolution of Semiconductors another, will only grow more important. Tokyo Electron In addition to pattering technologies, EUV, a new type of number of masks needed per layer, reducing placement excel in performing complex calculations on large volumes provides equipment for a wide range of processes. light source for lithographic exposure, is approaching com- error and thereby increasing yields (Figure 5). of information and are expected to be adopted in data Leveraging this strength, we are beginning to aggressively mercialization. In particular, the use of EUV in litho-etch Tokyo Electron is working with exposure equipment center servers and similar electronics. develop and offer integration technology solutions. processes (as explained above) is expected to reduce the suppliers, consortia and other partners to develop coater/ These new devices can only be commercialized through developers for EUV lithography. We report our progress the application of existing semiconductor production Figure 4: Atomic Layer Etch (ALE) and Atomic Layer Deposition (ALD) every year at SPIE Advanced Lithography, the world’s technologies. Tokyo Electron is focusing not just on ways largest lithography conference, as we strive toward the to continue miniaturization, but also on the technologies ALE ALD adoption of EUV in mass production in the semiconductor that will be required for continued evolution over the long A gas is adsorbed to the wafer surface, then the excess gas is A gas is adsorbed to the wafer surface, then the excess gas is purged and the adsorbed gas is reacted with another substance purged and the adsorbed gas is reacted with another substance industry. The combination of patterning technologies and term. In addition to our independent R&D initiatives, we to etch the exposed atomic layer of the wafer. This process is to deposit an atomic layer on the wafer. This process is repeat- EUV is now pushing miniaturization toward the 5-nm are beginning to build an ecosystem for collaboration with repeated as many times as necessary. ed as many times as necessary. technology node and beyond. consortia, academia and other equipment and material Purge suppliers around the world. By creating new production Surface modification technologies, Tokyo Electron will contribute to the contin- AICH pulse HO pulse a b ued evolution of semiconductors. Ligand Repeat Beyond Miniaturization Next cycle ALEt exposure 2 TS Böscke, et al., “Ferroelectricity in hafnium oxide thin films,” Applied
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