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EE241B : Advanced Digital Circuits • Sign up for Piazza If You Haven’T Already inst.eecs.berkeley.edu/~ee241b Announcements EE241B : Advanced Digital Circuits • Sign up for Piazza if you haven’t already Lecture 3 – Modern Technologies Borivoje Nikoliü ASML Ramps up EUV Scanners Production: 35 in 2020, up to 50 in 2021. ASML shipped 26 extreme ultraviolet lithography (EUVL) step-and-scan systems to its customers last year, and the company plans to increase shipments to around 35 in 2020. And the ramp-up won't stop there: as semiconductor fabs ramp up their own usage of EUV process technologies, they are going to need more leading-edge equipment, with ASML expecting to sell up to 50 EUVL scanners in 2021. AnandTech, January 23, 2020. EECS241B L03 TECHNOLOGY 1 EECS241B L02 TECHNOLOGY 2 Assigned Reading Outline • Scaling issues • R.H. Dennard et al, “Design of ion-implanted MOSFET's with very small physical dimensions” IEEE Journal of Solid-State Circuits, April 1974. • Technology scaling trends • Just the scaling principles • Features of modern technologies • C.G. Sodini, P.-K. Ko, J.L. Moll, "The effect of high fields on MOS device and circuit performance," IEEE • Lithography Trans. on Electron Devices, vol. 31, no. 10, pp. 1386 - 1393, Oct. 1984. • Process technologies • K.-Y. Toh, P.-K. Ko, R.G. Meyer, "An engineering model for short-channel MOS devices" IEEE Journal of Solid-State Circuits, vol. 23, no. 4, pp. 950-958, Aug. 1988. • T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, vol. 25, no. 2, pp. 584 - 594, April 1990. EECS241B L02 TECHNOLOGY 3 EECS241B L02 TECHNOLOGY 4 Technology Features • Lithography implications (this lecture) • Restrictions on design • Implications on design variability • FEOL features (next lecture) 1.C Features of Modern • Models Technologies EECS241B L02 TECHNOLOGY 5 EECS241B L02 TECHNOLOGY 6 Lithography – Key Points Step-and-Scan Lithography • Current lithography restricts features in design, affects variability • This is change with EUV (expected next year in volume) • But that ‘next year’ has been taking a while to arrive EECS241B L02 TECHNOLOGY 7 EECS241B L02 TECHNOLOGY 8 Lithography Scaling Sub-Wavelength Lithography • Light projected through a gap 10 10000 Nominal feature size scaling 193nm light 1 1000 Mask 365nm 248nm nm Pm 193nm Light Light 250nm intensity intensity 180nm 0.1 130nm 100 90nm 65nm 45nm 32nm 22nm EUV 13nm 0.01 10 1970 1980 1990 2000 2010 2020 EUV – Technology of the future (forever)? EECS241B L02 TECHNOLOGY 9 EECS241B L02 TECHNOLOGY 10 Sub-Wavelength Lithography Litho: How to Enhance Resolution? • Immersion • CD ~ half pitch O • Decrease O CD k • Off-axis illumination • Presently: 193 nm (ArF excimer laser) 1 NA • (Distant?) future: EUV • Optical proximity correction • Increase NA = nsinɲ • Maximum n is 1 in air • Phase-shifting masks • Presently: ~0.92-1.35 • Immersion • Double patterning • Result: Shrinking k1 O 193nm CD k 0.25 50 nm • Presently: 0.35 – 0.4 min 1 NA 0.92 • Theoretical limit: 0.25 22nm pitches beyond resolution limit EECS241B L02 TECHNOLOGY 11 EECS241B L02 TECHNOLOGY 12 Litho (1): Immersion Litho (2): Illumination • Project through a drop of liquid • Amplifies certain pitches/rotations at expense of others • n = 1.47 water O 193nm Regular Illumination CD k 0.25 35 nm min 1 NA 1.35 Many off-axis designs (OAI) Annular or Quadrupole / Quasar Dipole + IBM A.Kahng, ICCAD’03 EECS241B L02 TECHNOLOGY 13 EECS241B L02 TECHNOLOGY 14 Litho (3): Resolution Enhancement Litho (3): OPC J.Hartmann, ISSCC’07 EECS241B L02 TECHNOLOGY 15 EECS241B L02 TECHNOLOGY 16 Litho (3): OPC Inverse Lithograpphy Techniques • Optical Proximity Correction (OPC) modifies layout to compensate for • OPC vs. ILT process distortions • Add non-electrical structures to layout to control diffraction of light • Rule-based (past) or model-based OPC Fracture Design Mask A.Kahng, ICCAD’03 https://semiengineering.com/what-happened-to-inverse-lithography/ EECS241B L02 TECHNOLOGY 17 EECS241B L02 TECHNOLOGY 18 Extreme Ultraviolet Lithography Litho (4): Restricted Design Rules • Wavelength O = 13.5nm • Lower wafer throughput • Simpler design rules (single patterning) • Used on critical layers • First deployed by Samsung in 7nm node (Exynos 9825 SoC) • Also used by Intel in 7nm, TSMC in 5nm Also: note poly density rules J.Hartmann, ISSCC’07 EECS241B L02 TECHNOLOGY 19 Litho (5): Phase-Shift Masks Litho (6): Double Patterning • Double exposure double etch • Phase Shifting Masks (PSM) • Double exposure double etch • Creates interference fringes on the wafer ÆInterference • Pitch split, litho-etch-litho-etch (LELE) effects boost contrast ÆPhase Masks can make extremely small lines • Self-aligned methods • Self-aligned double patterning conventional mask phase shifting mask • Self-aligned quadruple patterning glass Chrome Phase shifter Electric field at mask Intensity at wafer A.Kahng, ICCAD’03 Double-Exposure Double-Etch 32nm Examples Starting layout Line + cut split Cut over line Single exposure Double exposure Result: IEDM’08 SRAM image from K. Mistry, IEDM’07 Pitch-Split Double Exposure Self-Aligned Double Patterning (SADP) Starting layout Split pattern Overlay With overlay misalignment • SADP: Double patterning – Also called litho-etch-litho-etch (LELE) Two litho-defined lines to form four fins • SAQP: Quadruple patterning Litho: Design Implications Litho: Current Options (Beyond 10nm) • Forbidden directions • Multiple patterning • Depends on illumination type • NA ~ 1.2-1.35 • Poly lines in other directions can exist but need to be thicker • EUV lithography • Forbidden pitches • O = 13.5nm • Nulls in the interference pattern • Multiple patterning • Forbidden shapes in PSM, multiple-patterning • Assist features • If a transistor doesn’t have a neighbor, let’s add a dummy Cost adder reduced with increased power/throughput of EUV A. Raley, SPIE’16 Some of the Process Features 1. Shallow-trench isolation 2. High-k/Metal-gate technology 3. Strained silicon 4. Thin-body devices (28nm, and beyond) 1.D Modern Bulk/finFET/FDSOI processes 5. Copper interconnects with low-k dielectrics EECS241B L02 TECHNOLOGY 29 1. Shallow Trench Isolation 2. Hi-k/Metal gate • Less space needed for isolation • Some impact on stress gate-oxide TiSi2 AlCu SiO2 Tungsten K. Mistry, IEDM’07 poly Replacement gate technology (Intel) p-well n-well SiO2 n+ p-epi p+ p+ S. Natarajan, IEDM’08 3. Strained Silicon Intel’s Strained Si Numbers PMOS High NMOS Performance gains: Stress Film 90 nm 65 nm SiGe SiGe NMOS PMOS NMOS PMOS P 20% 55% 35% 90% Compressive channel strain Tensile channel strain IDSAT 10% 30% 18% 50% 30% drive current increase 10% drive current increase in 90nm CMOS in 90nm CMOS IDLIN 10% 55% 18% 80% S. Thompson, VLSI’06 Tutorial Intel Strained Silicon 5. Thin-Body Devices • No strain • Strained Si • 28nm FDSOI • 22/14nm finFET VDD VDD M2 W2 ~ 2 M2 W2 = 1.6 In Out In Out M 1 W1 = 1 M1 W1 = 1 N. Planes, VLSI’2012 C. Auth, VLSI’2012 5. FinFETs 5. FDSOI • FinFET scaling • Track scaling 20122013 2014 2015 2016 2017 22/20nm 16/14nm 10nm 28FDSOI (STMicroelectronics) 28FD-SOI (Samsung) Intel, Intel, Intel, 22FDX (GLOBALFOUNDRIES) IEDM’12 VLSI’14 IEDM’17 12FDX (GLOBALFOUNDRIES) 18FDS (Samsung) • N-P spacing Garcia Bardon, IEDM’16 5. Interconnect Interconnect: CMP Cu interconnect: Dual damascene process Ta barrier layer to prevent Cu from diffusing into Si Mi Etch stop (SiN) Mi-1 • Metal density rules (20%-80%) • Slotting rules • Also: Antenna rules J. Hartmann, ISSCC’07 Next Lecture • Transistor models EECS241B L02 TECHNOLOGY 41.
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