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Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies

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Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies University of California Los Angeles Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering by Rani Abou Ghaida 2012 c Copyright by Rani Abou Ghaida 2012 Abstract of the Dissertation Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies by Rani Abou Ghaida Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 2012 Professor Puneet Gupta, Chair The semiconductor industry is likely to see several radical changes in the manufac- turing, device and interconnect technologies in the next few years and decades. One of the most favorable options of manufacturing technologies is multiple-patterning lithography. This novel technology has serious implications on design, however, and it will require an enabling design to see any adoption. This dissertation contributes to the design enablement of multiple-patterning technology. We propose a general methodology for the automated adaptation of layout to multiple-patterning masking the complexity in dealing with its manufac- turing constraints. We also study the impact of this technology on design and show the benefits of bringing the design perspective into making manufacturing-process decisions. Lastly, we propose a novel technique for DP that reduces cost and improve overlay/Critical-Dimension (CD) control in multiple-patterning. Many technology choices are presented to achieve scaling to every next node and early technology assessment, before the actual development of technologies, has be- come more necessary than ever as a means to ensure faster adoption and manageable technology/design development costs. Technology assessment is currently a highly unsystematic procedure that relies on small-scale experiments and manufacturing tests and much on speculations based on technologists/designers experience with previous technology generations. ii This dissertation also addresses the problem of increasing complexity in making technological decisions. It aims at the development of a computation infrastructure for the systematic and early assessment of technologies and their impact on circuit design. The infrastructure is the first of its kind and is expected to have a lasting impact on technology development. The infrastructure allows for true exploration of design and technology choices, thereby redirecting research and development ef- forts toward options that are more likely to eventually see adoption. Finally, the infrastructure is applied to evaluate multiple-patterning process decisions and study their implications on design. iii The dissertation of Rani Abou Ghaida is approved. Jingsheng Jason Cong Lei He Dejan Markovic Puneet Gupta, Committee Chair University of California, Los Angeles 2012 iv To Said, Nabila, Houssam, Rania, and Hikmat . v Table of Contents 1 Introduction ::::::::::::::::::::::::::::::::: 1 1.1 Scaling in the Sub-wavelength Lithography Regime . .2 1.1.1 Multiple-Patterning Lithography . .3 1.2 Design/Manufacturing Interactions . .7 1.2.1 Design Rules . .7 1.2.2 Design Enablement . .7 1.3 Problem Statement . .9 1.4 Objective and Scope of this Thesis . 12 I Design Enablement of Multiple-Patterning Technology 14 2 Layout Decomposition and Legalization for Multiple-Patterning Technology ::::::::::::::::::::::::::::::::::: 15 2.1 DP Coloring . 17 2.1.1 Prior Art in DP Coloring . 18 2.1.2 Overview of Our DP Coloring Approach . 20 2.1.3 Multiple Spacing-Rules Projection . 21 2.1.4 Coloring Objectives . 21 2.1.5 Implementation Details . 23 2.1.6 Stitches vs. Conflicts and Special Cases . 27 2.1.7 Coloring Results . 28 2.2 TP Coloring . 32 2.2.1 Prior Art in TP Coloring . 34 2.2.2 Overview of Our Approach . 35 vi 2.2.3 Description of the Proposed Methodology for TP Coloring . 36 2.2.4 Experimental Results . 39 2.3 Layout Legalization for MP . 45 2.3.1 Prior Art in DP Conflict-Removal . 45 2.3.2 Our Approach { Legalization with Minimum Layout Pertur- bation . 47 2.3.3 Layout Simplification for More Efficient DP Conflict Removal 50 2.3.4 DP-Compatible Design . 54 2.3.5 Experimental Setup and Results . 56 3 Overlay Impact for Design in Metal Double-Patterning ::::: 62 3.1 Electrical Impact of Within-Layer Overlay . 65 3.1.1 Overlay Modeling . 65 3.1.2 Capacitance Model . 66 3.1.3 Electrical Impact in Positive DP . 66 3.1.4 Electrical Impact in Negative DP . 68 3.2 Experimental Methodology and Results . 69 3.2.1 Experimental Setup . 69 3.2.2 Evaluation Methodology . 72 3.2.3 Results . 72 3.3 Observations and Implications for Design . 73 3.3.1 Results Analysis and Relative Importance of Overlay Sources . 73 3.3.2 Effects of Design Parameters . 75 3.3.3 Expected Worst-Case Overlay Impact in Critical Path . 77 3.3.4 Overlay Impact on Crosstalk Noise . 82 3.3.5 Estimation of Overlay Requirement . 83 vii 3.4 Exploring Processing Options . 84 4 Single-Mask Double-Patterning Lithography :::::::::::: 88 4.1 Shift-Trim DP Overview and Layout Restrictions . 91 4.1.1 Manufacturing Process . 91 4.1.2 STDP Challenges and Downsides . 93 4.1.3 Layout Restrictions at Poly-line Layer . 93 4.1.4 Layout Restrictions at Contacts Layer . 96 4.2 STDP Design Implementation . 98 4.2.1 Limitation on Pitch Relaxation of Double Patterning . 98 4.2.2 Poly-line STDP Standard-Cell Library and Mask Layout Gen- eration . 99 4.2.3 Poly-line Plus Contacts STDP Standard-Cell Library and Mask Layout Generation . 106 4.3 STDP Benefits . 110 4.3.1 Overlay and Throughput Benefits . 110 4.3.2 Alleviating CD Bimodality Problem . 111 4.3.3 Comparison with Popular Double-Patterning Technologies . 112 II Design-Centric Assessment of Technology 115 5 A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies :::::::::::::::::::: 116 5.1 Area Estimation . 120 5.1.1 Layout Topology Generation . 120 5.1.2 Tweaking Pairing . 124 5.1.3 Routing Estimation . 125 viii 5.1.4 Congestion Estimation . 128 5.1.5 Area Increase Due to Congestion . 131 5.1.6 Runtime and Validation of Area Estimation . 134 5.2 Manufacturability Evaluation . 135 5.3 Variability Evaluation . 137 5.4 Experimental Setup and Results . 140 5.4.1 Testing Setup . 140 5.4.2 Evaluation of Poly-Patterning Restrictions . 142 5.4.3 Evaluation of Layout Styles . 143 5.4.4 Assessment of Technologies and Wiring Schemes . 146 5.4.5 DR Comparison of Different Processes . 152 5.4.6 DR Exploration . 152 6 Exploration of Design Rules for Multiple-Patterning Technologies156 6.1 A Methodology for the Early Exploration of Design Rules for Multiple- Patterning Technologies . 157 6.1.1 Probabilistic Layout and Congestion Estimation . 159 6.1.2 DP Conflict Prediction Using Machine Learning . 166 6.1.3 DP Design-Rule Exploration . 171 6.2 A Methodology for Exploring the Interaction Between Design Rules and Overlay Control . 176 6.2.1 Design Rules and Overlay Interaction . 178 6.2.2 Overlay and Yield Modeling . 179 6.2.3 Evaluation of Rules Impact on Design . 180 6.2.4 Experimental Results . 181 7 Conclusions and Future Research ::::::::::::::::::: 187 ix 7.1 Research Contributions . 187 7.2 Future Research . 189 References :::::::::::::::::::::::::::::::::::: 192 x List of Figures 1.1 Abrupt poly line-ends formed using the trim exposure of a DP process at 45nm technology node (reprinted from [ACC08]). .4 1.2 Example of pitch-split DP, where dark-colored features were formed with one exposure and light-colored features were formed with a sec- ond exposure (reprinted from [Mac08]). .4 1.3 Process flows for the different approaches of double-patterning (reprinted from [ITRa]). .5 1.4 Examples of a LELE/LLE forbidden pattern (a) and a SADP for- bidden pattern (b). Smin denotes the minimum spacing of single- patterning and mandrel denotes layout features that do not appear on the mask of the first exposure. .6 1.5 Example of a regular fabric, which implements the function !(AB+C) (reprinted from [LPH09]). .8 1.6 Possible technology choices for the scaling to future technology gen- erations. 10 2.1 The flow for our proposed method to achieve MP-enabled layout design. 17 2.2 Example of a layout with odd cycle in its conflict graph (a) that was broken by introducing a stitch (b). 18 2.3 Illustration of the drawbacks of segmenting the layout into rectangles, which is performed in prior art of DP coloring and conflict removal. 19 2.4 DR-dependent projection to identify violating parts and stitch loca- tions. Violating parts are the blue features and non-violating parts are the clear features. 20 xi 2.5 Odd cycle coloring can affect the efficiency of conflict removal. In (a), the conflict is on M1 between shapes A and B and can only be fixed if the gates are spaced apart and area is increased; in (b), the conflict is on M1 between shapes B and C and can be fixed by moving C in the direction of the arrow without increasing area. 22 2.6 An illustrating example showing each step of the coloring process for an isolated region of the layout. 23 2.7 O(n) coloring procedure with greedy algorithm for color-flipping2... 25 2.8 Case of most suboptimal solution for greedy-based flipping. 26 2.9 Example showing two coloring solutions that our method may give for the same layout (rare case with all diagonal violations) depending on the propagation order of the coloring: (a) with two DP violations and (b) with a single DP violation. 28 2.10 Comparison of the number of same-color spacing violations when stitches are forbidden and when they are allowed. 31 2.11 Region of forbidden stitching at corner, which will be merged with the overlapping violating part on the left to prevent stitching at the corner.
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