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Paper Dark Current Characterization of Low-Noise CMOS Global Shutter Pixels Using Pinned Storage Diodes

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Paper Dark Current Characterization of Low-Noise CMOS Global Shutter Pixels Using Pinned Storage Diodes ITE Trans. on MTA Vol. 2, No. 2, pp. 108-113 (2014) Copyright © 2014 by ITE Transactions on Media Technology and Applications (MTA) Paper Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes † † † Keita Yasutomi (member) , Taishi Takasawa , Shoji Kawahito (fellow) Abstract This paper describes dark current characterization of two-stage charge transfer pixels, which enable a global shuttering and kTC noise canceling. The proposed pixel uses pinned diode structures for the photodiode (PD) as well as the storage diode (SD), thereby a very low dark current is expected. In this paper, effects of negative gate biasing and temperature dependency are discussed with device simulations and measurement results. The measured dark current of the PD and SD with the negative gate bias results in 19.5 e-/s and 7.3 e-/s (totally 26.8 e-/s) at ambient temperature of 25oC (the chip temperature is approximately 30◦C). This value is much smaller than that of conventional global shutter pixels, showing the effectiveness of use of the pinned storage diode. Key words: CMOS Image Sensor, dark current. global shutter, two-stage charge transfer, kTC noise free. measured dark current is still higher than rolling shut- 1. Introduction ter CISs. Recently, true-correlated double sampling (CDS) This paper describes dark current characterization global shutter (GS) pixels1)−4) have been developed, of the two-stage charge transfer pixels using pinned and the noise level of GS CMOS image sensors (CISs) storage diodes under negative gate bias conditions for has been improved to a few electrons. Taking advan- charge transfer gates. The negative gate biasing7)−10) tage of such a low noise performance requires low dark is a well known method to suppress dark current due to current less than 100e-/s in order to keep the noise Shockley-Read-Hall (SRH) surface generation process. floor from the shot noise of dark current5). However, In this paper, temperature dependence of the photodi- no CMOS GS pixels which can satisfy low dark current ode (PD) and storage diode (SD) dark current under characteristic have been reported. negative gate biasing is also described. A five-transistor (5T)-GS pixel1) with a correlated The remainder of the present paper is organized as quadruple sampling (CQS) technique offers kTC noise follows. In Section 2, the pixel structure and operation canceling while suppressing 1/f noise at the cost of the are shown. Section 3 describes measurement methods frame rate to be half. The pixel, however, suffers from and conditions for dark current characterization. Sec- high dark current at a charge storage node due to the tion 4 presents the experimental results and discussion use of a floating diffusion as an analog memory. In about effects of temperature dependency and negative the eight transistor (8T) pixel2), the kTC noise is can- gate biasing. Conclusions are presented in Section 5. celled by a CDS with in-pixel sample-and-hold capaci- 2. Pixel implementation tors. Since the sampling capacitors should be small to maintain a high fill factor, causing relatively high leak- Figs.1 and 2 show the proposed pixel structure, the age and the thermal noise induced by the sampling ca- potential profile and the layout. Compared with the pacitors. The two-stage charge transfer pixels3)4) using previous design for the dual global shutter3)4) , the pixel a pinned storage diode have demonstrated its low-noise is simplified for a single global shutter and consists of six performance and a high shutter efficiency. Though the transistors and two pinned diodes: a PD and SD. The pixel structure is suitable for reduced dark current, the PD has a role of photoelectron generation and storage, while the SD has a role of charge storage only. A part of this paper was reported in International Image Sensor Work- The pixel introduces a dual doping technique and shop 2011, June 8-11th, 2011. Received September 3, 2013; Revised November 22, 2013; Accepted shielding structure to meet a high charge transfer ef- December 10, 2013 ficiency and shutter efficiency. By means of the dual † Research Institute of Electronics, Shizuoka University (Hamamatsu, Japan) doping technique, the PD and SD have different con- 108 Paper » Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes centrations of n-type dopant: n1 and n2,andthepo- tential difference between the PD and SD are built to RFD(i) MR be higher charge transfer efficiency (CTE). Stepwise po- M V SF tential created by p under the GS gate also enhances DD RS(i) 1 RPD GS TX(i) PD SD FD the CTE. It has an another p-type doping (p2) beneath n+ p+ p+ n+ M the n2 layer for charge shielding. This shielding layer n(n2) SEL p(p2) improves the shutter efficiency to be 99.7% at incident p(p1) n(n1) p-well p-well light wavelength of 550nm4). The dominant source of p-sub shutter leakage is carriers which are generated at deep OFF OFF OFF substrate and diffuse into the SD. Therefore, the shutter efficiency can be improved with higher concentration of 11) p2 doping than that of the p-type substrate . ON ON ON Fig.3 shows the timing diagram of the pixel. For V every pixel, a signal charge accumulated in the PD is Fig. 1 Pixel structure and potential profile. transferred to the SD with the GS gate. The SD stores the charge until the pixel row is selected to be read. The signal charge is transferred to a floating diffusion p1 (FD), and is read out in the same manner as that of MR, MSF, MSEL rolling-shutter-based four transistor (4T) pixel, i.e., a Transistors true CDS is accomplished. Since the kTC noise is can- Active celed, the noise level is as low as that of rolling shutter FD B' p2 CMOS imagers. Generally, there are three components in dark cur- PD TX rent: the generation current generated in depletion B layer (depletion dark current), the generation current Rst. Drain Rst. SD at Si-surface (surface dark current), and the diffusion current generated in the bulk neutral region (diffusion A A' dark current). In the proposed pixel, both the PD and GS SD employ a pinned-diode structure, which can sup- RPD press surface dark current. Fig. 2 Pixel layout. In pinned diode structures, it is well known that edges of the transfer gates and shallow trench isolation (STI) 20% and 14%, respectively. The signal from a pixel is become the primary source of dark current9)12)13) .The digitized by a 13-bit column cyclic ADC, and then, the edges of PD are covered by p1 layer, which helps to digital code is read out. attract holes there. Also in the SD, STI edges are cov- The dark currents are measured by the gradient of the ered by p1 layer to reduce the depletion dark current plot of the dark signal versus integration time of the PD as shown in Fig.2. While, the channels both under the and SD. As shown in Fig.3, only the integration time GS gate (along A-A’) and under TX gate (along B-B’) of the PD, Ta,P D, is varied from approximately 15s to is not covered by p1 layer, causing large depletion dark 30s to measure the PD dark current. Similarly, only current. This depletion dark current can be suppressed the integration time of the SD, Ta,SD, is varied for the by applying the negative gate bias technique discussed measurements of SD dark current. These measurement in Section 4. methods allow us to measure the PD and SD dark cur- rents separately. Although the exact integration time 3. Measurements of SD dark signal is different from row to row as shown A test chip with the proposed pixels is fabricated in a in Fig.3, the time difference (e.g. ΔTa,SD(1 − 2)) is 0.18um CIS technology shown as Fig.4.Inthispaper, much smaller than the common integration time, Ta,SD, measurement results of 3 (H)×480 (V), totally 1440 pix- thereby making it negligible. els are described. The pixel size is 7.5 × 7.5 μm2,and the fill factors of the PD and SD area are approximately 109 ITE Trans. on MTA Vol. 2, No. 2 (2014) Integration time, Ta,PD 30 Integration time, Ta,SD GS 25 VTXL:Changed (VGSL:-1.0V) RPD 20 RS(1) 15 RFD(1) TX(1) 10 RS(2) RFD(2) 5 VGSL:Changed (VTXL:-1.0V) TX(2) Average dark current (e-/s) Average 0 ΔTa,SD(1-2) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 RS(N) Gate voltage RFD(N) TX(N) Fig. 5 SD dark current for various VGSL and VTXL voltages. Frame period Fig. 3 Timing diagram for Measurements of the PD and SD dark current. the VTXL become negative, the surface beneath the TX gate become gradually a pinning condition, resulting in the SD dark current to be small. The surface potential rapidly decrease up to the VTXL of -0.6V. When VTXL is less than -0.6V, the surface is sufficiently pinned, and a region in which the depletion region touch the surface Pixel TEG Pixel V.Scanner at the edge of TX is slightly reduced. SF load Fig.7 shows the simulation results of potential dis- w/ Cap. tribusion along A-A’. Similar to the negative bias on TX gate, as the VGSL become more negative, the de- pletion region of SD become shallow at the edge of GS 13Bit Column ADC Cyclic gate.
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