Paper Dark Current Characterization of Low-Noise CMOS Global Shutter Pixels Using Pinned Storage Diodes

Paper Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes

† † † Keita Yasutomi (member) , Taishi Takasawa , Shoji Kawahito (fellow)

Abstract This paper describes dark current characterization of two-stage charge transfer pixels, which enable a global shuttering and kTC noise canceling. The proposed pixel uses pinned diode structures for the photodiode (PD) as well as the storage diode (SD), thereby a very low dark current is expected. In this paper, eﬀects of negative gate biasing and temperature dependency are discussed with device simulations and measurement results. The measured dark current of the PD and SD with the negative gate bias results in 19.5 e-/s and 7.3 e-/s (totally 26.8 e-/s) at ambient temperature of 25oC (the chip temperature is approximately 30◦C). This value is much smaller than that of conventional global shutter pixels, showing the eﬀectiveness of use of the pinned storage diode.

Key words: CMOS Image Sensor, dark current. global shutter, two-stage charge transfer, kTC noise free.

measured dark current is still higher than rolling shut- 1. Introduction ter CISs. Recently, true-correlated double sampling (CDS) This paper describes dark current characterization global shutter (GS) pixels1)−4) have been developed, of the two-stage charge transfer pixels using pinned and the noise level of GS CMOS image sensors (CISs) storage diodes under negative gate bias conditions for has been improved to a few electrons. Taking advan- charge transfer gates. The negative gate biasing7)−10) tage of such a low noise performance requires low dark is a well known method to suppress dark current due to current less than 100e-/s in order to keep the noise Shockley-Read-Hall (SRH) surface generation process. floor from the shot noise of dark current5). However, In this paper, temperature dependence of the photodi- no CMOS GS pixels which can satisfy low dark current ode (PD) and storage diode (SD) dark current under characteristic have been reported. negative gate biasing is also described. A five-transistor (5T)-GS pixel1) with a correlated The remainder of the present paper is organized as quadruple sampling (CQS) technique offers kTC noise follows. In Section 2, the pixel structure and operation canceling while suppressing 1/f noise at the cost of the are shown. Section 3 describes measurement methods frame rate to be half. The pixel, however, suffers from and conditions for dark current characterization. Sec- high dark current at a charge storage node due to the tion 4 presents the experimental results and discussion use of a floating diffusion as an analog memory. In about effects of temperature dependency and negative the eight transistor (8T) pixel2), the kTC noise is can- gate biasing. Conclusions are presented in Section 5. celled by a CDS with in-pixel sample-and-hold capaci- 2. Pixel implementation tors. Since the sampling capacitors should be small to maintain a high fill factor, causing relatively high leak- Figs.1 and 2 show the proposed pixel structure, the age and the thermal noise induced by the sampling ca- potential profile and the layout. Compared with the pacitors. The two-stage charge transfer pixels3)4) using previous design for the dual global shutter3)4) , the pixel a pinned storage diode have demonstrated its low-noise is simplified for a single global shutter and consists of six performance and a high shutter efficiency. Though the transistors and two pinned diodes: a PD and SD. The pixel structure is suitable for reduced dark current, the PD has a role of photoelectron generation and storage, while the SD has a role of charge storage only. A part of this paper was reported in International Image Sensor Work- The pixel introduces a dual doping technique and shop 2011, June 8-11th, 2011. Received September 3, 2013; Revised November 22, 2013; Accepted shielding structure to meet a high charge transfer ef- December 10, 2013 ficiency and shutter efficiency. By means of the dual † Research Institute of Electronics, Shizuoka University (Hamamatsu, Japan) doping technique, the PD and SD have different con-

108 Paper » Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes

centrations of n-type dopant: n1 and n2,andthepo- tential difference between the PD and SD are built to RFD(i) MR be higher charge transfer efficiency (CTE). Stepwise po- M V SF tential created by p under the GS gate also enhances DD RS(i) 1 RPD GS TX(i) PD SD FD the CTE. It has an another p-type doping (p2) beneath n+ p+ p+ n+ M the n2 layer for charge shielding. This shielding layer n(n2) SEL p(p2) improves the shutter efficiency to be 99.7% at incident p(p1) n(n1) p-well p-well light wavelength of 550nm4). The dominant source of p-sub shutter leakage is carriers which are generated at deep OFF OFF OFF substrate and diffuse into the SD. Therefore, the shutter efficiency can be improved with higher concentration of 11) p2 doping than that of the p-type substrate . ON ON ON Fig.3 shows the timing diagram of the pixel. For V every pixel, a signal charge accumulated in the PD is Fig. 1 Pixel structure and potential profile. transferred to the SD with the GS gate. The SD stores the charge until the pixel row is selected to be read. The signal charge is transferred to a floating diffusion p1 (FD), and is read out in the same manner as that of MR, MSF, MSEL rolling-shutter-based four transistor (4T) pixel, i.e., a Transistors true CDS is accomplished. Since the kTC noise is can- Active celed, the noise level is as low as that of rolling shutter FD B' p2 CMOS imagers. Generally, there are three components in dark cur- PD TX rent: the generation current generated in depletion B layer (depletion dark current), the generation current

Rst. Drain Rst. SD at Si-surface (surface dark current), and the diﬀusion current generated in the bulk neutral region (diﬀusion A A' dark current). In the proposed pixel, both the PD and GS SD employ a pinned-diode structure, which can sup- RPD press surface dark current. Fig. 2 Pixel layout. In pinned diode structures, it is well known that edges of the transfer gates and shallow trench isolation (STI) 20% and 14%, respectively. The signal from a pixel is become the primary source of dark current9)12)13) .The digitized by a 13-bit column cyclic ADC, and then, the edges of PD are covered by p1 layer, which helps to digital code is read out. attract holes there. Also in the SD, STI edges are cov- The dark currents are measured by the gradient of the ered by p1 layer to reduce the depletion dark current plot of the dark signal versus integration time of the PD as shown in Fig.2. While, the channels both under the and SD. As shown in Fig.3, only the integration time

GS gate (along A-A’) and under TX gate (along B-B’) of the PD, Ta,P D, is varied from approximately 15s to is not covered by p1 layer, causing large depletion dark 30s to measure the PD dark current. Similarly, only current. This depletion dark current can be suppressed the integration time of the SD, Ta,SD, is varied for the by applying the negative gate bias technique discussed measurements of SD dark current. These measurement in Section 4. methods allow us to measure the PD and SD dark currents separately. Although the exact integration time 3. Measurements of SD dark signal is diﬀerent from row to row as shown

A test chip with the proposed pixels is fabricated in a in Fig.3, the time diﬀerence (e.g. ΔTa,SD(1 − 2)) is

0.18um CIS technology shown as Fig.4.Inthispaper, much smaller than the common integration time, Ta,SD, measurement results of 3 (H)×480 (V), totally 1440 pix- thereby making it negligible. els are described. The pixel size is 7.5 × 7.5 μm2,and the ﬁll factors of the PD and SD area are approximately

109 ITE Trans. on MTA Vol. 2, No. 2 (2014)

Integration time, Ta,PD 30 Integration time, Ta,SD GS 25 VTXL:Changed (VGSL:-1.0V) RPD 20 RS(1) 15 RFD(1) TX(1) 10 RS(2) RFD(2) 5 VGSL:Changed (VTXL:-1.0V) TX(2) Average dark current (e-/s) Average 0 ΔTa,SD(1-2) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 RS(N) Gate voltage RFD(N)

TX(N) Fig. 5 SD dark current for various VGSL and VTXL voltages. Frame period

Fig. 3 Timing diagram for Measurements of the PD and SD dark current. the VTXL become negative, the surface beneath the TX gate become gradually a pinning condition, resulting in the SD dark current to be small. The surface potential

rapidly decrease up to the VTXL of -0.6V. When VTXL is less than -0.6V, the surface is suﬃciently pinned, and a region in which the depletion region touch the surface Pixel TEG Pixel V.Scanner at the edge of TX is slightly reduced. SF load Fig.7 shows the simulation results of potential dis- w/ Cap. tribusion along A-A’. Similar to the negative bias on

TX gate, as the VGSL become more negative, the depletion region of SD become shallow at the edge of GS

13Bit Column ADC Cyclic gate. As the surface potential beneath the GS gate is

Timing Gen. Register negative, the region is ﬁlled with holes, reducing the SD Fig. 4 Chip photograph. dark current. As shown in Fig.5, the dark current re- duction eﬀect of negative gate bias on GS gate is smaller 4. Results and Discussion than that of the TX gate. This is because the region

without the p1 layer under the GS gate is about half of 4. 1 Effects of negative gate biases that under the TX gate. Fig.5 shows the measured SD dark current as a func- The cumulative probabilities of the SD dark cur- tion of VGSL or VTXL where, VGSL and VTXL are low rent at various biases of VTXL and VGSL are shown levels of GS and TX gate pulses, respectively. In the in Figs.8-9. The negative gate bias effectively reduces measurements, either V or V is varid from 0V to GSL TXL the number of ”hot” pixels. For instance, in Fig.8, the -1.0V in order to measure the effect of the negative gate number of pixels which have dark current of over 200e- biasing on the SD dark current. The ambient tempera- /s is 2% of entire pixels at VTXL=0V, and it is reduced ture is 25◦C, and the chip temperature is approximately to be approximately 0.3% at VTXL=-1.0V. Similarly, in 30◦C. As shown in Fig.5, the negative gate bias of the Fig.9, the number of pixels with the SD dark current of TX gate effectively suppresses the SD dark current, and over 200e-/s at VGSL=-1.0V is reduced to half of that the dark current with VTXL = -1.0V is measured to 1/3 at VGSL=0V. of that of V =0V. TXL Figs.10 and 11 show the measured PD dark current Fig.6(a) shows the simulation results of potential as a function of VGSL and the cumulative probability, distribusion along B-B’ in Fig.2. In Fig.6(b), magni- respectively. The negative gate bias of the GS gate has fied views at various V are shown. At the V of TXL TXL no significant effect to the PD dark current. As shown 0V, the depletion region is extended to beneath the TX in Fig.7, the surface potential at the PD-side edge of gate, resulting in the SD dark current to be large. As GS gate is negative even at VGSL= 0V. Therefore the

110 Paper » Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes

TX gate TX gate p+ p+ p+ GS gate p+ p+ GS gate p+ n+ n+ n2 n2 n n n n p2 p2 1 2 1 2 Magnified area p1 p2 p1 p2

TXL: 0V TXL: -1.0V (a) Magnified area Si surface GSL: 0V GSL: -1.0V TX gate TX gate TX gate Si surface (a)

GS gate GS gate TXL: 0V TXL: -0.2V TXL: -0.4V

TX gate TX gate TX gate

GSL: 0V GSL: -0.2V

GS gate GS gate

TXL: -0.6 V TXL: -0.8V TXL: -1.0V (b)

Fig. 6 Potential distribution under the TX gate (along GSL: -0.4V GSL: -0.6V B-B’). (a) overview (b) magnified view. Red line shows a contour line of 0V. GS gate GS gate p1 layer creating the stepwise-potential under GS gates helps to attract a hole accumulation at Si-surface, and the surface dark current is suppressed sufficiently. GSL: -0.8V GSL: -1.0V The large negative gate bias leads to the increase of (b) another dark current component due to Gate-Induced- Fig. 7 Potential distribution under the GS gate (along A-A’). (a) overview (b) magnified view. Red line Leak (GIL) Trap Assisted Tunneling (TAT) process shows a contour line of 0V. 10), which appear in a region with large electric field.

Fig.10 and Fig.11, however, do not show signiﬁcant 0 10 V : 0.0V increase in the PD dark current for VGSL of up to - TXL VTXL: -0.5V 1.0V. This is because the potential proﬁle at PD-side VTXL: -1.0V beneath the GS gate is almost unchanged in the range -1 of -0.4V to -1.0V as shown in Fig.7. Therefore, the PD 10 dark current generated from GIL-TAT process was not observed in this sensor. -2 4. 2 Temperature dependency 10

Temperature dependency of dark current gives its ac- Probability Cumulative tivation energies, which are useful to clarify their phys- ical reason of the dark current generation. The acti- -3 10 vation energy is found from the Arrhenius plot14) ex- 0 50 100 150 200 250 300 Dark current (e- /s) pressed by Fig. 8 SD dark current distribution for various VTXL −E voltages. D = De T 3 exp a,diff 0,diff kT −Ea,dep +De T 3/2 exp (1) solute temperature. Ea,diff and Ea,gen stand for acti- 0,dep kT vation energy of diffusion and depletion dark current, where De0,diff and De0,gen denote pre-factors in e-/s of respectively. diffusion and depletion dark current, respectively. k and Fig.12 shows the temperature dependence of PD and T , respectively, represent Boltzmann coefficient and ab-

111 ITE Trans. on MTA Vol. 2, No. 2 (2014)

0 10 VGSL: 0.0V 5 VGSL: -0.5V 10 VGSL: -1.0V PD 4 10 E =1.12eV PD -1 SD a 10 SD 103

102 -2 E =1.12eV 10 a 101 Cumulative Probability Cumulative 100 Ea=0.56eV

-3 dark current (e-/s) Average 10 -1 0 50 100 150 200 250 300 10 Dark current (e-/s) 2.7 2.9 3.1 3.3 3.5 3.7 1000/T (1/K) Fig. 9 SD dark current distribution for various VGSL voltages.

Fig. 12 Temperature dependence of PD and SD dark currents (VGSL : −1.0V , VTXL : −1.0V , 30 VRP DL :0.5V ). 25 20 gap energy of Si, Eg. Therefore, the diﬀusion current is dominant in the PD dark current. On the other hand, 15 the dominant sources of SD dark current are diﬀerent 10 at operating temperatures. At low temperatures below 25◦C, the activation energy of SD dark current is E /2, 5 g which indicates that the depletion dark current is dom-

Average dark current (e-/s) Average 0 inant. At high temperatures over 50◦C, the activation -1.0 -0.8 -0.6 -0.4 -0.2 0.0 Gate voltage energy equals to Eg. Therefore the diﬀusion dark current of the SD is ten times smaller than that of the PD Fig. 10 PD dark current as a function of VGSL. by the use of shielding structure. As shown in Figs.5 and 12, the depletion current of SD is larger than that of PD even when the negative gate biasing is applied. The residual depletion current 0 10 of SD may be due to imperfect hole accumulation at VGSL: 0.0V VGSL: -0.5V the surface of pinned diode structure and transfer gates, V : -1.0V GSL which can be reduced by increasing doping concentra-

-1 10 tion of the pinned layer (p+) and minimizing area of the charge-transfer channel under transfer gates.

5. Conclusions -2 10 In this paper, the dark current characteristics of the Cumulative Probability two-stage charge transfer global shutter pixel are presented. By means of the negative bias technique, total -3 10 dark current is reduced to 26.8 e-/s (PD:19.5 e-/s, SD: 0 50 100 150 200 250 300 Dark current (e- /s) 7.3 e-/s) at ambient temperature of 25◦C(the chip tem- ◦ Fig. 11 PD dark current distributions for various VGSL perature is approximately 30 C), which is much smaller voltages. than that of other global shutter pixels. From the Arrhenius plot, the diﬀusion dark current SD dark currents. In this measurement, both VGSL and of the SD is reduced to be ten times smaller than that VTXL are set to -1.0V. The activation energy of PD of the PD, showing an advantage of the proposed pixel dark current is 1.12eV, which is the same as the band-

112 Paper » Dark Current Characterization of Low-noise CMOS Global Shutter Pixels Using Pinned Storage Diodes for reduced dark current. In the present structure, the Keita Yasutomi received the Ph.D. degree duffusion current in the PD is dominant. Therefore, from Shizuoka University, Hamamatsu, Japan, in 2011. He is currently an Assistant Professor with the further reduced dark current can be achieved by the Research Institute of Electronics, Shizuoka Uni- versity. He is a member of the ITE, IEICE, and using other structures such as an n-substrate and thin IEEE. His research interests include time-resolved epi substrate. CMOS image sensors and low-noise imagers. Taishi Takasawa received the B.S. degree from Tokai University, Kanagawa, Japan, in 2003. References In 2009, he joined Shizuoka University, Hama- matsu, Japan, where he is engaged in the design 1)BFowler,C.Liu,S.Mims,J.Balicki,W.Li,H.Do,J.Appel- of the digital circuit and the Verilog language. baum, P. Vu, ”A 5.5Mpixel 100 frames/sec wide dynamic range low noise CMOS image sensor for scientific applications” in Proc. of SPIE-IS&T, pp. 753607-1-753607-7-12 (Feb. 2010) Shoji Kawahito received the Ph.D. degree 2) X. Wang, J. Bogaerts, G. Vanhorebeek, K. Ruythoren, B. Ceule- from Tohoku University, Sendai, Japan, in 1988. He mans, G. Lepage, P. Willems, G. Meynants, “A 2.2M CMOS Im- is presently a Professor with the Research Institute age Sensor for High Speed Machine Vision Application” in Proc. of Electronics, Shizuoka University and the CTO of SPIE-IS&T, 7536, pp. 75360M-1-75360M-7 (Jan. 2010) of BrookmanTechnology Inc. He is a Fellow of the 3) K. Yasutomi, S. Itoh, S. Kawahito: “A 2.7e- Temporal Noise IEEE and ITE. His research interests are in analog 99.7% Shutter Efficiency 92dB Dynamic Range CMOS Image circuits and pixel architecture designs for CMOS Sensor with Dual Global Shutter Pixels” Dig. Tech. Papers, IEEE imagers. ISSCC, pp.398-399 (Feb. 2010) 4) K. Yasutomi, S. Itoh, S. Kawahito: “A Two-Stage Charge Trans- fer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode” IEEE Trans. Electron Devices, 58, 3, pp.740-747 (Mar. 2011) 5) K. Mizobuchi, S. Adachi, J. Tejada, H. Oshikubo, N. Akahane, S. Sugawa: “A Very Low Dark Current Temperature-Resistant, Wide Dynamic Range, Complementary Metal Oxide Semicon- ductor Image Sensor” Jpn. J. Appl. Phys., 47, 7 (Jul. 2007) 6) N. Bock, A. Krymski, et al.: “A Wide-VGA CMOS Image Sen- sor with Global Shutter and Extended Dynamic Range” in Proc. of 2005 IEEE Workshop on CCDs and Advanced Image Sensors, pp.222-225 (Jun. 2005) 7) H. Han, H. Park, P. Altice, W. Choi, Y. Lim, S. Lee, S. Kang, J. kim, S. Yoon, and J. Hynecek: “Evaluation of a Small Nega- tive Transfer Gate Bias on the Performance of 4T CMOS Image Sensor Pixels” in Proc. of 2007 International Image Sensor Work- shop, pp.238-240 (Jun. 2007) 8) B. Mheen, Y.J. Song, and A.J.P. Theuwissen: “Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current” IEEE Electron De- vice Lett., 29, 4, pp.347-349 (Apr. 2008) 9) T. Watanabe, J.H. Park, S. Aoyama, K. Isobe, S. Kawahito: “Ef- fects of Negative-Bias Operation and Optical Stress on Dark Cur- rent in CMOS Image Sensors” IEEE Trans. Electron Devices, 50, 1, pp.1512-1518 (Jun. 2010) 10) H. Yamashita, M. Maeda, S. Furuya, T. Yagami: “Analysis of Dark Current in 4-Transistor CMOS Imager Pixel with Negative Transfer-gate bias Operation” in Proc. Int. Image Sensor Work- shop (Jun. 2009) 11) T. Kumesawa et al.: “High-Resolution CCD Image Sensors with Reduced Smear” IEEE Trans. Electron Devices, ED-32, 8, pp.1451-1456 (Aug. 1985) 12) B. Pain, T. Cunningham, B. Hancock, C. Wrigley, and C. Sun: “Excess noise and dark current mechanisms in CMOS imagers” in Proc. of 2005 IEEE Workshop CCDs & AISs, pp. 145-148 (2005). 13) Y. Kunimi and B. Pain: “Consideration of dark current generation at the transfer channel region in the solid state image sensor” in Proc. Int. Image Sensor Workshop 2007, pp. 66-69 (2007) 14) R. Widenhorn, M. Blouke, A. Weber, A. Rest, E. Bodegom: “Temperature dependence of dark current in a CCD” in Proc. of 2003 IEEE Workshop on CCDs&AIS (May 2003)

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