ChapterChapter 88 BasicBasic ProcessingProcessing UnitUnit

Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline ¾ Fundamental Concepts ¾ Hardwired Control ¾ Microprogrammed Control

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 2 Content Coverage

Main Memory System

Address Data/Instruction

Central Processing Unit (CPU)

Operational Registers Arithmetic Instruction and Cache Logic Unit Sets memory Program Counter

Control Unit

Input/Output System

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 3 Instruction Execution

¾ To execute an instruction, the processor has to perform the following three steps: ‹ Step 1: fetch the contents of the memory location pointed by the PC. The contents of this location are interpreted as an instruction to be executed. Hence, they are loaded into the IR. Symbolically, this can be written as IRÅ[[PC]] ‹ Step 2: assuming that the memory is byte addressable, increment the contents of the PC by 4, that is, PCÅ[PC]+4 ‹ Step 3: carry out the actions specified by the instruction in the IR ¾ Step 1 and Step 2Æfetch phase ¾ Step 3Ædecode phase, execution phase, and/or write phase

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 4 Single-Bus Organization of the Datapath

Control signals PC Address lines Instruction MAR decoder and Memory bus control logic Data MDR lines Y IR Constant 4 R0 Select

AB ALU control ALU R(n-1) lines Carry-in TEMP Z

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 5 Instruction Execution

¾ An instruction can be executed by performing one or more of the following operations in some specified sequence ‹ Transfer a word of data from one processor register to another or to the ALU ‹ Perform an arithmetic or a logic operation and store the result in a processor register ‹ Fetch the contents of a given memory location and load them into a processor register ‹ Store a word of data from a processor register into a given memory location

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 6 Register Transfers

Riin

Ri Rjout

1 Riout Yin Rj Y Constant 4 Rjin 1 Select

AB ALU

Zin

Z Zout

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 7 Input and Output Gating for 1-bit Register

Bus

0 D D 1

Riout

Riin

Clock

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 8 Arithmetic Operation

R1 Add R3, R1, R2 in

R1 R2out 1

1 R1out 1 Yin R2 Y Constant 4 R2in 1 Select 01 R3out

AB ALU R3

1 Zin

Z R3in 1 1 Zout

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 9 Fetching a Word from Memory

Memory data bus Internal processor bus

MDRoutE MDRout Move (R1), R2

1. R1out, MARin, Read 2. MDRinE, WMFC MDR 3. MDRout, R2in WMFC: is the control signal that causes the processor’s control MDRinE MDRin circuitry to wait for the arrival of the MFC signal.

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 10 Execution of a Complete Instruction

¾ Ass (R3), R1: adds the contents of a memory location pointed to by R3 to register R1. Executing this instruction requires the following actions: ‹ Fetch the instruction ‹ Fetch the first operand (the contents of the memory location pointed to by R3) ‹ Perform the addition ‹ Load the result into R1

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 11 Control Sequence

Riin

Rjout Ri Rj Riout Yin

Y Rjin Instruction fetch Constant 4 Step Action

Select 1PCout, MARin, Read, Select4 Add, Zin 2Zout, PCin, Yin, WMFC AB ALU 3MDRout, IRin 4R3out, MARin, Read Zin 5R1out, Yin, WMFC 6MDRout, SelectY, Add, Zin Z 7Zout, R1in, End Zout

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 12 Control

¾ To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence. Computer designers use a wide variety of techniques to solve this problem. ¾ The approaches used fall into one of two categories: hardwired control and microprogrammed control

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 13 Control Unit Organization

CLK Clock Control step counter

External inputs

Decoder/encoder IR Conditional codes

Control signals

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 14 Finite State Machine for Control

PCWrite PCWriteCond IorD MemRead MemWrite IRW rite Control logic MemtoReg PCSource ALUOp Outputs ALUSrcB ALUSrcA RegWrite RegDst

NS3 NS2 NS1 Inputs NS0 Op5 Op4 Op3 Op2 Op1 Op0 S3 S2 S1 S0

Instruction register State register opcode field

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 15 PLA Implementation

Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0

PCWrite PCWriteCond IorD MemRead MemWrite IRWrite MemtoReg PCSource1 PCSource0 ALUOp1 ALUOp0 ALUSrcB1 ALUSrcB0 ALUSrcA RegWrite RegDst NS3 NS2 NS1 NS0

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 16 ROM Implementation ¾ ROM = "Read Only Memory" ‹ values of memory locations are fixed ahead of time ¾ A ROM can be used to implement a truth table ‹ if the address is m-bits, we can address 2m entries in the ROM. ‹ our outputs are the bits of data that the address points to. 0 0 0 0 0 1 1 0 0 1 1 1 0 0 mn 0 1 0 1 1 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 m is the "height", and n is the "width"

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU Microprogrammed Control ¾ Microprogrammed control ‹ Control signals are generated by a program similar to machine language programs

Control unit PCWrite PCWriteCond IorD Microcode memory MemRead Datapath MemWrite IRWrite BWrite Outputs MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst AddrCtl Input 1

Microprogram counter

Adder

Address select logic

Instruction register opcode field

Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU 18 Microinstruction format Field name Value Signals active Comment Add ALUOp = 00 Cause the ALU to add. ALU control Subt ALUOp = 01 Cause the ALU to subtract; this implements the compare for branches. Func code ALUOp = 10 Use the instruction's function code to determine ALU control. SRC1 PC ALUSrcA = 0 Use the PC as the first ALU input. A ALUSrcA = 1 Register A is the first ALU input. B ALUSrcB = 00 Register B is the second ALU input. SRC2 4 ALUSrcB = 01 Use 4 as the second ALU input. Extend ALUSrcB = 10 Use output of the sign extension unit as the second ALU input. Extshft ALUSrcB = 11 Use the output of the shift-by-two unit as the second ALU input. Read Read two registers using the rs and rt fields of the IR as the register numbers and putting the data into registers A and B. Write ALU RegWrite, Write a register using the rd field of the IR as the register number and Register RegDst = 1, the contents of the ALUOut as the data. control MemtoReg = 0 Write MDR RegWrite, Write a register using the rt field of the IR as the register number and RegDst = 0, the contents of the MDR as the data. MemtoReg = 1 Read PC MemRead, Read memory using the PC as address; write result into IR (and lorD = 0 the MDR). Memory Read ALU MemRead, Read memory using the ALUOut as address; write result into MDR. lorD = 1 Write ALU MemWrite, Write memory using the ALUOut as address, contents of B as the lorD = 1 data. ALU PCSource = 00 Write the output of the ALU into the PC. PCWrite PC write control ALUOut-cond PCSource = 01, If the Zero output of the ALU is active, write the PC with the contents PCWriteCond of the register ALUOut. jump address PCSource = 10, Write the PC with the jump address from the instruction. PCWrite Seq AddrCtl = 11 Choose the next microinstruction sequentially. Sequencing Fetch AddrCtl = 00 Go to the first microinstruction to begin a new instruction. Dispatch 1 AddrCtl = 01 Dispatch using the ROM 1. Dispatch 2 AddrCtl = 10 Dispatch using the ROM 2. Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU