Growing Market Share by Embracing AI
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Quantum Imaging for Semiconductor Industry
Quantum Imaging for Semiconductor Industry Anna V. Paterova1,*, Hongzhi Yang1, Zi S. D. Toa1, Leonid A. Krivitsky1, ** 1Institute of Materials Research and Engineering, Agency for Science Technology and Research (A*STAR), 138634 Singapore *[email protected] **[email protected] Abstract Infrared (IR) imaging is one of the significant tools for the quality control measurements of fabricated samples. Standard IR imaging techniques use direct measurements, where light sources and detectors operate at IR range. Due to the limited choices of IR light sources or detectors, challenges in reaching specific IR wavelengths may arise. In our work, we perform indirect IR microscopy based on the quantum imaging technique. This method allows us to probe the sample with IR light, while the detection is shifted into the visible or near-IR range. Thus, we demonstrate IR quantum imaging of the silicon chips at different magnifications, wherein a sample is probed at 1550 nm wavelength, but the detection is performed at 810 nm. We also analyze the possible measurement conditions of the technique and estimate the time needed to perform quality control checks of samples. Infrared (IR) metrology plays a significant role in areas ranging from biological imaging1-5 to materials characterisation6 and microelectronics7. For example, the semiconductor industry utilizes IR radiation for non-destructive microscopy of silicon-based devices. However, IR optical components, such as synchrotrons8, quantum cascade lasers, and HgCdTe (also known as MCT) photodetectors, are expensive. Some of these components, in order to maximize the signal-to-noise ratio, may require cryogenic cooling, which further increases costs over the operational lifetime. -
DEEP-Hybriddatacloud ASSESSMENT of AVAILABLE TECHNOLOGIES for SUPPORTING ACCELERATORS and HPC, INITIAL DESIGN and IMPLEMENTATION PLAN
DEEP-HybridDataCloud ASSESSMENT OF AVAILABLE TECHNOLOGIES FOR SUPPORTING ACCELERATORS AND HPC, INITIAL DESIGN AND IMPLEMENTATION PLAN DELIVERABLE: D4.1 Document identifier: DEEP-JRA1-D4.1 Date: 29/04/2018 Activity: WP4 Lead partner: IISAS Status: FINAL Dissemination level: PUBLIC Permalink: http://hdl.handle.net/10261/164313 Abstract This document describes the state of the art of technologies for supporting bare-metal, accelerators and HPC in cloud and proposes an initial implementation plan. Available technologies will be analyzed from different points of views: stand-alone use, integration with cloud middleware, support for accelerators and HPC platforms. Based on results of these analyses, an initial implementation plan will be proposed containing information on what features should be developed and what components should be improved in the next period of the project. DEEP-HybridDataCloud – 777435 1 Copyright Notice Copyright © Members of the DEEP-HybridDataCloud Collaboration, 2017-2020. Delivery Slip Name Partner/Activity Date From Viet Tran IISAS / JRA1 25/04/2018 Marcin Plociennik PSNC 20/04/2018 Cristina Duma Aiftimiei Reviewed by INFN 25/04/2018 Zdeněk Šustr CESNET 25/04/2018 Approved by Steering Committee 30/04/2018 Document Log Issue Date Comment Author/Partner TOC 17/01/2018 Table of Contents Viet Tran / IISAS 0.01 06/02/2018 Writing assignment Viet Tran / IISAS 0.99 10/04/2018 Partner contributions WP members 1.0 19/04/2018 Version for first review Viet Tran / IISAS Updated version according to 1.1 22/04/2018 Viet Tran / IISAS recommendations from first review 2.0 24/04/2018 Version for second review Viet Tran / IISAS Updated version according to 2.1 27/04/2018 Viet Tran / IISAS recommendations from second review 3.0 29/04/2018 Final version Viet Tran / IISAS DEEP-HybridDataCloud – 777435 2 Table of Contents Executive Summary.............................................................................................................................5 1. -
Global Semiconductor Industry | Accenture
GLOBALITY AND COMPLEXITY of the Semiconductor Ecosystem The semiconductor industry is a truly global affair. Around the world, semiconductor chip designers use intellectual property (IP) licenses and design verification to provide designs to wafer fabricators, which use raw silicon, photomasks, and equipment to create chips for package manufacturing to assemble with printed circuit board (PCB) substrates for delivery to end customers. In fact, components for a chip could travel more than 25,000 miles by the time it finds its way into a television set, mobile phone, automobile, computer, or any of the millions of products that now rely on chips to operate (Figure 1). 2 | Globality and Complexity of the Semiconductor Ecosystem Figure 1: Components for a chip could travel more than 25,000 miles before completion IP Licenses Euipment Modules Package Raw Silicon Manufacturing PC Substrates Asembly Standard Products and Test components Wafer Fabrication Equipment Chip Design Design Verification Photomask Wafer Manufacturing Fabrication The Global Semiconductor Alliance (GSA) and Accenture have teamed up to conduct a joint study on the globality and complexity of the semiconductor ecosystem to explore the interdependencies and benefits of the cross-border partnerships required to produce semiconductors, as well as to illustrate what’s needed to keep this global ecosystem operating efficiently and profitably. Industry executives can use this study to inform their company strategies, as well as to educate non-semiconductor partners, including policy makers, on the nature of their business to promote a better understanding of the important role semiconductors play in everyday life and on the globe-spanning ecosystem that’s needed to produce them. -
Wire-Aware Architecture and Dataflow for CNN Accelerators
Wire-Aware Architecture and Dataflow for CNN Accelerators Sumanth Gudaparthi Surya Narayanan Rajeev Balasubramonian University of Utah University of Utah University of Utah Salt Lake City, Utah Salt Lake City, Utah Salt Lake City, Utah [email protected] [email protected] [email protected] Edouard Giacomin Hari Kambalasubramanyam Pierre-Emmanuel Gaillardon University of Utah University of Utah University of Utah Salt Lake City, Utah Salt Lake City, Utah Salt Lake City, Utah [email protected] [email protected] pierre- [email protected] ABSTRACT The 52nd Annual IEEE/ACM International Symposium on Microarchitecture In spite of several recent advancements, data movement in modern (MICRO-52), October 12–16, 2019, Columbus, OH, USA. ACM, New York, NY, USA, 13 pages. https://doi.org/10.1145/3352460.3358316 CNN accelerators remains a significant bottleneck. Architectures like Eyeriss implement large scratchpads within individual pro- cessing elements, while architectures like TPU v1 implement large systolic arrays and large monolithic caches. Several data move- 1 INTRODUCTION ments in these prior works are therefore across long wires, and ac- Several neural network accelerators have emerged in recent years, count for much of the energy consumption. In this work, we design e.g., [9, 11, 12, 28, 38, 39]. Many of these accelerators expend sig- a new wire-aware CNN accelerator, WAX, that employs a deep and nificant energy fetching operands from various levels of the mem- distributed memory hierarchy, thus enabling data movement over ory hierarchy. For example, the Eyeriss architecture and its row- short wires in the common case. An array of computational units, stationary dataflow require non-trivial storage for scratchpads and each with a small set of registers, is placed adjacent to a subarray registers per processing element (PE) to maximize reuse [11]. -
The Next Growth Engine for the Semiconductor Industry
www.pwc.com The Internet of Things: The next growth engine for the semiconductor industry A study of global semi conductor trends and powerful drivers behind them – special focus on the impacts of Internet of Things. The Internet of Things: The next growth engine for the semiconductor industry A study of global semi conductor trends and powerful drivers behind them – special focus on the impacts of Internet of Things. The Internet of Things: The next growth engine for the semiconductor industry Published by PricewaterhouseCoopers AG Wirtschaftsprüfungsgesellschaft By Raman Chitkara, Werner Ballhaus, Olaf Acker, Dr. Bin Song, Anand Sundaram and Maria Popova May 2015, 36 pages, 8 figures The results of this survey and the contributions from our experts are meant to serve as a general reference for our clients. For advice on individual cases, please refer to the sources cited in this study or consult one of the PwC contacts listed at the end of the publication. Publications express the opinions of the authors. All rights reserved. Reproduction, microfilming, storing or processing in electronic media is not allowed without the permission of the publishers. Printed in Germany © May 2015 PwC. All rights reserved. PwC refers to the PwC network and/or one or more of its member firms, each of which is a separate legal entity. Please see www.pwc.com/structure for further details. MW-15-2285 Preface Preface The ever-expanding array of cutting-edge devices such as smartphones, tablets, ultramobile, electric cars, new aircraft, and wearable devices, is driving a constant expansion of the number of semiconductor components we use in our daily lives. -
Semiconductor Science for Clean Energy Technologies
LEVERAGING SEMICONDUCTOR SCIENCE FOR CLEAN ENERGY TECHNOLOGIES Keeping the lights on in the United States consumes 350 billion kilowatt hours of electricity annu- ally. Most of that light still comes from incandescent bulbs, which haven’t changed much since Thomas Edison invented them 140 years ago. But now a dramatically more efficient lighting tech- nology is seeing rapid adoption: semiconductor devices known as light-emitting diodes (LEDs) use 85 percent less energy than incandescent bulbs, last 25 times as long, and have the potential to save U.S. consumers a huge portion of the electricity now used for lighting. High-performance solar power plant in Alamosa, Colorado. It generates electricity with multi-layer solar cells, developed by the National Renewable Energy Laboratory, that absorb and utilize more of the sun’s energy. (Dennis Schroeder / National Renewable Energy Laboratory) How we generate electricity is also changing. The costs of to produce an electrical current. The challenge has been solar cells that convert light from the sun into electricity to improve the efficiency with which solar cells convert have come down dramatically over the past decade. As a sunlight to electricity and to reduce their cost for commer- result, solar power installations have grown rapidly, and cial applications. Initially, solar cell production techniques in 2016 accounted for a significant share of all the new borrowed heavily from the semiconductor industry. Silicon electrical generating capacity installed in the U.S. This solar cells are built on wafers cut from ingots of crystal- grid-scale power market is dominated by silicon solar cells, line silicon, just as are the chips that drive computers. -
Semiconductor Industry
Semiconductor industry Heat transfer solutions for the semiconductor manufacturing industry In the microelectronics industry a the cleanroom, an area where the The following applications are all semiconductor fabrication plant environment is controlled to manufactured in a semicon fab: (commonly called a fab) is a factory eliminate all dust – even a single where devices such as integrated speck can ruin a microcircuit, which Microchips: Manufacturing of chips circuits are manufactured. A business has features much smaller than with integrated circuits. that operates a semiconductor fab for dust. The cleanroom must also be LED lighting: Manufacturing of LED the purpose of fabricating the designs dampened against vibration and lamps for lighting purposes. of other companies, such as fabless kept within narrow bands of PV industry: Manufacturing of solar semiconductor companies, is known temperature and humidity. cells, based on Si wafer technology or as a foundry. If a foundry does not also thin film technology. produce its own designs, it is known Controlling temperature and Flat panel displays: Manufacturing of as a pure-play semiconductor foundry. humidity is critical for minimizing flat panels for everything from mobile static electricity. phones and other handheld devices, Fabs require many expensive devices up to large size TV monitors. to function. The central part of a fab is Electronics: Manufacturing of printed circuit boards (PCB), computer and electronic components. Semiconductor plant Waste treatment The cleanroom Processing equipment Preparation of acids and chemicals Utility equipment Wafer preparation Water treatment PCW Water treatment UPW The principal layout and functions of would be the least complex, requiring capacities. Unique materials combined the fab are similar in all the industries. -
Efficient Management of Scratch-Pad Memories in Deep Learning
Efficient Management of Scratch-Pad Memories in Deep Learning Accelerators Subhankar Pal∗ Swagath Venkataramaniy Viji Srinivasany Kailash Gopalakrishnany ∗ y University of Michigan, Ann Arbor, MI IBM TJ Watson Research Center, Yorktown Heights, NY ∗ y [email protected] [email protected] fviji,[email protected] Abstract—A prevalent challenge for Deep Learning (DL) ac- TABLE I celerators is how they are programmed to sustain utilization PERFORMANCE IMPROVEMENT USING INTER-NODE SPM MANAGEMENT. Incep Incep Res Multi- without impacting end-user productivity. Little prior effort has Alex VGG Goog SSD Res Mobile Squee tion- tion- Net- Head Geo been devoted to the effective management of their on-chip Net 16 LeNet 300 NeXt NetV1 zeNet PTB v3 v4 50 Attn Mean Scratch-Pad Memory (SPM) across the DL operations of a 1 SPM 1.04 1.19 1.94 1.64 1.58 1.75 1.31 3.86 5.17 2.84 1.02 1.06 1.76 Deep Neural Network (DNN). This is especially critical due to 1-Step 1.04 1.03 1.01 1.10 1.11 1.33 1.18 1.40 2.84 1.57 1.01 1.02 1.24 trends in complex network topologies and the emergence of eager execution. This work demonstrates that there exists up to a speedups of 12 ConvNets, LSTM and Transformer DNNs [18], 5.2× performance gap in DL inference to be bridged using SPM management, on a set of image, object and language networks. [19], [21], [26]–[33] compared to the case when there is no We propose OnSRAM, a novel SPM management framework SPM management, i.e. -
Efficient Processing of Deep Neural Networks
Efficient Processing of Deep Neural Networks Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer Massachusetts Institute of Technology Reference: V. Sze, Y.-H.Chen, T.-J. Yang, J. S. Emer, ”Efficient Processing of Deep Neural Networks,” Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020 For book updates, sign up for mailing list at http://mailman.mit.edu/mailman/listinfo/eems-news June 15, 2020 Abstract This book provides a structured treatment of the key principles and techniques for enabling efficient process- ing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the- art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas. 1 Contents Preface 9 I Understanding Deep Neural Networks 13 1 Introduction 14 1.1 Background on Deep Neural Networks . -
Accelerate Scientific Deep Learning Models on Heteroge- Neous Computing Platform with FPGA
Accelerate Scientific Deep Learning Models on Heteroge- neous Computing Platform with FPGA Chao Jiang1;∗, David Ojika1;5;∗∗, Sofia Vallecorsa2;∗∗∗, Thorsten Kurth3, Prabhat4;∗∗∗∗, Bhavesh Patel5;y, and Herman Lam1;z 1SHREC: NSF Center for Space, High-Performance, and Resilient Computing, University of Florida 2CERN openlab 3NVIDIA 4National Energy Research Scientific Computing Center 5Dell EMC Abstract. AI and deep learning are experiencing explosive growth in almost every domain involving analysis of big data. Deep learning using Deep Neural Networks (DNNs) has shown great promise for such scientific data analysis appli- cations. However, traditional CPU-based sequential computing without special instructions can no longer meet the requirements of mission-critical applica- tions, which are compute-intensive and require low latency and high throughput. Heterogeneous computing (HGC), with CPUs integrated with GPUs, FPGAs, and other science-targeted accelerators, offers unique capabilities to accelerate DNNs. Collaborating researchers at SHREC1at the University of Florida, CERN Openlab, NERSC2at Lawrence Berkeley National Lab, Dell EMC, and Intel are studying the application of heterogeneous computing (HGC) to scientific prob- lems using DNN models. This paper focuses on the use of FPGAs to accelerate the inferencing stage of the HGC workflow. We present case studies and results in inferencing state-of-the-art DNN models for scientific data analysis, using Intel distribution of OpenVINO, running on an Intel Programmable Acceleration Card (PAC) equipped with an Arria 10 GX FPGA. Using the Intel Deep Learning Acceleration (DLA) development suite to optimize existing FPGA primitives and develop new ones, we were able accelerate the scientific DNN models under study with a speedup from 2.46x to 9.59x for a single Arria 10 FPGA against a single core (single thread) of a server-class Skylake CPU. -
Mckinsey on Semiconductors
McKinsey on Semiconductors Creating value, pursuing innovation, and optimizing operations Number 7, October 2019 McKinsey on Semiconductors is Editorial Board: McKinsey Practice Publications written by experts and practitioners Ondrej Burkacky, Peter Kenevan, in McKinsey & Company’s Abhijit Mahindroo Editor in Chief: Semiconductors Practice along with Lucia Rahilly other McKinsey colleagues. Editor: Eileen Hannigan Executive Editors: To send comments or request Art Direction and Design: Michael T. Borruso, copies, email us: Leff Communications Bill Javetski, McKinsey_on_ Semiconductors@ Mark Staples McKinsey.com. Data Visualization: Richard Johnson, Copyright © 2019 McKinsey & Cover image: Jonathon Rivait Company. All rights reserved. © scanrail/Getty Images Managing Editors: This publication is not intended to Heather Byer, Venetia Simcock be used as the basis for trading in the shares of any company or for Editorial Production: undertaking any other complex or Elizabeth Brown, Roger Draper, significant financial transaction Gwyn Herbein, Pamela Norton, without consulting appropriate Katya Petriwsky, Charmaine Rice, professional advisers. John C. Sanchez, Dana Sand, Sneha Vats, Pooja Yadav, Belinda Yu No part of this publication may be copied or redistributed in any form without the prior written consent of McKinsey & Company. Table of contents What’s next for semiconductor How will changes in the 3 profits and value creation? 47 automotive-component Semiconductor profits have been market affect semiconductor strong over the past few years. companies? Could recent changes within the The rise of domain control units industry stall their progress? (DCUs) will open new opportunities for semiconductor companies. Artificial-intelligence hardware: Right product, right time, 16 New opportunities for 50 right location: Quantifying the semiconductor companies semiconductor supply chain Artificial intelligence is opening Problems along the the best opportunities for semiconductor supply chain semiconductor companies in are difficult to diagnose. -
Building America's Innovation Economy
BUILDING AMERICA’S INNOVATION ECONOMY Maintaining a vibrant U.S. semiconductor industry is critical to America’s continued strength. For over 40 years, SIA has represented the semiconductor industry, one of America’s top export sectors and a key driver of our country’s economic strength, national security, and global technology leadership. SIA members account for 95 percent of U.S. industry sales and 78 percent of all global sales. SEMICONDUCTORS ARE THE BRAINS OF MODERN ELECTRONICS, enabling advances in medical devices and health care, communications, computing, defense, transportation, clean energy, and technologies of the future such as artificial intelligence, quantum computing, and advanced wireless networks. THE U.S. SEMICONDUCTOR INDUSTRY IS THE WORLDWIDE INDUSTRY LEADER with about half of global market share and sales of $193 billion in 2019. THE SEMICONDUCTOR INDUSTRY DIRECTLY EMPLOYS NEARLY A QUARTER OF A MILLION PEOPLE IN THE U.S. and supports more than one million additional U.S. jobs. NEARLY HALF OF U.S. SEMICONDUCTOR MANUFACTURERS' PRODUCTION IS DONE IN THE UNITED STATES, and 19 states are home to major semiconductor manufacturing facilities. SEMICONDUCTORS ARE A TOP-5 U.S. EXPORT, and more than 80% of U.S. semiconductor companies’ sales are to overseas customers. The United States exported $46 billion in semiconductors in 2019 and maintains a consistent trade surplus in semiconductors, including with major trading partners such as China. THE U.S. SEMICONDUCTOR INDUSTRY ANNUALLY INVESTS ABOUT ONE-FIFTH OF ITS REVENUE INTO R&D ($40 billion in 2019), which is the second-highest share of any major U.S. industry, behind only the pharmaceutical industry.