DS1876 SFP Controller with Dual LDD Interface

19-5153; Rev 0; 2/10

SFP Controller with Dual LDD Interface DS1876 General Description Features The DS1876 controls and monitors all functions for S Meets All SFF-8472 Transmitter Control and dual transmitter modules. The memory map is based Monitoring Requirements on SFF-8472. The DS1876 supports APC and modula- S Six Analog Monitor Channels: Temperature, VCC, tion control and eye safety functionality for two laser PMON1, BMON1, PMON2, BMON2 drivers. It continually monitors for high output current, PMON_ and BMON_ Support Internal and high bias current, and low and high transmit power to External Calibration ensure that laser shutdown for eye safety requirements Scalable Dynamic Range are met without adding external components. Six ADC Internal Direct-to-Digital Temperature Sensor channels monitor VCC, temperature, and four external Alarm and Warning Flags for All Monitored monitor inputs that can be used to meet all monitoring Channels requirements. S Six Quick Trips for Fast Monitoring of Critical Functions for Laser Safety Applications S Four 10-Bit Delta-Sigma Outputs Dual Tx Video SFP Modules Each Controlled by 72-Entry Temperature Lookup Table (LUT) Ordering Information S Digital I/O Pins: Six Inputs, Five Outputs S Comprehensive Fault Measurement System with PART TEMP RANGE PIN-PACKAGE Maskable Laser Shutdown Capability DS1876T+ -40NC to +95NC 28 TQFN-EP* S Flexible, Two-Level Password Scheme Provides DS1876T+T&R -40NC to +95NC 28 TQFN-EP* Three Levels of Security +Denotes a lead(Pb)-free/RoHS-compliant package. S 256 Additional Bytes Located at A0h Slave T&R = Tape and reel. *EP = Exposed pad. Address S Transmitter 1 is Accessed at A2h Slave Address S Transmitter 2 is Accessed at B2h Slave Address S I2C-Compatible Interface S +2.85V to +3.9V Operating Voltage Range S -40NC to +95NC Operating Temperature Range S 28-Pin TQFN (5mm x 5mm x 0.8mm) Package

______Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. SFP Controller with Dual LDD Interface

TABLE OF CONTENTS

Absolute Maximum Ratings ...... 5 Recommended Operating Conditions ...... 5 DC Electrical Characteristics ...... 5

DS1876 MOD_, APC_ Electrical Characteristics...... 6 Analog Quick-Trip Characteristics ...... 6 Analog Voltage Monitoring Characteristics ...... 6 Digital Thermometer Characteristics ...... 7 AC Electrical Characteristics ...... 7 Quick-Trip Timing Characteristics...... 7 I2C AC Electrical Characteristics...... 7 Nonvolatile Memory Characteristics...... 8 Typical Operating Characteristics ...... 9 Pin Configuration ...... 10 Pin Description...... 10 Block Diagram ...... 11 Typical Operating Circuit ...... 12 Detailed Description...... 12 DACs During Power-Up ...... 12 DACs as a Function of Transmit Disable (TXD1, TXD2) ...... 13 Quick-Trip Timing ...... 13 Monitors and Fault Detection ...... 14 Monitors ...... 14 Six Quick-Trip Monitors and Alarms...... 14 Six ADC Monitors and Alarms...... 14 ADC Timing ...... 15 Right-Shifting ADC Result ...... 15 Low-Voltage Operation ...... 15 Delta-Sigma Outputs...... 16 Digital I/O Pins...... 18 IN1, RSEL, OUT1, RSELOUT...... 18 TXF1, TXF2, TXFOUT, TXD1, TXD2, TXDOUT1, TXDOUT2 ...... 18 Transmit Fault (TXFOUT) Output ...... 19 Die Identification ...... 19 I2C Communication ...... 19 I2C Definitions...... 19 I2C Protocol...... 21

2 ______SFP Controller with Dual LDD Interface DS1876 TABLE OF CONTENTS (continued)

Memory Organization...... 22 Shadowed EEPROM...... 23 Register Descriptions...... 24 Memory Map Access Codes ...... 24 Memory Addresses A0h, A2h, and B2h...... 24 Lower Memory Register Map ...... 25 Table 01h Register Map ...... 25 Table 02h Register Map ...... 26 Table 04h Register Map ...... 26 Table 05h Register Map ...... 27 Table 06h Register Map ...... 27 Auxiliary Memory A0h Register Map ...... 27 Lower Memory Register Descriptions...... 28 Table 01h Register Descriptions ...... 40 Table 02h Register Descriptions...... 44 Table 04h Register Descriptions...... 64 Table 06h Register Descriptions...... 65 Auxiliary Memory A0h Register Descriptions ...... 68 Applications Information...... 69 Power-Supply Decoupling...... 69 SDA and SCL Pullup Resistors...... 69 Package Information...... 69

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LIST OF FIGURES

Figure 1. Power-Up Timing...... 13 Figure 2. TXD1, TXD2 Timing...... 13 Figure 3. Quick-Trip Sample Timing...... 14

DS1876 Figure 4. ADC Round-Robin Timing...... 15 Figure 5. Low-Voltage Hysteresis Example ...... 16 Figure 6. Recommended RC Filter for DAC Outputs in Voltage Mode and Current Sink Mode...... 16 Figure 7. 3-Bit (8-Position) Delta-Sigma Example ...... 17 Figure 8. DAC OFFSET LUTs...... 17 Figure 9. Logic Diagram 1 ...... 18 Figure 10. Logic Diagram 2 ...... 18 Figure 11a. TXFOUT Nonlatched Operation ...... 19 Figure 11b. TXFOUT Latched Operation ...... 19 Figure 12. I2C Timing...... 20 Figure 13. Example I2C Timing ...... 21 Figure 14. Memory Map...... 23

LIST OF TABLES

Table 1. Acronyms ...... 13 Table 2. ADC Default Monitor Full-Scale Ranges ...... 14

4 ______SFP Controller with Dual LDD Interface DS1876 ABSOLUTE MAXIMUM RATINGS Voltage Range on PMON_, BMON_, RSEL, Continuous Power Dissipation IN1, TXF_, and TXD_ Pins 28-Pin TQFN (derate 34.5mW/°C) above +70°C ....2758.6mW Relative to Ground ...... -0.5V to (VCC + 0.5V)* Operating Temperature Range ...... -40NC to +95NC Voltage Range on VCC, SDA, SCL, Programming Temperature Range ...... 0NC to +95NC OUT1, RSELOUT, and TXFOUT Pins Storage Temperature Range ...... -55NC to +125NC Relative to Ground ...... -0.5V to +6V Soldering Temperature ...... Refer to the IPC/JEDEC J-STD-020 Specification. *Subject to not exceeding +6V.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Main Supply Voltage VCC (Note 1) +2.85 +3.9 V High-Level Input Voltage 0.7 x VCC + VIH:1 V (SDA, SCL) VCC 0.3 Low-Level Input Voltage 0.3 x VIL:1 -0.3 V (SDA, SCL) VCC High-Level Input Voltage V + V 2.0 CC V (TXD_, TXF_, RSEL, IN1) IH:2 0.3 Low-Level Input Voltage V -0.3 +0.8 V (TXD_, TXF_, RSEL, IN1) IL:2

DC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current ICC (Notes 1, 2) 2.5 10 mA Output Leakage (SDA, OUT1, I 1 FA RSELOUT, TXFOUT) LO Low-Level Output Voltage I = 4mA 0.4 (SDA, OUT1, RSELOUT, OL V V TXDOUT_, MOD_, APC_, OL IOL = 6mA 0.6 TXFOUT) High-Level Output Voltage V - V I = 4mA CC V (MOD_, APC_, TXDOUT_) OH OH 0.4 TXDOUT_ Before EEPROM 10 100 nA Recall MOD_, APC_ Before Recall Figure 1 10 100 nA Input Leakage Current I 1 FA (SCL, TXD_, RSEL, IN1, TXF_) LI Digital Power-On Reset POD 1.0 2.2 V Analog Power-On Reset POA 2.0 2.75 V

______5 SFP Controller with Dual LDD Interface

MOD_, APC_ ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Main Oscillator Frequency fOSC 5 MHz Delta-Sigma Input-Clock f f /2 MHz Frequency DS OSC DS1876 Reference Voltage Input (REFIN) VREFIN Minimum 0.1FF to GND 2 VCC V Output Range 0 VREFIN V See the Delta-Sigma Outputs section for Output Resolution 10 Bits details Output Impedance RDS 35 100 I

ANALOG QUICK-TRIP CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TXP HI, TXP LO Full-Scale 2.507 V Voltage HBIAS Full-Scale Voltage 1.25 V PMON_ Input Resistance 35 50 65 kΩ Resolution 8 Bits Error TA = +25°C ±2 %FS Integral Nonlinearity -1 +1 LSB Differential Nonlinearity -1 +1 LSB Temperature Drift -2.5 +2.5 %FS Offset -5 +10 mV

ANALOG VOLTAGE MONITORING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC Resolution 13 Bits Input/Supply Accuracy ACC At factory setting 0.25 0.5 %FS (BMON_, PMON_, VCC) Update Rate for Temperature, tRR 64 78 ms BMON_, PMON_, VCC Input/Supply Offset VOS (Note 3) 0 5 LSB (BMON_, PMON_, VCC) BMON_, PMON_ 2.5 Factory Setting (Note 4) V VCC 6.5536

6 ______SFP Controller with Dual LDD Interface DS1876 DIGITAL THERMOMETER CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Thermometer Error TERR -40NC to +95NC -3 +3 NC

AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TXD_ Enable tOFF From ↑ TXD_ 5 Fs Recovery from TXD_ Disable tON From ↓ TXD_ 1 ms (Figure 2) tINITR1 From ↓ TXD_ 131 Fault Reset Time (to TXFOUT = 0) On power-up or ↓ TXD_, when VCC LO ms tINITR2 161 alarm is detected (Note 5) Fault Assert Time (to TXFOUT = 1) tFAULT After HTXP_, LTXP_, HBATH_ 1.6 10.5 Fs

QUICK-TRIP TIMING CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output-Enable Time Following POA tINIT 20 ms Sample Time per Quick-Trip t 1.6 Fs Comparison REP

I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.85V to +3.9V, TA = -40NC to +95NC, timing referenced to VIL(MAX) and VIH(MIN), unless otherwise noted. See the I2C Communication section.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 6) 0 400 kHz Clock Pulse-Width Low tLOW 1.3 Fs Clock Pulse-Width High tHIGH 0.6 Fs Bus Free Time Between STOP and t 1.3 Fs START Condition BUF START Hold Time tHD:STA 0.6 Fs START Setup Time tSU:STA 0.6 Fs Data Out Hold Time tHD:DAT 0 0.9 Fs Data In Setup Time tSU:DAT 100 ns Rise Time of Both SDA and SCL 20 + tR (Note 7) 300 ns Signals 0.1CB Fall Time of Both SDA and SCL 20 + tF (Note 7) 300 ns Signals 0.1CB STOP Setup Time tSU:STO 0.6 Fs Capacitive Load for Each Bus Line CB 400 pF EEPROM Write Time tWR (Note 8) 20 ms

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NONVOLATILE MEMORY CHARACTERISTICS (VCC = +2.85V to +3.9V, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS At +25NC 200,000 EEPROM Write Cycles At +85NC 50,000

DS1876 Note 1: All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative. Note 2: Inputs are at supply rail. Outputs are not loaded. Note 3: This parameter is guaranteed by design. Note 4: Full scale is user programmable. Note 5: A temperature conversion is completed and MOD1 DAC, MOD2 DAC, APC1 DAC, and APC2 DAC values are recalled from the LUT and VCC has been measured to be above VCC LO alarm, if the VCC LO alarm is enabled. Note 6: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. Note 7: CB—Total capacitance of one bus line in pF. Note 8: EEPROM write begins after a STOP condition occurs.

8 ______SFP Controller with Dual LDD Interface DS1876 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. TEMPERATURE 2.7 3.0 SDA = SCL = VCC DAC POSITIONS = 1FFh DACs AT 1FFh 2.9 SDA = SCL = VCC

2.6 DS1876 toc02 +95°C DS1876 toc01 2.8 2.5 2.7 V = 3.9V 2.6 CC 2.4 2.5 VCC = 3.3V 2.3 2.4 +25°C

SUPPLY CURRENT (mA) 2.3 SUPPLY CURRENT (mA) 2.2 -40°C 2.2 2.1 2.1 VCC = 2.85V 2.0 2.0 2.850 3.150 3.450 3.750 -40 -15 10 35 60 85 VCC (V) TEMPERATURE (°C)

APC1/2 AND MOD1/2 DAC DNL APC1/2 AND MOD1/2 DAC INL 1.0 3 0.8

DS1876 toc03 2 DS1876 toc04 0.6 0.4 1 0.2 0 0 -0.2 -1 -0.4 -0.6 APC1/2 AND MOD1/2 DAC INL (LSB)

APC1/2 AND MOD1/2 DAC DNL (LSB) -2 -0.8 -1.0 -3 0 500 1000 0 500 1000 DAC POSITION (DEC) DAC POSITION (DEC)

PMON1/2 AND BMON1/2 DNL PMON1/2 AND BMON1/2 INL 1.0 1.0 USING FACTORY-PROGRAMMED FULL-SCALE USING FACTORY-PROGRAMMED FULL-SCALE 0.8 VALUE OF 2.5V 0.8 VALUE OF 2.5V 0.6 DS1876 toc05 0.6 DS1876 toc06 0.4 0.4 0.2 0.2 0 0 -0.2 -0.2 -0.4 -0.4 -0.6 -0.6 PMON1/2 AND BMON1/2 INL (LSB) PMON1/2 AND BMON1/2 DNL (LSB) -0.8 -0.8 -1.0 -1.0 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5 PMON1/2 AND BMON1/2 INPUT VOLTAGE (V) PMON1/2 AND BMON1/2 INPUT VOLTAGE (V)

______9 SFP Controller with Dual LDD Interface

Pin Configuration

TOP VIEW CC N.C. GND MOD1 GND TXDOUT2 V MOD2

2120 1918 17 16 15 DS1876 REFIN 22 14 BMON1

TXD2 23 13 PMON1

APC2 24 12 BMON2

APC1 25 DS1876 11 PMON2

VCC 26 10 TXDOUT1 TXF2 27 9 RSEL + *EP OUT1 28 8 GND

1 2 3 4 5 6 7 IN1 SCL SDA TXF1 TXD1 TXFOUT RSELOUT THIN QFN (5mm × 5mm × 0.8mm) *EXPOSED PAD.

Pin Description

PIN NAME FUNCTION PIN NAME FUNCTION 1 RSELOUT Rate-Select Output External Monitor Input BMON1 14 BMON1 2 SCL I2C Serial-Clock Input and HBATH1 Quick Trip 3 SDA I2C Serial-Data Input/Output 15 N.C. No Connection Transmit Fault Output, Open 16, 26 VCC Power-Supply Input 4 TXFOUT Drain 17 TXDOUT2 Transmit Disable Output 2 5 TXF1 Transmit Fault Input 1 19 MOD2 MOD2 DAC, Delta-Sigma Output Digital Input. General-purpose 20 MOD1 MOD1 DAC, Delta-Sigma Output 6 IN1 input, AS1 in SFF-8079, or RS1 Reference Input for DAC1 and 22 REFIN in SFF-8431. DAC2 7 TXD1 Transmit Disable Input 1 23 TXD2 Transmit Disable Input 2 8, 18, 21 GND Ground Connection 24 APC2 APC2 DAC, Delta-Sigma Output 9 RSEL Rate-Select Input 25 APC1 APC1 DAC, Delta-Sigma Output 10 TXDOUT1 Transmit Disable Output 1 27 TXF2 Transmit Fault Input 2 External Monitor Input PMON2 Digital Output. General-purpose 11 PMON2 and HTXP2/LTXP2 Quick Trip 28 OUT1 output, AS1 output in SFF-8079, External Monitor Input BMON2 or RS1 output in SFF-8431. 12 BMON2 and HBATH2 Quick Trip — EP Exposed Pad (Connect to GND) External Monitor Input PMON1 13 PMON1 and HTXP1/LTXP1 Quick Trip

10 ______SFP Controller with Dual LDD Interface DS1876 Block Diagram

REFIN VCC

VCC MOD2 DAC MAIN MEMORY 10 BITS MOD2 SDA I2C EEPROM/SRAM SCL INTERFACE A/D CONFIGURATION/RESULTS, APC2 DAC SYSTEM STATUS/CONTROL BITS, 10 BITS APC2 ALARMS/WARNINGS, EEPROM LOOKUP TABLES, 256 BYTES USER MEMORY MOD1 DAC AT A0h 10 BITS MOD1

VCC APC1 DAC 13-BIT 10 BITS APC1 BMON1 ADC PMON1 BMON2 8-BIT QTs PMON2 ANALOG MUX TXFOUT POWER-ON TEMPERATURE ANALOG SENSOR INTERRUPT

VCC

TXD1 TXDOUT1

TXD2 LOGIC CONTROL VCC TXF1

TXF2 TXDOUT2

RSELOUT RSEL

LOGIC CONTROL OUT1 IN1

DS1876 GND

______11 SFP Controller with Dual LDD Interface

Typical Operating Circuit

TOSA2

LDD2 DS1876

BMON APCIN FAULT APCSET MODSET DISABLE

TOSA1

LDD1

BMON APCIN FAULT APCSET MODSET DISABLE RC FILTERS (FIGURE 6)

MOD1 DAC DS1876 APC1 DAC TXF1 EEPROM TXF2 MOD2 TXFOUT TX_FAULT DAC TXDOUT1 APC2 TXDOUT2 DAC TXD1 TX_DISABLE1 TXD2 TX_DISABLE2 BMON1 PMON1 QUICK BMON2 TRIP PMON2 SDA MODE_DEF2 (SDA) I2C SCL MODE_DEF1 (SCL) RP1 RB1 RP2 RB1 ADC

Detailed Description set in EEPROM. After a temperature conversion is completed and if the VCC LO alarm is enabled, an additional The DS1876 integrates the control and monitoring func- VCC conversion above the customer-defined VCC LO tionality required in a dual transmitter system. Key com- alarm level is required before the DACs are updated with ponents of the DS1876 are shown in the Block Diagram the value determined by the temperature conversion and and described in subsequent sections. the DAC LUT. DACs During Power-Up If a fault is detected, and TXD1 and TXD2 are toggled On power-up, the DS1876 sets the DACs to high imped- to re-enable the outputs, the DS1876 powers up fol- ance. After time tINIT, the DACs are set to an initial condition lowing a similar sequence to an initial power-up. The

12 ______SFP Controller with Dual LDD Interface DS1876 Table 1. Acronyms only difference is that the DS1876 already has determined the present temperature, so the tINIT time is not ACRONYM DESCRIPTION required for the DS1876 to recall the APC and MOD ADC Analog-to-Digital Converter set points from EEPROM. See Figure 1. AGC Automatic Gain Control APC Automatic Power Control DACs as a Function of Transmit Disable (TXD1, TXD2) APD Avalanche Photodiode If TXD1 or TXD2 are asserted (logic 1) during normal ATB Alarm Trap Bytes operation, the associated outputs are disabled within DAC Digital-to-Analog Converter tOFF. When TXD1 or TXD2 are deasserted (logic 0), the LOS Loss of Signal DS1876 sets the DACs with the value associated with LUT Lookup Table the present temperature. When asserted, soft TXD1 or NV Nonvolatile soft TXD2 (TXDC) (Lower Memory, Register 6Eh) would QT Quick Trip allow a software control identical to the TXD1 or TXD2 pin TE Tracking Error (Figure 2). The POLARITY register (Table 02h, Register C6h) determines if the off-state value of the DACs is TIA Transimpedance Amplifier VREFIN or 0V. ROSA Receiver Optical Subassembly SEE Shadowed EEPROM Quick-Trip Timing SFF Small Form Factor As shown in Figure 3, the DS1876’s input comparator is shared among the six quick-trip alarms (TXP1 Document Defining Register Map of SFPs SFF-8472 HI, TXP1 LO, TXP2 HI, TXP2 LO, BIAS1 HI, and BIAS2 and SFFs HI). The comparator polls the alarms in a multiplexed SFP Small Form Factor Pluggable sequence. The updates are used to compare the HTXP1, SFP+ Enhanced SFP LTXP1, HTXP2, and LTXP2 (monitor diode voltages) and TOSA Transmit Optical Subassembly the HBATH1 and HBATH2 (BMON1, BMON2) signals TXP Transmit Power against the internal APC and BIAS reference, respectively. Depending on the results of the comparison, the

VPOA VCC 500µs tINIT

DAC HIGH IMPEDANCE OFF STATE LUT VALUE SETTINGS

Figure 1. Power-Up Timing

TXD_

tOFF tON

DAC LUT VALUEOFF STATE LUT VALUE SETTINGS

Figure 2. TXD1, TXD2 Timing

______13 SFP Controller with Dual LDD Interface

QT CYCLE

LTXP2 HBIAS1 HBIAS2 HTXP1 HTXP2 LTXP1 LTXP2 HBIAS1 QUICK-TRIP SAMPLE TIMES SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE

DS1876 tREP

Figure 3. Quick-Trip Sample Timing

Table 2. ADC Default Monitor Full-Scale Ranges SIGNAL (UNITS) +FS SIGNAL +FS HEX -FS SIGNAL -FS HEX Temperature (NC) 127.996 7FFF -128 8000 VCC (V) 6.5528 FFF8 0 0000 PMON1, PMON2 and BMON1, BMON2 (V) 2.4997 FFF8 0 0000

corresponding alarms and warnings (TXP HI1, TXP LO1, The high and low transmit power quick-trip registers TXP HI2, TXP LO2, BIAS HI1, and BIAS HI2) are asserted (HTXP1, HTXP2, LTXP1, and LTXP2) set the thresholds or deasserted. used to compare against the PMON1 and PMON2 volt- After resetting, the device completes one QT cycle ages to determine if the transmit power is within speci- before making comparisons. The TXP LO quick-trip fication. The HBATH1 and HBATH2 QTs compare the alarm updates its alarm bit, but does not create FETG BMON1 and BMON2 inputs (generally from the laser driver’s bias monitor output) against their threshold set- until after TXDEXT. TXP HI and BIAS HI can also be con- tings to determine if the present bias current is above figured to wait for TXDEXT; however, this can be disabled using QTHEXT_ (Table 02h, Register 88h). specification. The bias and power QTs are routed to FETG through interrupt masks to allow combinations Monitors and Fault Detection of these alarms to be used to trigger FETG. The bias Monitors and power QTs are directly connected to TXFOUT (see Monitoring functions on the DS1876 include six quick- Figure 9). The user can program up to eight different trip comparators and six ADC channels. This monitoring temperature-indexed threshold levels for HBATH1 and combined with the alarm enables (Table 01h/05h) deter- HBATH2 (Table 06h, Registers E0h-E7h). mines when/if the DS1876 turns off DACs and triggers Six ADC Monitors and Alarms the TXFOUT and TXDOUT1, TXDOUT2 outputs. All the The ADC monitors six channels that measure tem- monitoring levels and interrupt masks are user program- perature (internal temp sensor), VCC, PMON1, PMON2, mable. BMON1, and BMON2 using an analog multiplexer to Six Quick-Trip Monitors and Alarms measure them round-robin with a single ADC (see the Six quick-trip monitors are provided to detect potential ADC Timing section). The channels have a customer- laser safety issues and LOS status. These monitor the programmable full-scale range, and all channels have a following: customer-programmable offset value that is factory pro- 1) High Bias Current 1 (HBATH1), causing QT BIAS1 HI grammed to a default value (see Table 2). Additionally, PMON1, PMON2 and BMON1, BMON2 can right-shift 2) Low Transmit Power 1 (LTXP1), causing QT TXP1 LO results by up to 7 bits before the results are compared 3) High Transmit Power 1 (HTXP1), causing QT TXP1 HI to alarm thresholds or read over the I2C bus. This allows 4) High Bias Current 2 (HBATH2), causing QT BIAS2 HI customers with specified ADC ranges to calibrate the ADC full scale to a factor of 1/2n of their specified range 5) Low Transmit Power 2 (LTXP2), causing QT TXP2 LO to measure small signals. The DS1876 can then right- 6) High Transmit Power 2 (HTXP2), causing QT TXP2 HI shift the results by n bits to maintain the bit weight of their specification.

14 ______SFP Controller with Dual LDD Interface DS1876 The ADC results (after right-shifting, if used) are com- shifts. Up to seven right-shift operations are allowed and pared to the alarm and warning thresholds after each are executed as a part of every conversion before the conversion, and the corresponding alarms are set that results are compared to the high and low alarm levels, or can be used to trigger the TXFOUT output. These ADC loaded into their corresponding measurement registers thresholds are user programmable, as are the masking (Lower Memory, Registers 64h–6Bh). This is true during registers that can be used to prevent the alarms from trig- the setup of internal calibration as well as during subse- gering the TXFOUT output. quent data conversions. ADC Timing Low-Voltage Operation There are six analog channels that are digitized in a The DS1876 contains two power-on reset (POR) levels. round-robin fashion in the order as shown in Figure 4. The lower level is a digital POR (POD) and the higher The total time required to convert all six channels is tRR level is an analog POR (POA). At startup, before the sup- (see the Analog Voltage Monitoring Characteristics table ply voltage rises above POA, the outputs are disabled, for details). all SRAM locations are set to their defaults, shadowed Right-Shifting ADC Result EEPROM (SEE) locations are zero, and all analog cir- If the weighting of the ADC digital reading must conform cuitry is disabled. When VCC reaches POA, the SEE is to a predetermined full-scale (PFS) value defined by recalled, and the analog circuitry is enabled. While VCC a standard’s specification (e.g., SFF-8472), then right- remains above POA, the device is in its normal operating shifting can be used to adjust the PFS analog measure- state, and it responds based on its nonvolatile configu- ment range while maintaining the weighting of the ADC ration. If during operation VCC falls below POA, but is results. The DS1876’s range is wide enough to cover all still above POD, the SRAM retains the SEE settings from requirements; when the maximum input value is P 1/2 the first SEE recall, but the device analog is shut down the FS value, right-shifting can be used to obtain greater and the outputs disabled. If the supply voltage recovers accuracy. For instance, the maximum voltage might be back above POA, the device immediately resumes nor- 1/8 the specified PFS value, so only 1/8 of the converter’s mal operation. If the supply voltage falls below POD, the range is effective over this range. An alternative is to cali- device SRAM is placed in its default state and another brate the ADC’s full-scale range to 1/8 the readable PFS SEE recall is required to reload the nonvolatile settings. value and use a right-shift value of 3. With this implemen- The EEPROM recall occurs the next time VCC next tation, the resolution of the measurement is increased by exceeds POA. Figure 5 shows the sequence of events a factor of 8, and because the result is digitally divided as the voltage varies. by 8 by right-shifting, the bit weight of the measurement Any time VCC is above POD, the I2C interface can be still meets the standard’s specification (i.e., SFF-8472). used to determine if VCC is below the POA level. This The right-shift operation on the ADC result is carried is accomplished by checking the RDYB bit in the status out based on the contents of right-shift control registers byte (Lower Memory, Register 6Eh). RDYB is set when (Table 02h, Registers 8Eh-8Fh) in EEPROM. Four analog VCC is below POA; when VCC rises above POA, RDYB channels—PMON1, PMON2, BMON1, and BMON2— is timed (within 500Fs) to go to 0, at which point the part each have 3 bits allocated to set the number of right- is fully functional.

ONE ROUND-ROBIN ADC CYCLE

TEMP VCC BMON1 BMON2 PMON1 PMON2 TEMP

tRR

NOTE: IF THE VCC LO ALARM IS ENABLED AT POWER-UP, THE ADC ROUND-ROBIN TIMING CYCLES BETWEEN TEMPERATURE AND VCC ONLY UNTIL VCC IS ABOVE THE VCC LO ALARM THRESHOLD. THIS ALSO OCCURS IF THERE ARE BOTH A TXD1 EVENT AND A TXD2 EVENT UNDER THE SAME CONDITIONS AS PREVIOUSLY MENTIONED.

Figure 4. ADC Round-Robin Timing

______15 SFP Controller with Dual LDD Interface

SEE RECALL SEE RECALL

VPOA

VCC DS1876

VPOD

SEEPRECHARGED RECALLED VALUE PRECHARGED TO 0 RECALLED VALUE PRECHARGED TO 0 TO 0

Figure 5. Low-Voltage Hysteresis Example

A delta-sigma DAC has a digital output using pulse-

3.24kΩ 3.24kΩ density modulation. It provides much lower output ripple DAC VOLTAGE OUTPUT than a standard digital PWM output given the same clock 0.01µF 0.01µF rate and filter components. Before tINIT, the DAC outputs are high impedance. The external RC filter components DS1876 are chosen based on ripple requirements, output load, delta-sigma frequency, and desired response time. Figure 6 shows a recommended filter. 1kΩ 1kΩ DAC CURRENT SINK For illustrative purposes, a 3-bit example is provided in 0.1µF 0.1µF Figure 7. 2kΩ In LUT mode the DACs are each controlled by an LUT DS1876 with high-temperature resolution and an OFFSET LUT with lower temperature resolution. The high-resolution LUTs each have 2NC resolutions. The OFFSET LUTs Figure 6. Recommended RC Filter for DAC Outputs in Voltage are located in the upper eight registers (F8h-FFh) of Mode and Current Sink Mode the table containing each high-resolution LUT. The DAC values are determined as follows: For all device addresses sourced from EEPROM (Table DAC value = LUT + 4 x (OFFSET LUT) 02h, Register 8Bh), the default device addresses are An example calculation for MOD1 DAC is as follows: A2h and B2h until VCC exceeds POA allowing the device address to be recalled from the EEPROM. Assumptions: Delta-Sigma Outputs 1) Temperature is +43NC Four delta-sigma outputs are provided: MOD1, MOD2, 2) Table 04h (MOD1 OFFSET LUT), Register FCh = 2Ah APC1, and APC2. With the addition of an external RC 3) Table 04h (MOD1 LUT), Register AAh = 7Bh filter, these outputs provide 10-bit resolution analog Because the temperature is +43NC, the MOD1 LUT index outputs with the full-scale range set by the input REFIN. is AAh and the MOD1 OFFSET LUT index is FCh. Each output is either manually controlled or controlled using a temperature-indexed LUT. MOD1 DAC = 7Bh + 4 x 2Ah = 123h = 291

16 ______SFP Controller with Dual LDD Interface DS1876

Figure 7. 3-Bit (8-Position) Delta-Sigma Example

DAC OFFSET LUTs (04h/06h)[A2h/B2h] DAC OFFSET LUTs (04h/06h)[A2h/B2h] EIGHT REGISTERS PER DAC EIGHT REGISTERS PER DAC

EACH OFFSET REGISTER CAN BE INDEPENDENTLY FFh EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 1023 SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS 1023 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE EXAMPLE ILLUSTRATES POSITIVE TEMPCO. DAC AND NEGATVE TEMPCO. FEh LUT DAC BITS FDh LUT 7:0 FDh 767 767 FCh FEh BITS DAC FBh DAC FFh FCh LUT 7:0 DAC LUT DAC FAh DAC LUT LUT DAC DAC BITS BITS LUT FBh DAC LUT BITS BITS LUT 7:0 F9h 7:0 BITS 511 511 LUT BITS 7:0 7:0 FAh DAC BITS 7:0 F9h DAC BITS 7:0 F8h DAC LUT 7:0 F8h

DELTA-SIGMA DACs DELTA-SIGMA DACs LUT DAC BITS 7:0 DAC LUT DAC BITS LUT 7:0 LUT BITS LUT 7:0 255 BITS 255 BITS 7:0 BITS 7:0 7:0 7:0

0 0 -40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C -40°C -8°C +8°C +24°C +40°C +56°C +70°C +88°C +104°C

Figure 8. DAC OFFSET LUTs

When temperature controlled, the DACs are updated REFIN and its decoupling must be able to support the after each temperature conversion. edge rate requirements of the delta-sigma outputs. In The reference input, REFIN, is the supply voltage for the a typical application, a 0.1FF capacitor should be con- output buffer of all four DACs. The voltage connected to nected between REFIN and ground.

______17 SFP Controller with Dual LDD Interface

VCC

TXDS_ SET BIAS_ DAC AND RPU MOD_ DAC TO HIGH IMPEDANCE TXD_ TXD_ C R TXDIO_ TXDC_ Q TXDFG_ C DS1876 FETG_ TXDOUT_ TXP_ HI FLAG Q D TXP HI ENABLE S TXDFLT_ HBAL_ FLAG HBAL ENABLE TXFOUTS_

QTHEXT_ TXFINT TXP_ LO FLAG TXFOUTS1 TXFOUT TXP LO ENABLE TXFOUTS2 INVTXF_

FAULT RESET TIMER TXF_ TXDEXT (tINITR1) (130ms) OUT IN POWER-ON TXFS_ IN RESET NOTE: _ CAN BE EITHER 1 OR 2 CORRESPONDING TO TRANSMITTERS 1 OR 2. OUT REFERS TO A PIN.

Figure 9. Logic Diagram 1

Register 89h). The open-drain RSELOUT output is IN1S OUT1 software controlled and/or inverted through the STATUS INVOUT1 IN1C register and CNFGA register (Table 02h, Register 88h). External pullup resistors must be provided on OUT1 and IN1 RSELOUT to realize high logic levels. INVRSOUT RSELOUT TXF1, TXF2, TXFOUT, TXD1, TXD2, RSELS TXDOUT1, TXDOUT2 RSELC TXDOUT1 and TXDOUT2 are generated from a com- RSEL bination of TXF1, TXF2, TXD1, TXD2, and the internal = PINS signals FETG1 and FETG2 (Table 02h, Register 8Ah). A software control identical to TXD1 and TXD2 is also avail- Figure 10. Logic Diagram 2 able (TXDC1 and TXDC2, Lower Memory, Register 6Eh). A TXD1 or TXD2 pulse is internally extended (TXDEXT) Digital I/O Pins by time tINITR1 to inhibit the latching of low alarms and Six digital input pins and five digital output pins are pro- warnings related to the APC loop to allow for the loop to vided for monitoring and control. stabilize. The nonlatching alarms and warnings are TXP IN1, RSEL, OUT1, RSELOUT LO, BMON1 LO, BMON2 LO, PMON1 LO, and PMON2 Digital input pins IN1 and RSEL primarily serve to meet LO. In addition, TXP LO is disabled from creating FETG. the rate-select requirements of SFP and SFP+. They See the Transmit Fault (TXFOUT) Output section for a can also serve as general-purpose inputs. OUT1 and detailed explanation of TXFOUT. As shown in Figure 9, RSELOUT are driven by a combination of the IN1, RSEL, the same signals and faults can also be used to gener- and logic dictated by control registers in the EEPROM ate the internal signal FETG. FETG is used to send a fast (see Figure 10). The levels of IN1 and RSEL can be “turn-off” command to the laser driver. The intended use read from the STATUS register (Lower Memory, Register is a direct connection to the laser driver’s TXD1, TXD2 6Eh). The open-drain output OUT1 can be controlled input if this is desired. When VCC < POA, TXDOUT1 and and/or inverted using the CNFGB register (Table 02h, TXDOUT2 are high impedance.

18 ______SFP Controller with Dual LDD Interface DS1876

DETECTION OF TXFOUT FAULT

TXFOUT

Figure 11a. TXFOUT Nonlatched Operation

DETECTION OF TXFOUT FAULT

TXD_ OR TXFOUT RESET

TXFOUT

Figure 11b. TXFOUT Latched Operation

Transmit Fault (TXFOUT) Output START Condition: A START condition is generated TXFOUT can be triggered by all alarms, warnings, QTs, by the master to initiate a new data transfer with a TXD1, TXD2, TXF1, and TXF2 (see Figure 9). The six slave. Transitioning SDA from high to low while SCL ADC alarms and warnings are controlled by enable bits remains high generates a START condition. See (Table 01h/05h, Registers F8h and FCh). See Figures Figure 12 for applicable timing. 11a and 11b for nonlatched and latched operation for STOP Condition: A STOP condition is generated TXFOUT. The CNFGB register (Table 02h, Register 89h) by the master to end a data transfer with a slave. controls the latching of the alarms. Transitioning SDA from low to high while SCL remains Die Identification high generates a STOP condition. See Figure 12 for The DS1876 has an ID hardcoded in its memory. Two applicable timing. registers (Table 02h, Registers 86h-87h) are assigned Repeated START Condition: The master can use for this feature. Register 86h reads 76h to identify the a repeated START condition at the end of one data part as the DS1876; Register 87h reads the present transfer to indicate that it will immediately initiate a device version. new data transfer following the current one. Repeated STARTs are commonly used during read operations I2C Communication to identify a specific memory address to begin a data I2C Definitions transfer. A repeated START condition is issued identi- The following terminology is commonly used to describe cally to a normal START condition. See Figure 12 for I2C data transfers. applicable timing. Master Device: The master device controls the slave Bit Write: Transitions of SDA must occur during the devices on the bus. The master device generates SCL low state of SCL. The data on SDA must remain valid clock pulses and START and STOP conditions. and unchanged during the entire high pulse of SCL plus the setup and hold time requirements (Figure 12). Slave Devices: Slave devices send and receive data Data is shifted into the device during the rising edge at the master’s request. of the SCL. Bus Idle or Not Busy: Time between STOP and Bit Read: At the end of a write operation, the master START conditions when both SDA and SCL are inac- must release the SDA bus line for the proper amount tive and in their logic-high states. of setup time (Figure 12) before the next rising edge

______19 SFP Controller with Dual LDD Interface

of SCL during a bit read. The device shifts out each bit read definition, and the master transmits an ACK bit of data on SDA at the falling edge of the previous using the bit write definition to receive additional data SCL pulse and the data bit is valid at the rising edge bytes. The master must NACK the last byte read to of the current SCL pulse. Remember that the master terminate communication so the slave returns control generates all SCL clock pulses, including when it is of SDA to the master. reading bits from the slave. Slave Address Byte: Each slave on the I2C bus

DS1876 Acknowledgement (ACK and NACK): An acknowl- responds to a slave address byte sent immediately edgement (ACK) or not-acknowledge (NACK) is following a START condition. The slave address byte always the 9th bit transmitted during a byte transfer. contains the slave address in the most significant 7 bits The device receiving data (the master during a read and the R/W bit in the least significant bit. or the slave during a write operation) performs an ACK The DS1876 responds to three slave addresses. The by transmitting a zero during the 9th bit. A device per- auxiliary memory always responds to a fixed I2C slave forms a NACK by transmitting a one during the 9th bit. address, A0h. (If the main device’s slave address Timing (Figure 12) for the ACK and NACK is identical is programmed to be A0h, access to the auxiliary to all other bit writes. An ACK is the acknowledgment memory is disabled.) The Lower Memory and Tables that the device is properly receiving data. A NACK is 00h–06h respond to I2C slave addresses whose lower used to terminate a read sequence or as an indication 3 bits are configurable (A0h–AEh, B0h-BEh) using the that the device is not receiving data. DEVICE ADDRESS byte (Table 02h, Register 8Bh). The Byte Write: A byte write consists of 8 bits of informa- user also must set the ASEL bit (Table 02h, Register tion transferred from the master to the slave (most 88h) for this address to be active. By writing the cor- significant bit first) plus a 1-bit acknowledgement from rect slave address with R/W = 0, the master indicates the slave to the master. The 8 bits transmitted by the it writes data to the slave. If R/W = 1, the master reads master are done according to the bit write definition data from the slave. If an incorrect slave address is and the acknowledgement is read using the bit read written, the DS1876 assumes the master is communi- definition. cating with another I2C device and ignores the com- Byte Read: A byte read is an 8-bit information transfer munications until the next START condition is sent. from the slave to the master plus a 1-bit ACK or NACK Memory Address: During an I2C write operation from the master to the slave. The 8 bits of information to the DS1876, the master must transmit a memory that are transferred (most significant bit first) from the address to identify the memory location where the slave to the master are read by the master using the slave is to store the data. The memory address is

SDA

tBUF

tF tSP t tLOW HD:STA

SCL

tHIGH tSU:STA tHD:STA tR tSU:STO

tHD:DAT tSU:DAT STOP START REPEATED START

NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).

Figure 12. I2C Timing

20 ______SFP Controller with Dual LDD Interface DS1876 always the second byte transmitted during a write For example: A 3-byte write starts at address 06h and operation following the slave address byte. writes three data bytes (11h, 22h, and 33h) to three “consecutive” addresses. The result is that addresses I2C Protocol 06h and 07h would contain 11h and 22h, respec- See Figure 13 for an example of I2C timing. tively, and the third data byte, 33h, would be written Writing a Single Byte to a Slave: The master must to address 00h. generate a START condition, write the slave address To prevent address wrapping from occurring, the byte (R/W = 0), write the memory address, write master must send a STOP condition at the end of the byte of data, and generate a STOP condition. the page, then wait for the bus-free or EEPROM write Remember that the master must read the slave’s time to elapse. Then the master can generate a new acknowledgement during all byte write operations. START condition and write the slave address byte Writing Multiple Bytes to a Slave: To write multiple (R/W = 0) and the first memory address of the next bytes to a slave, the master generates a START condi- memory row before continuing to write data. tion, writes the slave address byte (R/W = 0), writes Acknowledge Polling: Any time a EEPROM page is the memory address, writes up to 8 data bytes, and written, the DS1876 requires the EEPROM write time generates a STOP condition. The DS1876 writes 1 to (tWR) after the STOP condition to write the contents of 8 bytes (one page or row) with a single write trans- the page to EEPROM. During the EEPROM write time, action. This is internally controlled by an address the DS1876 does not acknowledge its slave address counter that allows data to be written to consecutive because it is busy. It is possible to take advantage addresses without transmitting a memory address of that phenomenon by repeatedly addressing the before each data byte is sent. The address counter DS1876, which allows the next page to be written limits the write to one 8-byte page (one row of the as soon as the DS1876 is ready to receive the data. memory map). Attempts to write to additional pages The alternative to acknowledge polling is to wait for of memory without sending a STOP condition between maximum period of tWR to elapse before attempting pages result in the address counter wrapping around to write again to the DS1876. to the beginning of the present row.

TYPICAL I2C WRITE TRANSACTION

MSB LSB MSB LSB MSB LSB SLAVE SLAVE SLAVE START X X X X 0 0 1 R/W b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 STOP ACK ACK ACK

SLAVE READ/ REGISTER ADDRESS DATA ADDRESS* WRITE

*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY. IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED ADDRESS FOR THE MAIN MEMORY IS A0h.

EXAMPLE I2C TRANSACTIONS WITH A2h AS THE SLAVE ADDRESS

A2h BAh 00h A) SINGLE-BYTE WRITE SLAVE SLAVE SLAVE START 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 STOP -WRITE 00h TO REGISTER BAh ACK ACK ACK

A2h BAh A3h DATA B) SINGLE-BYTE READ SLAVE SLAVE REPEATED SLAVE MASTER START 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 1 0 1 0 0 0 1 1 DATA IN BAh STOP -READ REGISTER BAh ACK ACK START ACK NACK

A2h C8h 01h 75h C) TWO-BYTE WRITE SLAVE SLAVE SLAVE SLAVE -WRITE 01h AND 75h TO START 1 0 1 0 0 0 1 0 ACK 1 1 0 0 1 0 0 0 ACK 0 0 0 0 0 0 0 1 ACK 0 1 1 1 0 1 0 1 ACK STOP REGISTERS C8h AND C9h

A2h C8h A3h DATA DATA D) TWO-BYTE READ SLAVE SLAVE REPEATED SLAVE MASTER MASTER START 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 DATA IN C8h DATA IN C9h STOP -READ C8h AND C9h ACK ACK START ACK ACK NACK

Figure 13. Example I2C Timing

______21 SFP Controller with Dual LDD Interface

EEPROM Write Cycles: When EEPROM writes occur, Table 01h, A2h primarily contains user EEPROM (with the DS1876 writes the whole EEPROM memory page, PW1 level access) as well as alarm and warning enable even if only a single byte on the page was modified. bytes. Writes that do not modify all 8 bytes on the page are Table 02h, A2h/B2h is a multifunction space that con- allowed and do not corrupt the remaining bytes of tains configuration registers, scaling and offset values, memory on the same page. Because the whole page passwords, and interrupt registers as well as other mis-

DS1876 is written, bytes on the page that were not modi- cellaneous control bytes. All functions and status can be fied during the transaction are still subject to a write written and read from either A2h or B2h addresses. cycle. This can result in a whole page being worn out over time by writing a single byte repeatedly. Table 04h, A2h contains a temperature-indexed LUT for Writing a page 1 byte at a time wears the EEPROM control of the MOD1 voltage. The MOD1 LUT can be pro- out 8x faster than writing the entire page at once. The grammed in 2NC increments over the -40NC to +102NC DS1876’s EEPROM write cycles are specified in the range. This also contains a temperature-indexed LUT for Nonvolatile Memory Characteristics table. The speci- the MOD1 offsets. fication shown is at the worst-case temperature. It can Table 05h, A2h is empty by default. It can be config- handle approximately 10x that many writes at room ured to contain the alarm and warning enable bytes temperature. Writing to SRAM-shadowed EEPROM from Table 01h, Registers F8h–FFh with the MASK bit memory with SEEB = 1 does not count as a EEPROM enabled (Table 02h, Register 88h). In this case Table write cycle when evaluating the EEPROM’s estimated 01h is empty. lifetime. Table 06h, A2h contains a temperature-indexed LUT for Reading a Single Byte from a Slave: Unlike the control of the APC1 voltage. The APC1 LUT can be pro- write operation that uses the memory address byte grammed in 2NC increments over the -40NC to +102NC to define where the data is to be written, the read range. This also contains a temperature-indexed LUT for operation occurs at the present value of the memory the APC1 offsets. address counter. To read a single byte from the slave, The main device located at B2h is used for transmitter 2 the master generates a START condition, writes the control, calibration, alarms, warnings, and monitoring. slave address byte with R/W = 1, reads the data byte Lower Memory, B2h is addressed from 00h–7Fh and with a NACK to indicate the end of the transfer, and contains alarm and warning thresholds, flags, masks, generates a STOP condition. several control registers, PWE, and the table-select byte. Manipulating the Address Counter for Reads: A Table 01h, B2h contains alarm and warning enable dummy write cycle can be used to force the address bytes. pointer to a particular value. To do this, the master generates a START condition, writes the slave Table 04h, B2h contains a temperature-indexed LUT for address byte (R/W = 0), writes the memory address control of the MOD2 voltage. The MOD2 LUT can be pro- where it desires to read, generates a repeated START grammed in 2NC increments over the -40NC to +102NC condition, writes the slave address byte (R/W = 1), range. This also contains a temperature-indexed LUT for reads data with ACK or NACK as applicable, and the MOD2 offsets. generates a STOP condition. Table 05h, B2h is empty by default. It can be configured to contain the alarm and warning enable bytes Memory Organization from Table 01h, Registers F8h–FFh with the MASK bit The DS1876 features nine separate memory tables enabled (Table 02h, Register 88h). In this case Table that are internally organized into 8-byte rows. The main 01h is empty. device located at A2h is used for overall device con- Table 06h, B2h contains a temperature-indexed LUT for figuration and transmitter 1 control, calibration, alarms, control of the APC2 voltage. The APC2 LUT can be pro- warnings, and monitoring. grammed in 2NC increments over the -40NC to +102NC Lower Memory, A2h is addressed from 00h–7Fh and range. This also contains a temperature-indexed LUT for contains alarm and warning thresholds, flags, masks, the APC2 offsets. several control registers, password entry area (PWE), and the table-select byte.

22 ______SFP Controller with Dual LDD Interface DS1876

I2C ADDRESS A0h I2C ADDRESS A2h/B2h 00h 00h

LOWER MEMORY NOTE 1: IF ASEL = 0, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS A2h/B2h. IF ASEL = 1, THEN THE MAIN DEVICE I2C SLAVE ADDRESS IS DETERMINED BY THE VALUE IN TABLE 02h, REGISTER 8Bh. NOTE 2: TABLE 00h DOES NOT EXIST. NOTE 3: ALARM-ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING THE MASK BIT IN TABLE 02h, REGISTER 88h. PASSWORD ENTRY

MAIN DEVICES AT A2h AND B2h (PWE) (4 BYTES)

TABLE-SELECT BYTE 7Fh EEPROM (256 BYTES) 80h 80h 80h 80h AUXILIARY DEVICE TABLE 04h TABLE 06h TABLE 02h ALARM-ENABLE ROW TABLE 01h MOD1 (A2h) CAN BE CONFIGURED APC1 (A2h) (A2h ONLY) NONLOOKUP MOD2 (B2h) TO EXIST AT TABLE 01h APC2 (B2h) TABLE CONTROL LOOKUP TABLE OR TABLE 05h USING LOOKUP TABLE EEPROM AND (72 BYTES) MASK BIT IN TABLE 02h, (72 BYTES) (120 BYTES) CONFIGURATION C7h REGISTER 88h. C7h REGISTERS

F7h (B2h ONLY CONTAINS E0h TRANSMITTER 2- F8h ALARM- F8h F8h TABLE 05h (APC1/2, HBATH1/2, RELATED REGISTERS) MOD1/2 ENABLE ROW ALARM-ENABLE ROW TXP HI 1/2, TXP LO 1/2) OFFSET LUT OFFSET LUT FFh (8 BYTES) FFh FFh FFh (8 BYTES) FFh FFh

Figure 14. Memory Map

Auxiliary Memory (Device A0h) contains 256 bytes SEEB, is not set and these locations act as ordinary of EE memory accessible from address 00h–FFh. It is EEPROM. By setting SEEB, these locations function selected with the device address of A0h. like SRAM cells, which allow an infinite number of write See the Register Descriptions section for a more com- cycles without concern of wearing out the EEPROM. plete detail of each byte’s function, as well as for read/ This also eliminates the requirement for the EEPROM write permissions for each byte. write time, tWR. Because changes made with SEEB enabled do not affect the EEPROM, these changes are Shadowed EEPROM not retained through power cycles. The power-on value Many nonvolatile memory locations (listed within the is the last value written with SEEB disabled. This func- Register Descriptions section) are actually shadowed tion can be used to limit the number of EEPROM writes EEPROM and are controlled by the SEEB bit in Table during calibration or to change the monitor thresholds 02h, Register 80h. periodically during normal operation helping to reduce The DS1876 incorporates shadowed EEPROM memory the number of times EEPROM is written. Figure 14 shows locations for key memory addresses that can be writ- the memory map and indicates which locations are ten many times. By default the shadowed EEPROM bit, shadowed EEPROM.

______23 SFP Controller with Dual LDD Interface

Register Descriptions Memory Map Access Codes The following section provides the DS1876 register defi- The register maps show each byte/word (2 bytes) in nitions. Each register or row of registers has an access terms of its row in the memory. The first byte in the row descriptor that determines the password level required is located in memory at the row address (hexadecimal) to read or write the memory. Level 2 password is in the leftmost column. Each subsequent byte on the row intended for the module manufacture access only. Level is one/two memory locations beyond the previous byte/

DS1876 1 password allows another level of protection for items word’s address. A total of 8 bytes are present on each the end consumer wishes to protect. Many registers are row. For more information about each of these bytes, see always readable, but require password access to write. the corresponding register description. There are a few registers that cannot be read without password access. The following access codes describe each mode used by the DS1876 with factory settings for the PW_ENA and PW_ENB (Table 02h, Registers C0h– C1h) registers.

ACCESS CODE READ ACCESS WRITE ACCESS At least 1 byte/bit in the row/byte is different than the rest of the row/byte, so look at each byte/bit <0/_> separately for permissions. <1/_> Read all Write PW2 <2/_> Read all Write not applicable Write all, but the DS1876 hardware also writes to <3/_> Read all these bytes/bits <4/_> Read PW2 Write PW2 + mode_bit <5/_> Read all Write all <6/_> Read not applicable Write all <7/_> Read PW1 Write PW1 <8/_> Read PW2 Write PW2 <9/_> Read not applicable Write PW2 <10/_> Read PW2 Write not applicable <11/_> Read all Write PW1

Memory Addresses A0h, A2h, and B2h using A2h. Transmitter 2 is accessed using B2h. Many There are three separate I2C addresses in the DS1876: of the registers in A2h and B2h are shared registers. A0h, A2h, and B2h. A2h and B2h are used to configure These registers can be read and written from both A2h and monitor two transmitters. Transmitter 1 is accessed and B2h.

MEMORY CODE A2h AND B2h REGISTERS A common memory location is used for A2h and B2h device addresses. Reading or writing to these or <_/C> locations is identical, regardless of using A2h or B2h addresses. or <_/D> Different memory locations are used for A2h and B2h device addresses. Mixture of common and different memory locations for A2h and B2h device addresses. See the individual or <_/M> bytes within the row for clarification. If “M” is used on an individual byte, see the expanded bit descriptions to determine which bits are common vs. different.

24 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory Register Map

LOWER MEMORY

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

00 <1/C> THRESHOLD0 TEMP ALARM HI TEMP ALARM LO TEMP WARN HI TEMP WARN LO

08 <1/C > THRESHOLD1 VCC ALARM HI VCC ALARM LO VCC WARN HI VCC WARN LO

10 <1/D> THRESHOLD2 BMON ALARM HI BMON ALARM LO BMON WARN HI BMON WARN LO

18 <1/D> THRESHOLD3 PMON ALARM HI PMON ALARM LO PMON WARN HI PMON WARN LO 20–40 <1/C > EEPROM EE EE EE EE

48–50 <1/D > EEPROM EE EE EE EE

58 <1/C > EEPROM EE EE EE EE EE EE EE EE

60 <2/M> ADC VALUES0 TEMP VALUE VCC VALUE BMON VALUE PMON VALUE

68 <0/M> ADC VALUES1 RESERVED RESERVED RESERVED <0/M>STATUS <3/D> UPDATE

70 <5/D> ALARM/WARN ALARM3 ALARM2 ALARM1 RESERVED WARN3 RESERVED RESERVED RESERVED 78 <0/M> TABLE SELECT RESERVED RESERVED RESERVED <6/C> PWE MSW <6/C> PWE LSW <5/D> TBL SEL or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.

Table 01h Register Map

TABLE 01h

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–F7 <1/C> EEPROM EE EE EE EE EE EE EE EE

F8 <7/M>ALARM ENABLE ALARM EN3 RESERVED ALARM EN1 RESERVED WARN EN3 RESERVED RESERVED RESERVED or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different. Note: The ALARM ENABLE bytes (Registers F8h–FFh) can be configured to exist in Table 05h instead of here at Table 01h with the MASK bit (Table 02h, Register 88h). If the row is configured to exist in Table 05h, these location are empty in Table 01h.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h). These registers also allow for custom permissions.

ACCESS <0/_> <1/_> <2/_> <3/_> <4/_> <5/_> <6/_> <7/_> <8/_> <9/_> <10/_> <11/_> CODE Read All All All PW2 All N/A PW1 PW2 N/A PW2 All Access See each bit/byte All and PW2 + Write separately PW2 N/A DS1876 mode All All PW1 PW2 PW2 N/A PW1 Access Hardware bit

______25 SFP Controller with Dual LDD Interface

Table 02h Register Map

TABLE 02h (PW2)

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80 <0/C> CONFIG0 <8/C>MODE <4/C>TINDEX RESERVED RESERVED RESERVED RESERVED <10> DEVICE ID <10> DEVICE VER

DS1876 88 <8/C> CONFIG1 CNFGA CNFGB CNFGC DEVICE ADDRESS RANGING2 RANGING1 RSHIFT2 RSHIFT1

90 <8/C> SCALE0 RESERVED VCC SCALE RESERVED RESERVED

98 <8/C> SCALE1 BMON2 SCALE PMON2 SCALE BMON1 SCALE PMON1 SCALE

A0 <8/C> OFFSET0 INTERNAL TEMP OFFSET* VCC OFFSET RESERVED RESERVED

A8 <8/C> OFFSET1 BMON2 OFFSET PMON2 OFFSET BMON1 OFFSET PMON1 OFFSET B0 <9/C> PWD VALUE PW1 MSW PW1 LSW PW2 MSW PW2 LSW

B8 <8/C> THRESHOLD RESERVED HBIAS2 DAC HTXP2 DAC LTXP2 DAC RESERVED HBIAS1 DAC HTXP1 DAC LTXP1 DAC

C0 <8/C> PWD ENABLE PW_ENA PW_ENB RESERVED RESERVED RESERVED RESERVED POLARITY TBLSELPON

C8 <4/C> DAC VALUES MOD2 DAC APC2 DAC MOD1 DAC APC1 DAC

D0–FF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different. *The final result must be XORed with BB40h before writing to this register.

Table 04h Register Map

TABLE 04h (MODULATION LUT)

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–C7 <8/D> LUT4 MOD MOD MOD MOD MOD MOD MOD MOD

C8–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

MOD OFFSET MOD OFFSET MOD OFFSET MOD OFFSET MOD OFFSET MOD OFFSET MOD OFFSET MOD OFFSET F8 <8/D> MOD OFFSET LUT LUT LUT LUT LUT LUT LUT LUT or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h). These registers also allow for custom permissions.

26 ______SFP Controller with Dual LDD Interface DS1876 Table 05h Register Map

TABLE 05h

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

F8 <7/M> ALARM ENABLE ALARM EN3 RESERVED ALARM EN1 RESERVED WARN EN3 RESERVED RESERVED RESERVED or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different. Note: Table 05h is empty by default. It can be configured to contain the alarm and warning enable bytes from Table 01h, Registers F8h–FFh with the MASK bit enabled (Table 02h, Register 88h). In this case Table 01h is empty.

Table 06h Register Map

TABLE 06h (APC LUT)

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

80–C7 <8/D> LUT6 APC LUT APC LUT APC LUT APC LUT APC LUT APC LUT APC LUT APC LUT

C8–DF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY

E0 <8/D> HBATH HBATH LUT HBATH LUT HBATH LUT HBATH LUT HBATH LUT HBATH LUT HBATH LUT HBATH LUT

E8 <8/D> HTXP HTXP LUT HTXP LUT HTXP LUT HTXP LUT HTXP LUT HTXP LUT HTXP LUT HTXP LUT

F0 <8/D> LTXP LTXP LUT LTXP LUT LTXP LUT LTXP LUT LTXP LUT LTXP LUT LTXP LUT LTXP LUT

APC OFFSET APC OFFSET APC OFFSET APC OFFSET APC OFFSET APC OFFSET APC OFFSET APC OFFSET F8 <8/D> APC OFFSET LUT LUT LUT LUT LUT LUT LUT LUT or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.

Auxiliary Memory A0h Register Map

AUXILIARY MEMORY (A0h)

ROW WORD 0 WORD 1 WORD 2 WORD 3 ROW NAME (HEX) BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F

00–7F <5> AUX EE EE EE EE EE EE EE EE EE

80–FF <5> AUX EE EE EE EE EE EE EE EE EE or <_/C> = Common, or <_/D> = Different, or <_/M> = Mixture of common and different.

The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h). These registers also allow for custom permissions.

______27 SFP Controller with Dual LDD Interface

Lower Memory Register Descriptions Lower Memory, Register 00h–01h: TEMP ALARM HI Lower Memory, Register 04h–05h: TEMP WARN HI

FACTORY DEFAULT 7FFFh READ ACCESS All

DS1876 WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

00h, 04h S 26 25 24 23 22 21 20 01h, 05h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0

Temperature measurement updates above this two’s complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 02h–03h: TEMP ALARM LO Lower Memory, Register 06h–07h: TEMP WARN LO

FACTORY DEFAULT 8000h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

02h, 06h S 26 25 24 23 22 21 20 03h, 07h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0

Temperature measurement updates below this two’s complement threshold set its corresponding alarm or warning bit. Temperature measurement updates equal to or above this threshold clear its alarm or warning bit.

28 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 08h–09h: VCC ALARM HI Lower Memory, Register 0Ch–0Dh: VCC WARN HI FACTORY DEFAULT FFFFh READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

08h, 0Ch 215 214 213 212 211 210 29 28 09h, 0Dh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 0Ah–0Bh: VCC ALARM LO Lower Memory, Register 0Eh–0Fh: VCC WARN LO

FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

0Ah, 0Eh 215 214 213 212 211 210 29 28 0Bh, 0Fh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit.

______29 SFP Controller with Dual LDD Interface

Lower Memory, Register 10h–11h: BMON ALARM HI Lower Memory, Register 14h–15h: BMON WARN HI Lower Memory, Register 18h–19h: PMON ALARM HI Lower Memory, Register 1Ch–1Dh: PMON WARN HI

FACTORY DEFAULT FFFFh DS1876 READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (SEE)

10h, 14h, 215 214 213 212 211 210 29 28 18h, 1Ch 11h, 15h, 27 26 25 24 23 22 21 20 19h, 1Dh BIT 7 BIT 0

Voltage measurement updates above this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or below this threshold clear its alarm or warning bit.

Lower Memory, Register 12h–13h: BMON ALARM LO Lower Memory, Register 16h–17h: BMON WARN LO Lower Memory, Register 1Ah–1Bh: PMON ALARM LO Lower Memory, Register 1Eh–1Fh: PMON WARN LO

FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (SEE)

12h, 16h, 215 214 213 212 211 210 29 28 1Ah, 1Eh 13h, 17h, 27 26 25 24 23 22 21 20 1Bh, 1Fh BIT 7 BIT 0

Voltage measurement updates below this unsigned threshold set its corresponding alarm or warning bit. Voltage measurements equal to or above this threshold clear its alarm or warning bit.

30 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 20h–47h: EE

FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (EE)

20h–47h EE EE EE EE EE EE EE EE BIT 7 BIT 0

PW2 level access-controlled EEPROM.

Lower Memory, Register 48h–57h: EE

FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

48h–57h EE EE EE EE EE EE EE EE BIT 7 BIT 0

PW2 level access-controlled EEPROM.

Lower Memory, Register 58h–5Fh: EE

FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WLOWER) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (EE)

58h–5Fh EE EE EE EE EE EE EE EE BIT 7 BIT 0

PW2 level access-controlled EEPROM.

______31 SFP Controller with Dual LDD Interface

Lower Memory, Register 60h–61h: TEMP VALUE FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile DS1876

60h S 26 25 24 23 22 21 20 61h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0

Signed two’s complement direct-to-temperature measurement.

Lower Memory, Register 62h–63h: VCC VALUE POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

62h 215 214 213 212 211 210 29 28 63h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Left-justified unsigned voltage measurement.

32 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 64h–65h: BMON VALUE Lower Memory, Register 66h–67h: PMON VALUE POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Volatile

64h, 66h 215 214 213 212 211 210 29 28 65h, 67h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Left-justified unsigned voltage measurement.

Lower Memory, Register 68h–6Dh: RESERVED

POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

68h, 6Dh 0 0 0 0 0 0 0 0 BIT 7 BIT 0

These registers are reserved. The value when read is 00h.

______33 SFP Controller with Dual LDD Interface

Lower Memory, Register 6Eh: STATUS POWER-ON VALUE X0XX 0XXXb READ ACCESS All WRITE ACCESS See below A2h AND B2h MEMORY Mixture of common memory locations and different memory locations (see below) MEMORY TYPE Volatile DS1876

Write Access N/A All N/A All All N/A N/A N/A 6Eh TXDS TXDC IN1S RSELS RSELC TXFS RAM RDYB BIT 7 BIT 0

TXDS1 [A2h]: TXD1 status bit. Reflects the logic state of the TXD1 pin (read-only). 0 = TXD1 pin is logic-low. 1 = TXD1 pin is logic-high. BIT 7 TXDS2 [B2h]: TXD2 status bit. Reflects the logic state of the TXD2 pin (read-only). 0 = TXD2 pin is logic-low. 1 = TXD2 pin is logic-high. TXDC1 [A2h]: TXD1 software control bit. This bit allows for software control that is identical to the TXD1 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further information. Its value is wire-ORed with the logic value of the TXD1 pin (writable by all users). 0 = (default) 1 = Forces the device into a TXD1 state regardless of the value of the TXD1 pin. BIT 6 TXDC2 [B2h]: TXD2 software control bit. This bit allows for software control that is identical to the TXD2 pin. See the DACs as a Function of Transmit Disable (TXD1, TXD2) section for further information. Its value is wire-ORed with the logic value of the TXD2 pin (writable by all users). 0 = (default) 1 = Forces the device into a TXD2 state regardless of the value of the TXD2 pin. IN1S [A2h or B2h]: IN1 status bit. Reflects the logic state of the IN1 pin (read-only). BIT 5 0 = IN1 pin is logic-low. 1 = IN1 pin is logic-high. RSELS [A2h or B2h]: RSEL status bit. Reflects the logic state of the RSEL pin (read-only). BIT 4 0 = RSEL pin is logic-low. 1 = RSEL pin is logic-high. RSELC [A2h or B2h]: RSEL software control bit. This bit allows for software control that is identical to the RSEL pin. Its value is wire-ORed with the logic value of the RSEL pin to create the BIT 3 RSELOUT pin’s logic value (writable by all users). 0 = (default) 1 = Forces the device into a RSEL state regardless of the value of the RSEL pin. TXFS1 [A2h]: Reflects state of the TXF1 pin (read-only). 0 = TXF1 pin is low. 1 = TXF1 pin is high. BIT 2 TXFS2 [B2h]: Reflects the state of the TXF2 pin (read-only). 0 = TXF2 pin is low. 1 = TXF2 pin is high. RAM1 [A2h]: Volatile memory location. BIT 1 RAM2 [B2h]: Volatile memory location. RDYB [A2h or B2h]: Ready bar. BIT 0 0 = VCC is above POA. 1 = VCC is below POA and/or too low to communicate over the I2C bus.

34 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 6Fh: UPDATE POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All and DS1876 hardware A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Volatile

TEMP BMON PMON 6Fh VCC RDY RESERVED RESERVED RESERVED RESERVED RDY RDY RDY BIT 7 BIT 0

TEMP RDY, VCC RDY, BMON RDY, PMON RDY: Update of completed conversions. At power-on, BITS 7:4 these bits are cleared and are set as each conversion is completed. These bits can be cleared so that a completion of a new conversion is verified. BITS 3:0 RESERVED

______35 SFP Controller with Dual LDD Interface

Lower Memory, Register 70h: ALARM3 POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Different A2h and B2h memory locations

DS1876 MEMORY TYPE Volatile

70h TEMP HI TEMP LO VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 7 BIT 0

TEMP HI: High alarm status for temperature measurement. BIT 7 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low alarm status for temperature measurement. BIT 6 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting.

VCC HI: High alarm status for VCC measurement. BIT 5 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.

VCC LO: Low alarm status for VCC measurement. This bit is set when the VCC supply is below the POA trip point value. It clears itself when a VCC measurement is completed and the value is BIT 4 above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. BMON HI: High alarm status for BMON measurement. BIT 3 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BMON LO: Low alarm status for BMON measurement. BIT 2 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. PMON HI: High alarm status for PMON measurement. BIT 1 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. PMON LO: Low alarm status for PMON measurement. BIT 0 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting.

36 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Register 71h: ALARM2 POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Mixed A2h and B2h memory locations MEMORY TYPE Volatile

71h RESERVED RESERVED RESERVED RESERVED RESERVED TXFOUTS FETG TXFINT BIT 7 BIT 0

BITS 7:3 RESERVED TXFOUTS: TXFOUT status. Indicates the state the open-drain output is attempting to achieve. BIT 2 0 = TXFOUT is pulling low. 1 = TXFOUT is high impedance. FETG: Status of internal signal FETG. The FETG signal is part of the internal shutdown logic. BIT 1 0 = (default) FETG is low. 1 = FETG is high. TXFINT: TXF interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with BIT 0 their corresponding enable bits, plus the wire-ORed logic of HBAL, TXP HI, and TXP LO. The enable bits are found in Table 01h/05h, Registers F8h–FFh.

Lower Memory, Register 72h: ALARM1 POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Volatile

72h RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO BIT 7 BIT 0

BITS 7:4, 2 RESERVED HBAL: High bias alarm status; fast comparison. A TXD event clears this alarm. BIT 3 0 = (default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. TXP HI: High alarm status TXP; fast comparison. A TXD event clears this alarm. BIT 1 0 = (default) Last comparison was below threshold setting. 1 = Last comparison was above threshold setting. TXP LO: Low alarm status TXP; fast comparison. A TXD event clears this alarm. BIT 0 0 = (default) Last comparison was above threshold setting. 1 = Last comparison was below threshold setting.

______37 SFP Controller with Dual LDD Interface

Lower Memory, Register 73h: RESERVED POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A DS1876

This register is reserved.

Lower Memory, Register 74h: WARN3 POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Volatile

74h TEMP HI TEMP LO VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 7 BIT 0

TEMP HI: High warning status for temperature measurement. BIT 7 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. TEMP LO: Low warning status for temperature measurement. BIT 6 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. VCC HI: High warning status for VCC measurement. BIT 5 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.

VCC LO: Low warning status for VCC measurement. This bit is set when the VCC supply is below the POA trip-point value. It clears itself when a VCC measurement is completed and the value is BIT 4 above the low threshold. 0 = Last measurement was equal to or above threshold setting. 1 = (default) Last measurement was below threshold setting. BMON HI: High warning status for BMON measurement. BIT 3 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BMON LO: Low warning status for BMON measurement. BIT 2 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting. PMON HI: High warning status for PMON measurement. BIT 1 0 = (default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. PMON LO: Low warning status for PMON measurement. BIT 0 0 = (default) Last measurement was equal to or above threshold setting. 1 = Last measurement was below threshold setting.

38 ______SFP Controller with Dual LDD Interface DS1876 Lower Memory, Registers 75h–7Ah: RESERVED MEMORY POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

These registers are reserved. The value when read is 00h.

Lower Memory, Registers 7Bh–7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE FFFF FFFFh READ ACCESS N/A WRITE ACCESS All A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

7Bh 231 230 229 228 227 226 225 224 7Ch 223 222 221 220 219 218 217 216 7Dh 215 214 213 212 211 210 29 28 7Eh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

There are two passwords for the DS1876. Each password is 4 bytes long. The lower level password (PW1) has all the access of a normal user plus those made available with PW1. The higher level password (PW2) has all the access of PW1 plus those made available with PW2. The values of the passwords reside in EEPROM inside PW2 memory. At power-up, all PWE bits are set to 1. All reads at this location are 0.

______39 SFP Controller with Dual LDD Interface

Lower Memory, Register 7Fh: TABLE SELECT (TBL SEL)

POWER-ON VALUE TBLSELPON (Table 02h, Register C7h) READ ACCESS All WRITE ACCESS All A2h AND B2h MEMORY Different A2h and B2h memory locations

DS1876 MEMORY TYPE Volatile

7Fh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The upper memory tables of the DS1876 are accessible by writing the desired table value in this register. The power-on value of this register is defined by the value written to TBLSELPON (Table 02h, Register C7h).

Table 01h Register Descriptions Table 01h, Register 80h–F7h: EEPROM

POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A) WRITE ACCESS PW2 or (PW1 and RWTBL1A) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (EE)

80h–F7h EE EE EE EE EE EE EE EE BIT 7 BIT 0

EEPROM for PW1 and/or PW2 level access.

40 ______SFP Controller with Dual LDD Interface DS1876 Table 01h, Register F8h: ALARM EN3 POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) Mixture of common memory locations and different memory locations (see the A2h AND B2h MEMORY descriptions below) MEMORY TYPE Nonvolatile (SEE)

F8h TEMP HI TEMP LO VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 7 BIT 0

Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. TEMP HI [A2h or B2h]: BIT 7 0 = Disables interrupt from TEMP HI alarm. 1 = Enables interrupt from TEMP HI alarm. TEMP LO [A2h or B2h]: BIT 6 0 = Disables interrupt from TEMP LO alarm. 1 = Enables interrupt from TEMP LO alarm. VCC HI [A2h or B2h]: BIT 5 0 = Disables interrupt from VCC HI alarm. 1 = Enables interrupt from VCC HI alarm. VCC LO [A2h or B2h]: BIT 4 0 = Disables interrupt from VCC LO alarm. 1 = Enables interrupt from VCC LO alarm. BMON1 HI [A2h]: 0 = Disables interrupt from BMON1 HI alarm. 1 = Enables interrupt from BMON1 HI alarm. BIT 3 BMON2 HI [B2h]: 0 = Disables interrupt from BMON2 HI alarm. 1 = Enables interrupt from BMON2 HI alarm. BMON1 LO [A2h]: 0 = Disables interrupt from BMON1 LO alarm. 1 = Enables interrupt from BMON1 LO alarm. BIT 2 BMON2 LO [B2h]: 0 = Disables interrupt from BMON2 LO alarm. 1 = Enables interrupt from BMON2 LO alarm. PMON1 HI [A2h]: 0 = Disables interrupt from PMON1 HI alarm. 1 = Enables interrupt from PMON1 HI alarm. BIT 1 PMON2 HI [B2h]: 0 = Disables interrupt from PMON2 HI alarm. 1 = Enables interrupt from PMON2 HI alarm. PMON1 LO [A2h]: 0 = Disables interrupt from PMON1 LO alarm. 1 = Enables interrupt from PMON1 LO alarm. BIT 0 PMON2 LO [B2h]: 0 = Disables interrupt from PMON2 LO alarm. 1 = Enables interrupt from PMON2 LO alarm.

______41 SFP Controller with Dual LDD Interface

Table 01h, Register F9h: RESERVED POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A DS1876

This register is reserved.

Table 01h, Register FAh: ALARM EN1 POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (SEE)

FAh RESERVED RESERVED RESERVED RESERVED HBAL RESERVED TXP HI TXP LO BIT 7 BIT 0

Layout is identical to ALARM1 in Lower Memory, Register 72h. Enables alarms to create internal signal FETG (see Figure 9). The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. BITS 7:4, 2 RESERVED HBAL: Enables alarm to create internal signal FETG. BIT 3 0 = Disables interrupt from HBAL alarm. 1 = Enables interrupt from HBAL alarm. TXP HI: Enables alarm to create internal signal FETG. BIT 1 0 = Disables interrupt from TXP HI alarm. 1 = Enables interrupt from TXP HI alarm. TXP LO: Enables alarm to create internal signal FETG. BIT 0 0 = Disables interrupt from TXP LO alarm. 1 = Enables interrupt from TXP LO alarm.

Table 01h, Register FBh: RESERVED POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

This register is reserved.

42 ______SFP Controller with Dual LDD Interface DS1876 Table 01h, Register FCh: WARN EN3 POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) Mixture of common memory locations and different memory locations (see the bit A2h AND B2h MEMORY descriptions) MEMORY TYPE Nonvolatile (SEE)

FCh TEMP HI TEMP LO VCC HI VCC LO BMON HI BMON LO PMON HI PMON LO BIT 7 BIT 0

Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h. TEMP HI [A2h or B2h]: BIT 7 0 = Disables interrupt from TEMP HI warning. 1 = Enables interrupt from TEMP HI warning. TEMP LO [A2h or B2h]: BIT 6 0 = Disables interrupt from TEMP LO warning. 1 = Enables interrupt from TEMP LO warning. VCC HI [A2h or B2h]: BIT 5 0 = Disables interrupt from VCC HI warning. 1 = Enables interrupt from VCC HI warning. VCC LO [A2h or B2h]: BIT 4 0 = Disables interrupt from VCC LO warning. 1 = Enables interrupt from VCC LO warning. BMON1 HI [A2h]: 0 = Disables interrupt from BMON1 HI warning. 1 = Enables interrupt from BMON1 HI warning. BIT 3 BMON1 HI [B2h]: 0 = Disables interrupt from BMON2 HI warning. 1 = Enables interrupt from BMON2 HI warning. BMON1 LO [A2h]: 0 = Disables interrupt from BMON1 LO warning. 1 = Enables interrupt from BMON1 LO warning. BIT 2 BMON2 LO [B2h]: 0 = Disables interrupt from BMON2 LO warning. 1 = Enables interrupt from BMON2 LO warning. PMON1 HI [A2h]: 0 = Disables interrupt from PMON1 HI warning. 1 = Enables interrupt from PMON1 HI warning. BIT 1 PMON2 HI [B2h]: 0 = Disables interrupt from PMON2 HI warning. 1 = Enables interrupt from PMON2 HI warning. PMON1 LO [A2h]: 0 = Disables interrupt from PMON1 LO warning. 1 = Enables interrupt from PMON1 LO warning. BIT 0 PMON2 LO [B2h]: 0 = Disables interrupt from PMON2 LO warning. 1 = Enables interrupt from PMON2 LO warning.

______43 SFP Controller with Dual LDD Interface

Table 01h, Register FDh–FFh: RESERVED POWER-ON VALUE READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A DS1876

These registers are reserved.

Table 02h Register Descriptions Table 02h, Register 80h: MODE

POWER-ON VALUE 7Fh READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

80h SEEB MOD2EN QT2EN APC2EN AEN MOD1EN QT1EN APC1EN BIT 7 BIT 0

SEEB: 0 = (default) Enables EEPROM writes to SEE bytes. BIT 7 1 = Disables EEPROM writes to SEE bytes during configuration, so that the configuration of the part is not delayed by the EE cycle time. Once the values are known, write this bit to a 0 and write the SEE locations again for data to be written to the EEPROM. MOD2EN: 0 = MOD2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to BIT 6 interactively test their modules by writing the values for MOD2. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for MOD2 DAC. QT2EN: 0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 2 are writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing to the QT thresholds. BIT 5 The thresholds are updated with the new values at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT QTs for transmitter 2. APC2EN: 0 = APC2 DAC is writable by the user and the LUT recalls are disabled. This allows the user to BIT 4 interactively test their modules by writing the values for APC2. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for APC2 DAC. AEN: 0 = The temperature-calculated index value TINDEX is writable by the user and the updates of calculated indexes are disabled. This allows the user to interactively test their modules by BIT 3 controlling the indexing for the LUTs. The recalled values from the LUTs appear in the DAC registers after the next completion of a temperature conversion. 1 = (default) The temperature-calculated index value TINDEX is used to control the LUTs.

44 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 80h: MODE (continued)

MOD1EN: 0 = MOD1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to BIT 2 interactively test their modules by writing the values for MOD1. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for MOD1 DAC. QT1EN: 0 = QTs (HBIAS, TXP HI, TXP LO) for transmitter 1 are writable by the user and the LUT recalls are disabled. This allows the user to interactively test their modules by writing to the QT thresholds. BIT 1 The thresholds are updated with the new values at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT QTs for transmitter 1. APC1EN: 0 = APC1 DAC is writable by the user and the LUT recalls are disabled. This allows the user to BIT 0 interactively test their modules by writing the values for APC1. The output is updated with the new value at the end of the write cycle. The I2C STOP condition is the end of the write cycle. 1 = (default) Enables automatic control of the LUT for APC1 DAC.

Table 02h, Register 81h: TEMPERATURE INDEX (TINDEX)

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL2 and AEN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

81h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h and 06h. Temperature measurements below -40NC or above +102NC are clamped to 80h and C7h, respectively. The calculation of TINDEX is as follows: Temp_Value+ 40 ° C TINDEX= + 80h 2° C For the temperature-indexed LUTs (2NC), the index used during the lookup function for each table is as follows:

Table 04h (MOD) 1 TINDEX6 TINDEX5 TINDEX4 TINDEX3 TINDEX2 TINDEX1 TINDEX0 Table 06h (APC) 1 TINDEX6 TINDEX5 TINDEX4 TINDEX3 TINDEX2 TINDEX1 TINDEX0

For the 8-position LUT tables, the following table shows the lookup function: TINDEX 1000_0xxx 1001_0xxx 1001_1xxx 1010_0xxx 1010_1xxx 1011_0xxx 1011_1xxx 11xx_xxxx BYTE F8 F9 FA FB FC FD FE FF TEMP (NC) < -8 -8 to +8 +8 to +24 +24 to +40 +40 to +56 +56 to +72 +72 to +88 R 88

______45 SFP Controller with Dual LDD Interface

Table 02h, Register 82h–85h: RESERVED FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A DS1876

These registers are reserved.

Table 02h, Register 86h: DEVICE ID FACTORY DEFAULT 76h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS N/A MEMORY TYPE ROM

86h 0 1 1 1 0 1 1 0 BIT 7 BIT 0

Hardwired connections to show the device ID.

Table 02h, Register 87h: DEVICE VER

FACTORY DEFAULT DEVICE VERSION READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS N/A MEMORY TYPE ROM

87h DEVICE VERSION BIT 7 BIT 0

Hardwired connections to show the device version.

46 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 88h: CNFGA FACTORY DEFAULT C0h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

88h QTHEXT2 QTHEXT1 RESERVED ASEL MASK INVRSOUT INVTXFOUT2 INVTXFOUT1 BIT 7 BIT 0

QTHEXT2: QT high extension for transmitter 2. 0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 2 immediately create FETG. BIT 7 1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 2 do not create FETG until the timeout of the TXDEXT time interval.

QTHEXT1: QT high extension for transmitter 1. 0 = Disabled. TXP HI and HBIAS QT alarms of transmitter 1 immediately create FETG. BIT 6 1 = (default) Enabled. TXP HI and HBIAS QT alarms of transmitter 1 do not create FETG until the timeout of the TXDEXT time interval. BIT 5 RESERVED ASEL: Address select. 0 = (default) Device address is A2h for transmitter 1 and B2h for transmitter 2. BIT 4 1 = The DEVICE ADDRESS register (Table 02h, Register 8Bh) is used to determine the main device address.

MASK: 0 = (default) Alarm-enable row exists at Table 01h, Registers F8h–FFh. Table 05h, Registers F8h– BIT 3 FFh are empty. 1 = Alarm-enable row exists at Table 05h, Registers F8h–FFh. Table 01h, Registers F8h–FFh are empty.

INVRSOUT: Allow for inversion of the RSELOUT pin (see Figure 10). BIT 2 0 = (default) RSELOUT is not inverted. 1 = RSELOUT is inverted. INVTXFOUT2: Allow for inversion of signal driven by the TXF2 input pin. BIT 1 0 = (default) TXF2 signal is not inverted. 1 = TXF2 signal is inverted. INVTXFOUT1: Allow for inversion of signal driven by the TXF1 input pin. BIT 0 0 = (default) TXF1 signal is not inverted. 1 = TXF1 signal is inverted.

______47 SFP Controller with Dual LDD Interface

Table 02h, Register 89h: CNFGB FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE) DS1876

89h IN1C INVOUT1 ALATCH2 QTLATCH2 WLATCH2 ALATCH1 QTLATCH1 WLATCH1 BIT 7 BIT 0

IN1C: IN1 software control bit (see Figure 10). BIT 7 0 = IN1 pin’s logic controls OUT1 pin. 1 = OUT1 is active (bit 6 defines the polarity). INVOUT1: Inverts the active state for OUT1 (see Figure 10). BIT 6 0 = Noninverted. 1 = Inverted.

ALATCH2: ADC alarm’s comparison latch for transmitter 2. Latches alarms in Lower Memory, Registers 70h–71h. BIT 5 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set.

QTLATCH2: QT’s comparison latch for transmitter 2. Latches QT alarms in Lower Memory, Registers 72h–73h and 76h. BIT 4 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set.

WLATCH2: ADC warning’s comparison latch for transmitter 2. Latches warnings in Lower Memory, Registers 74h–75h. BIT 3 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set.

ALATCH1: ADC alarm’s comparison latch for transmitter 1. Latches alarms in Lower Memory, Registers 70h–71h. BIT 2 0 = ADC alarm and flags reflect the status of the last comparison. 1 = ADC alarm flags remain set.

QTLATCH1: QT’s comparison latch for transmitter 1. Latches QT alarms in Lower Memory, Registers 72h–73h and 76h. BIT 1 0 = QT alarm and warning flags reflect the status of the last comparison. 1 = QT alarm and warning flags remain set.

WLATCH1: ADC warning’s comparison latch for transmitter 1. Latches warnings in Lower Memory, Registers 74h–75h. BIT 0 0 = ADC warning flags reflect the status of the last comparison. 1 = ADC warning flags remain set.

48 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 8Ah: CNFGC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

8Ah TXDFG2 TXDFLT2 TXDIO2 TXDFG1 TXDFLT1 TXDIO1 RESERVED RESERVED BIT 7 BIT 0

TXDFG2: See Figure 9. BIT 7 0 = FETG2, an internal signal, has no effect on TXDOUT2. 1 = FETG2 is enabled and ORed with other possible signals to create TXDOUT2. TXDFLT2: See Figure 9. BIT 6 0 = TXF2 pin has no effect on TXDOUT2. 1 = TXF2 pin is enabled and ORed with other possible signals to create TXDOUT2. TXDIO2: See Figure 9. BIT 5 0 = (default) TXD2 input signal is enabled and ORed with other possible signals to create TXDOUT2. 1 = TXD2 input signal has no effect on TXDOUT2. TXDFG1: See Figure 9. BIT 4 0 = FETG1, an internal signal, has no effect on TXDOUT1. 1 = FETG1 is enabled and ORed with other possible signals to create TXDOUT1. TXDFLT1: See Figure 9. BIT 3 0 = TXF1 pin has no effect on TXDOUT1. 1 = TXF1 pin is enabled and ORed with other possible signals to create TXDOUT1. TXDIO1: See Figure 9. BIT 2 0 = (default) TXD1 input signal is enabled and ORed with other possible signals to create TXDOUT1. 1 = TXD1 input signal has no effect on TXDOUT1. BITS 1:0 RESERVED

Table 02h, Register 8Bh: DEVICE ADDRESS

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

8Bh SEE SEE SEE SEE 23 22 21 SEE BIT 7 BIT 0

This value becomes the I2C slave address for the main memory when the ASEL bit (Table 02h, Register 88h) is set. If A0h is programmed to this register, the auxiliary memory is disabled. For example, writing xxxx_010x makes the main device addresses A4h and B4h.

______49 SFP Controller with Dual LDD Interface

Table 02h, Register 8Ch: RANGING2 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE) DS1876

8Ch RESERVED HBIAS22 HBIAS21 HBIAS20 RESERVED TXP22 TXP21 TXP20 BIT 7 BIT 0

The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON2. The lower nibble of this byte controls the full-scale range for the QT monitoring for PMON2.

BITS 7, 3 RESERVED (default = 0) HBIAS2[2:0]: HBIAS2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for BMON2. Default is 000b and creates a full scale of 1.25V. HBIAS2[2:0] % OF 1.25V FS VOLTAGE (V) 000b 100.00 1.250 001b 80.03 1.000 BITS 6:4 010b 66.71 0.834 011b 50.07 0.626 100b 40.08 0.501 101b 33.41 0.418 110b 28.65 0.358 111b 25.08 0.314 TXP2[2:0]: TXP2 full-scale ranging: 3-bit value to select the full-scale comparison voltage for PMON2. Default is 000b and creates a full scale of 2.5V. TXP2[2:0] % OF 2.5V FS VOLTAGE (V) 000b 100.00 2.507 001b 80.03 2.006 BITS 2:0 010b 66.71 1.672 011b 50.07 1.255 100b 40.08 1.005 101b 33.41 0.838 110b 28.65 0.718 111b 25.08 0.629

50 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 8Dh: RANGING1 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

8Dh RESERVED HBIAS12 HBIAS11 HBIAS10 RESERVED TXP12 TXP11 TXP10 BIT 7 BIT 0

The upper nibble of this byte controls the full-scale range of the QT monitoring for BMON1. The lower nibble of this byte controls the full-scale range for the QT monitoring for PMON1.

BITS 7, 3 RESERVED (default = 0) HBIAS1[2:0]: HBIAS1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for BMON1. Default is 000b and creates a full scale of 1.25V. HBIAS1[2:0] % OF 1.25V FS VOLTAGE (V) 000b 100.00 1.250 001b 80.03 1.000 BITS 6:4 010b 66.71 0.834 011b 50.07 0.626 100b 40.08 0.501 101b 33.41 0.418 110b 28.65 0.358 111b 25.08 0.314 TXP1[2:0]: TXP1 full-scale ranging: 3-bit value to select the full-scale comparison voltage for PMON1. Default is 000b and creates a full scale of 2.5V. TXP1[2:0] % OF 2.5V FS VOLTAGE (V) 000b 100.00 2.507 001b 80.03 2.006 BITS 2:0 010b 66.71 1.672 011b 50.07 1.255 100b 40.08 1.005 101b 33.41 0.838 110b 28.65 0.718 111b 25.08 0.629

______51 SFP Controller with Dual LDD Interface

Table 02h, Register 8Eh: RIGHT-SHIFT2 (RSHIFT2) FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE) DS1876

8Eh RESERVED BMON22 BMON21 BMON20 RESERVED PMON22 PMON21 PMON20 BIT 7 BIT 0

Allows for right-shifting the final answer of BMON2 and PMON2 voltage measurements. This allows for scaling the measurement to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.

Table 02h, Register 8Fh: RIGHT-SHIFT1 (RSHIFT1) FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

8Fh RESERVED BMON12 BMON11 BMON10 RESERVED PMON12 PMON11 PMON10 BIT 7 BIT 0

Allows for right-shifting the final answer of BMON1 and PMON1 voltage measurements. This allows for scaling the measurements to the smallest full-scale voltage and then right-shifting the final result so the reading is weighted to the correct LSB.

Table 02h, Register 90h–91h: RESERVED

FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

These registers are reserved.

52 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register 92h–93h: VCC SCALE Table 02h, Register 94h–97h: RESERVED Table 02h, RegisteR 98h–99h: BMON2 SCALE Table 02h, Register 9Ah–9Bh: PMON2 SCALE Table 02h, Register 9Ch–9Dh: BMON1 SCALE Table 02h, Register 9Eh–9Fh: PMON1 SCALE

FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

92h, 94h, 96h, 98h, 215 214 213 212 211 210 29 28 9Ah, 9Ch, 9Eh

93h, 95h, 97h, 99h, 27 26 25 24 23 22 21 20 9Bh, 9Dh, 9Fh BIT 7 BIT 0

Controls the scaling or gain of the full-scale voltage measurements. The factory-calibrated value produces an FS voltage of 6.5536V for VCC and 2.5V for BMON2, PMON2, BMON1, and PMON1.

Table 02h, Register A0h–A1h: INTERNAL TEMP OFFSET

FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

A0h S 28 27 26 25 24 23 22 A1h 21 20 2-1 2-2 2-3 2-4 2-5 2-6 BIT 7 BIT 0

Allows for offset control of temperature measurement if desired. The final result must be XORed with BB40h before writing to this register. Factory calibration contains the desired value for a reading in degrees Celsius.

______53 SFP Controller with Dual LDD Interface

Table 02h, Register A2h–A3h: VCC OFFSET Table 02h, Register A4h–A7h: RESERVED Table 02h, Register A8h–A9h: BMON2 OFFSET Table 02h, Register AAh–ABh: PMON2 OFFSET Table 02h, Register ACh–ADh: BMON1 OFFSET

DS1876 Table 02h, Register AEh–AFh: PMON1 OFFSET

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

A2h, A4h, A6h, A8h, S S 215 214 213 212 211 210 AAh, ACh, AEh

A3h, A5h, A7h, A9h, 29 28 27 26 25 24 23 22 ABh, ADh, AFh BIT 7 BIT 0

Allows for offset control of these voltage measurements if desired. This number is two’s complement.

Table 02h, Register B0h–B3h: PW1

FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 or (PW1 and WPW1) MEMORY TYPE Nonvolatile (SEE)

B0h 231 230 229 228 227 226 225 224 B1h 223 222 221 220 219 218 217 216 B2h 215 214 213 212 211 210 29 28 B3h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The PWE value is compared against the value written to this location to enable PW1 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW1 access on power-on without writing the password entry. All reads of this register are 00h.

54 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register B4h–B7h: PW2 FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE)

B4h 231 230 229 228 227 226 225 224 B5h 223 222 221 220 219 218 217 216 B6h 215 214 213 212 211 210 29 28 B7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The PWE value is compared against the value written to this location to enable PW2 access. At power-on, the PWE value is set to all ones. Thus, writing these bytes to all ones grants PW2 access on power-on without writing the password entry. All reads of this register are 00h.

Table 02h, Register B8h: RESERVED

FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

This register is reserved.

Table 02h, Register B9h: HBIAS2 DAC

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

B9h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the HBIAS2 reference and recalled from Table 06h (Registers E0h–E7h) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHBIAS2 compared against VBMON2 create an HBAL alarm. Full Scale V= × HBIAS2 DAC HBIAS2 256

______55 SFP Controller with Dual LDD Interface

Table 02h, Register BAh: HTXP2 DAC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile DS1876

BAh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the HTXP2 reference and recalled from Table 06h (Registers E8h–EFh) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHTXP2 compared against VPMON2 create a TXP HI alarm. Full Scale V= × HTXP2 DAC HTXP2 256

Table 02h, Register BBh: LTXP2 DAC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

BBh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the LTXP2 reference and recalled from Table 06h (Registers F0h–F7h) (transmitter 2) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons less than VLTXP2 compared against VPMON2 create a TXP LO alarm. Full Scale V= × LTXP2 DAC LTXP2 256

Table 02h, Register BCh: RESERVED FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

This register is reserved.

56 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register BDh: HBIAS1 DAC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

BDh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the HBIAS1 reference and recalled from Table 06h (Registers E0h–E7h) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons greater than VHBIAS1 compared against VBMON1 create an HBAL alarm. Full Scale V= × HBIAS1DAC HBIAS1 256

Table 02h, Register BEh: HTXP1 DAC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

BEh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the HTXP1 reference and recalled from Table 06h (Registers E8h–EFh) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons great than VHTXP1 compared against VPMON1 create a TXP HI alarm. Full Scale V= × HTXP1 DAC HTXP1 256

Table 02h, Register BFh: LTXP1 DAC FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and QT1EN = 0) or (PW1 and RWTBL2 and QT1EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

BFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for the LTXP1 reference and recalled from Table 06h (Registers F0h–F7h) (transmitter 1) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. Comparisons less than VLTXP1 compared against VPMON1 create a TXP LO alarm. Full Scale V= × LTXP1 DAC LTXP1 256

______57 SFP Controller with Dual LDD Interface

Table 02h, Register C0h: PW_ENA

FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location

DS1876 MEMORY TYPE Nonvolatile (SEE)

C0h RESERVED RWTBL1C RWTBL2 RWTBL1A RWTBL1B WLOWER WAUXA WAUXB BIT 7 BIT 0

BIT 7 RESERVED RWTBL1C: Table 01h or 05h bytes F8–FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). BIT 6 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2.

RWTBL2: Table 02h. Writing a nonvolatile value to this bit requires PW2 access. BIT 5 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. RWTBL1A: Table 01h, Registers 80h–BFh. BIT 4 0 = Read and write access for PW2 only. 1 = (default) Read and write access for both PW1 and PW2. RWTBL1B: Table 01h, Registers C0h–F7h. BIT 3 0 = (default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2. WLOWER: Bytes 00h–5Fh in main memory. All users can read this area. BIT 2 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXA: Auxiliary memory, Registers 00h–7Fh. All users can read this area. BIT 1 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2. WAUXB: Auxiliary memory, Registers 80h–FFh. All users can read this area. BIT 0 0 = (default) Write access for PW2 only. 1 = Write access for both PW1 and PW2.

58 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register C1h: PW_ENB

FACTORY DEFAULT 03h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

C1h RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B WPW1 WAUXAU WAUXBU BIT 7 BIT 0

RWTBL46: Tables 04h and 06h. BIT 7 0 = (default) Read and write access for PW2 only. 1 = Read and write access for PW1 and PW2. RTBL1C: Table 01h or Table 05h, Registers F8h–FFh. Table address is dependent on MASK bit (Table 02h, Register 88h). BIT 6 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL2: Table 02h. BIT 5 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1A: Table 01h, Registers 80h–BFh. BIT 4 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. RTBL1B: Table 01h, Registers C0h–F7h. BIT 3 0 = (default) Read and write access for PW2 only. 1 = Read access for PW1 and PW2. WPW1: Register PW1 (Table 02h, Registers B0h–B3h). For security purposes these registers are not readable. BIT 2 0 = (default) Write access for PW2 only. 1 = Write access for PW1 and PW2. WAUXAU: Auxiliary memory, Registers 00h–7Fh. All users can read this area. BIT 1 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2. WAUXBU: Auxiliary memory, Registers 80h–FFh. All users can read this area. BIT 0 0 = Write access for PW2 only. 1 = (default) Write access for user, PW1, and PW2.

Table 02h, Register C2h–C5h: RESERVED FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE N/A

These registers are reserved.

______59 SFP Controller with Dual LDD Interface

Table 02h, Register C6h: POLARITY

FACTORY DEFAULT 0Fh READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location

DS1876 MEMORY TYPE Nonvolatile (SEE)

C6h RESERVED RESERVED RESERVED RESERVED MOD2P APC2P MOD1P APC1P BIT 7 BIT 0

BITS 7:4 RESERVED MOD2P: MOD2 DAC polarity. The MOD2 DAC (Table 02h, Registers C8h–C9h) range is 000h–3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of MOD2 DAC is 000h; thus an application that needs VREFIN to be the off state should use the BIT 3 inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. APC2P: APC2 DAC polarity. The APC2 DAC (Table 02h, Registers CAh–CBh) range is 000h–3FFh. A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of APC DAC is 000h; thus an application that needs V to be the off state should use the inverted polarity. BIT 2 REFIN 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. MOD1P: MOD1 DAC polarity. The MOD1 DAC (Table 02h, Registers CCh–CDh) range is 000h–3FFh. A setting of 000h creates a pulse-density of zero and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of MOD1 DAC is 000h; thus an application that needs VREFIN to be the off state should use the BIT 1 inverted polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND. APC1P: APC1 DAC polarity. The APC1 DAC (Table 02h, Registers CEh–CFh) range is 000h–3FFh. A setting of 000h creates a pulse-density of zero, and 3FFh creates a pulse-density of 1023/1024. This polarity bit allows the user to use GND or VREFIN as the reference. The power-on of APC1 DAC is 000h; thus an application that needs VREFIN to be the off state should use the inverted BIT 0 polarity. 0 = Normal polarity. A setting of 000h results in a pulse-density output of zero held at GND, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at VREFIN. 1 = Inverted polarity. A setting of 000h results in a pulse-density output of zero held at VREFIN, and a setting of 3FFh results in a pulsed-density output of 1023/1024 held mostly at GND.

60 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register C7h: TBLSELPON

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Nonvolatile (SEE)

C7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Chooses the initial value for the TBL SEL byte (Lower Memory, Register 7Fh) at power-on.

Table 02h, Register C8h–C9h: MOD2 DAC

FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and MOD2EN = 0) or (PW1 and RWTBL2 and MOD2EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

C8h 0 0 0 0 0 0 29 28 C9h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for MOD2 DAC. It is the result of LUT4 plus MOD2 OFFSET times 4 recalled from Table 04h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. MOD2 DAC = LUT4 + MOD2 OFFSET x 4 V V=REFIN × MOD2 DAC MOD2 1024

______61 SFP Controller with Dual LDD Interface

Table 02h, Register CAh–CBh: APC2 DAC FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and APC2EN = 0) or (PW1 and RWTBL2 and APC2EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile DS1876

CAh 0 0 0 0 0 0 29 28 CBh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for APC2 DAC. It is the result of LUT6 plus APC2 OFFSET times 4 recalled from Table 06h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. APC2 DAC = LUT6 + APC2 OFFSET x 4 V V=REFIN × APC2 DAC APC2 1024

Table 02h, Register CCh–CDh: MOD1 DAC FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and MOD1EN = 0) or (PW1 and RWTBL2 and MOD1EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

CCh 0 0 0 0 0 0 29 28 CDh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for MOD1 DAC. It is the result of LUT4 plus MOD1 OFFSET times 4 recalled from Table 04h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. MOD1 DAC = LUT4 + MOD1 OFFSET x 4 V V=REFIN × MOD1 DAC MOD1 1024

62 ______SFP Controller with Dual LDD Interface DS1876 Table 02h, Register CEh–CFh: APC1 DAC FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS (PW2 and APC1EN = 0) or (PW1 and RWTBL2 and APC1EN = 0) A2h AND B2h MEMORY Common A2h and B2h memory location MEMORY TYPE Volatile

CEh 0 0 0 0 0 0 29 28 CFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value used for APC1 DAC. It is the result of LUT6 plus APC1 OFFSET times 4 recalled from Table 06h (Registers F8h–FFh) at the adjusted memory address found in TINDEX. This register is updated at the end of the temperature conversion. APC1 DAC = LUT6 + APC1 OFFSET x 4 V V=REFIN × APC1 DAC APC1 1024

Table 02h, Register D0h–FFh: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE None

These registers do not exist.

______63 SFP Controller with Dual LDD Interface

Table 04h Register Descriptions Table 04h, Register 80h–C7h: MODULATION LUT (MOD)

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations DS1876 MEMORY TYPE Nonvolatile (EE)

80h–C7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Digital value for the MOD1 DAC (A2h address) and MOD2 DAC (B2h address) outputs. The MODULATION LUT is a set of registers assigned to hold the temperature profile for the MOD1 and MOD2 DACs. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h in Table 04h. Register 80h defines the -40NC to -38NC MOD output, Register 81h defines -38NC to -36NC MOD output, and so on. Values recalled from this EEPROM memory table are written into the MOD1 and MOD2 DACs (Table 02h, Registers C8h–C9h, CCh–CDh) locations that hold the values until the next temperature conversion. The part can be placed into a manual mode (MOD1EN and MOD2EN bits, Table 02h, Register 80h), where MOD1 and MOD2 DACs are directly controlled for calibration. If the temperature compensation functionality is not required, program the entire Table 04h to the desired modulation setting.

Table 02h, Register C8h–F7h: EMPTY

FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE None

These registers do not exist.

64 ______SFP Controller with Dual LDD Interface DS1876 Table 04h, Register F8h–FFh: MOD OFFSET LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

F8h–FFh 29 28 27 26 25 24 23 22 BIT 7 BIT 0

The digital value for the temperature offset of the MOD1 and MOD2 DAC outputs.

F8h Less than or equal to -8NC F9h Greater than -8NC up to +8NC FAh Greater than +8NC up to +24NC FBh Greater than +24NC up to +40NC FCh Greater than +40NC up to +56NC FDh Greater than +56NC up to +72NC FEh Greater than +72NC up to +88NC FFh Greater than +88NC

The MOD DAC is a 10-bit value. The MODULATION LUT is an 8-bit LUT. The MOD OFFSET LUT times 4 plus the MODULATION LUT makes use of the entire 10-bit range.

Table 06h Register Descriptions Table 06h, Register 80h–C7h: APC LUT

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

80h–C7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The digital value for the APC1 DAC (A2h address) and APC2 DAC (B2h address) outputs. The APC LUT is a set of registers assigned to hold the temperature profile for the APC1 and APC2 DACs. The temperature measurement is used to index the LUT (TINDEX, Table 02h, Register 81h) in 2NC increments from -40NC to +102NC, starting at 80h. Register 80h defines the -40NC to -38NC APC output, Register 81h defines -38NC to -36NC APC output, and so on. Values recalled from this EEPROM memory table are written into the APC1 and APC2 DACs (Table 02h, Registers CAh–CBh, CEh–CFh) locations that hold the values until the next temperature conversion. The part can be placed into a manual mode (APC1EN and APC2EN bits, Table 02h, Register 80h), where APC1 and APC2 DACs are directly controlled for calibration. If the temperature compensation functionality is not required, program the entire Table 06h to the desired APC setting.

______65 SFP Controller with Dual LDD Interface

Table 06h, Register C8h–DFh: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A A2h AND B2h MEMORY N/A MEMORY TYPE None DS1876

These registers do not exist.

Table 06h, Register E0h–E7h: HBATH LUT

FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

E0h–E7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The high bias alarm threshold (HBATH) LUT is used to temperature compensate the bias QT threshold (HBIAS). The table below shows the range of temperature for each byte’s location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis.

E0h Less than or equal to -8NC E1h Greater than -8NC up to +8NC E2h Greater than +8NC up to +24NC E3h Greater than +24NC up to +40NC E4h Greater than +40NC up to +56NC E5h Greater than +56NC up to +72NC E6h Greater than +72NC up to +88NC E7h Greater than +88NC

66 ______SFP Controller with Dual LDD Interface DS1876 Table 06h, Register E8h–EFh: HTXP LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

E8h–EFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The HTXP LUT is used to temperature compensate the transmit power-high QT threshold (TXP HI). The table below shows the range of temperature for each byte’s location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis.

E8h Less than or equal to -8NC E9h Greater than -8NC up to +8NC EAh Greater than +8NC up to +24NC EBh Greater than +24NC up to +40NC ECh Greater than +40NC up to +56NC EDh Greater than +56NC up to +72NC EEh Greater than +72NC up to +88NC EFh Greater than +88NC

Table 06h, Register F0h–F7h: LTXP LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE)

F0h–F7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0

The LTXP LUT is used to temperature compensate the transmit power-low QT threshold (TXP LO). The table below shows the range of temperature for each byte’s location. The table shows a rising temperature; for a falling temperature there is 1NC of hysteresis.

F0h Less than or equal to -8NC F1h Greater than -8NC up to +8NC F2h Greater than +8NC up to +24NC F3h Greater than +24NC up to +40NC F4h Greater than +40NC up to +56NC F5h Greater than +56NC up to +72NC F6h Greater than +72NC up to +88NC F7h Greater than +88NC

______67 SFP Controller with Dual LDD Interface

Table 06h, Register F8h–FFh: APC OFFSET LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL46) WRITE ACCESS PW2 or (PW1 and RWTBL46) A2h AND B2h MEMORY Different A2h and B2h memory locations MEMORY TYPE Nonvolatile (EE) DS1876

F8h–FFh 29 28 27 26 25 24 23 22 BIT 7 BIT 0

The digital value for the temperature offset of the APC1 and APC2 DAC outputs.

The APC DAC is a 10-bit value. The APC LUT is an 8-bit LUT. The APC OFFSET LUT times 4 plus the APC LUT makes use of the entire 10-bit range.

Auxiliary Memory A0h Register Descriptions Auxiliary Memory A0h, Register 00h–7Fh: EEPROM

FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WAUXA) or (WAUXAU) MEMORY TYPE Nonvolatile (EE)

00h–7Fh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Accessible with the slave address A0h.

68 ______SFP Controller with Dual LDD Interface DS1876 Auxiliary Memory A0h, Register 80h–FFh: EEPROM FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 or (PW1 and WAUXB) or (WAUXBU) MEMORY TYPE Nonvolatile (EE)

80h–FFh 27 26 25 24 23 22 21 20 BIT 7 BIT 0

Accessible with the slave address A0h.

Applications Information Package Information Power-Supply Decoupling For the latest package outline information and land patterns, To achieve best results, it is recommended that the power go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package supply is decoupled with a 0.01FF or a 0.1FF capacitor. drawings may show a different suffix character, but the drawing Use high-quality, ceramic, surface-mount capacitors, pertains to the package regardless of RoHS status. and mount the capacitors as close as possible to the PACKAGE TYPE PACKAGE CODE DOCUMENT NO. VCC and GND pins to minimize lead inductance. 28 TQFN-EP T2855+6 21-0140 SDA and SCL Pullup Resistors SDA is an open-collector output on the DS1876 that requires a pullup resistor to realize high logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the I2C AC Electrical Characteristics table are within specification.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 69 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.