CSX700 Floating Point Processor Datasheet
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CSX700 Floating Point Processor Datasheet Feature summary 1.2V and 1.8V analog supplies High performance Mechanical/thermal 40 mm x 40 mm thermally enhanced flip-chip 96 GFLOPS double precision floating point package (peak) 1429 balls on 1 mm pitch Single and double precision, IEEE 754 compliant, FPUs 680 signal pins (including analog supplies) Power efficient architecture Power dissipation 10W typical Features Description Professional Software Development Kit (SDK) The CSX700 is a high performance, low power Two multi-threaded processing cores, each floating point coprocessor. It is designed for use with: in a variety of applications in high performance – Array of 96 Processing Elements (PE) computing and embedded systems. – Double and single precision floating-point The CSX700 is the second product in acceleration in every PE ClearSpeed’s family of floating point application – Controller with 8 Kbyte instruction and 4 accelerators. The CSX processors are based Kbyte data cache around ClearSpeed’s multi-threaded array PCI-Express x16 (Gen. 1 rev 1.1) host processor (MTAP) architecture. This architecture interface has been developed to address the 2 x 128 Kbyte on-chip SRAM implementation issues of high-performance systems by providing unparalleled performance- 2 x 8 Gbytes of external DDR2 DRAM support per-watt. High speed chip-chip interface (CCBR) Configuration/debug port (HDP) CSX700 Bus Bus JTAG boundary scan (IEEE compliant) Monitor Monitor 128K 128K Applications SRAM SRAM MU MTAP MTAP MU Designed for data-intensive and high-compute DDR2- DDR2- applications 533 533 Finance Radar systems D D M M Bio-informatics A A Signal processing On Chip Network (ClearConnect Bus) Medical imaging System DM A Host Interface Services PCIe x16 Electrical HDP CCBR 1.0V core supply 1.8V and 3.3V I/O supplies 06-PD-1425 Rev 1E January 2011 1 Table of contents CSX700 Datasheet Table of contents 1 Description . 3 1.1 Multi-threaded array processor (MTAP) core . 3 1.1.1 MTAP overview . 5 1.1.2 Mono controller . 5 1.1.3 Mono execution unit . 6 1.1.4 Poly execution unit . 6 1.1.5 Input-output . 6 1.2 PCI Express host interface (HIF) . 7 1.3 Host debug port (HDP) . 7 1.4 ClearConnect Bridge (CCBR) . 7 1.5 Memory unit (MU) . 7 1.6 Interrupt and semaphore unit (ISU) . 7 1.7 SRAM . 8 1.8 System services . 8 1.9 Bus monitor (BMON) . 8 1.10 ClearConnect Bus (CCB) . 8 2 Interfaces . 9 2.1 I/O signal types . 9 2.1.1 3.3V LVTTL . 9 2.1.2 1.8V CMOS . 9 2.1.3 1.8V SSTL . 9 2.1.4 1.8V differential SSTL clock inputs . 9 2.1.5 PCI Express . 9 2.2 Pin lists . 10 2.3 PCI Express . 20 2.4 Host/debug port (HDP) . 22 2.5 ClearConnect Bridge port . 22 2.6 Memory unit . 23 2.7 System services . 24 2.7.1 Reset . 24 2.7.2 Clocking . 25 2.7.3 GPIO . 25 2 06-PD-1425 Rev 1E ClearSpeed Technology Ltd CSX700 Datasheet Table of contents 2.7.4 Configuration TAP controller . 25 2.7.5 Thermal monitor . 28 2.8 JTAG boundary scan test access port (TAP) . 28 2.8.1 TAP instructions . 29 3 DC and thermal characteristics . 30 3.1 Recommended operating conditions . 30 3.1.1 Supply sequencing . 31 3.2 Handling and assembly . 31 3.3 Absolute maximum and minimum ratings . 32 3.4 Termination and reference voltages . 32 3.4.1 CCBR . 32 3.4.2 PCI Express . 33 3.4.3 MU . 33 3.4.4 Analog supplies . 33 3.5 1.8V CMOS DC characteristics . 35 3.6 3.3V LVTTL characteristics . 36 3.7 SSTL DC characteristics . 36 4 AC characteristics . 37 4.1 Test conditions . 37 4.2 PCI Express interface . 37 4.3 HDP . 38 4.4 CCBR . 40 4.5 Memory unit . 42 4.6 System service . 43 4.6.1 JTAG and CTAP . 44 5 Bootstrap sequence . 45 6 Mechanical data . 46 7 Ordering Information . 48 Revision history . 49 06-PD-1425 Rev 1E 3 ClearSpeed Technology Ltd Table of contents CSX700 Datasheet 4 06-PD-1425 Rev 1E ClearSpeed Technology Ltd CSX700 Datasheet Description 1 Description The CSX700 comprises two multi-threaded array processor (MTAP) cores, two external DDR2 DRAM interfaces, a 16-lane PCI Express host interface, a high-speed chip-to-chip interface and embedded SRAM integrated onto a single chip. All subsystems on the chip are interconnected by a ClearConnect on-chip network (the ClearConnect bus). Bus CSX700 Bus Monitor Monitor 128K 128K SRAM SRAM MTAP MTAP Mono Mono Control Instruc Controller Controller Instruc Control and tion Data Data tion and MU MU Debug Cache Cache Cache Cache Debug DDR2- DDR2- 533 533 Poly Controller Poly Controller P P P P PE PE E E E E n–1 n–1 0 1 … 0 1 … D D M M A Programmable I/O Programmable I/O A On Chip Network (ClearConnect Bus) System Services DMA Host Interface GPIO JTAG Reset & Clocking PCIe x16 HDP CCBR Figure 1: CSX700 block diagram 1.1 Multi-threaded array processor (MTAP) core The MTAP architecture provides an exceptionally powerful and scalable processing solution, based on a SIMD array of processing elements (PEs). Each PE has its own local memory and I/O capability, making the architecture ideally suited for applications which have high processing and/or bandwidth requirements. Each MTAP core contains an array of 96 PEs. The PEs include multiple processing units and have high level of internal instruction-level and data parallelism. Each PE also has its own local memory providing a high bandwidth access to frequently used data. 06-PD-1425 Rev 1E 5 ClearSpeed Technology Ltd Description CSX700 Datasheet Instruction Fetch Load/Store 128 Instruction Data Cache Cache (8 Kbytes) (4 Kbytes) 128 Control Unit Instruction 32 Register Fetch Control Read/Write 128 32 32 Interrupt Instruction IRQ Semaphores ALU Load/Store Generation 32 Decode 32 16 16 32 128 32 Register File (64 bytes) Result Per Thread Return Registers PC (8 threads) PIO Load/Store Array Controller Controller Controller Mono Execution Unit Poly Execution Unit MAC FP Mul FP Add FP ÷ √ ALU 64 64 64 Register File 64(128 bytes) 64 64 PE PE PE 0 PE i-1 SRAM i+1 n-1 (6 Kbytes) 32 I/O Buffer (64 bytes) 128 PIO PIO 128 Engine Figure 2: Block diagram of a single MTAP core 6 06-PD-1425 Rev 1E ClearSpeed Technology Ltd CSX700 Datasheet Description 1.1.1 MTAP overview The two MTAP cores are identical; a single MTAP core is shown in the block diagram (Figure 2). The main components of the processor are: z Mono control unit: fetches and decodes instructions. The single, unified instruction stream are fetched and decoded by the control unit. Mono instructions are despatched to the mono execution unit, poly instructions are sent to the poly controller; z Poly controller: contains three.