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Architecture and Organization (AR) 1 Architecture and Organization (AR) 2 Computing professionals should not regard the computer as just a black box that executes 3 programs by magic. AR builds on SF to develop a deeper understanding of the hardware 4 environment upon which all of computing is based, and the interface it provides to higher 5 software layers. Students should acquire an understanding and appreciation of a computer 6 system’s functional components, their characteristics, performance, and interactions, and, in 7 particular, the challenge of harnessing parallelism to sustain performance improvements now and 8 into the future. Students need to understand computer architecture to develop programs that can 9 achieve high performance through a programmer’s awareness of parallelism and latency. In 10 selecting a system to use, students should to able to understand the tradeoff among various 11 components, such as CPU clock speed, cycles per instruction, memory size, and average memory 12 access time. 13 The learning outcomes specified for these topics correspond primarily to the core and are 14 intended to support programs that elect to require only the minimum 16 hours of computer 15 architecture of their students. For programs that want to teach more than the minimum, the same 16 topics (AR1-AR8) can be treated at a more advanced level by implementing a two-course 17 sequence. For programs that want to cover the elective topics, those topics can be introduced 18 within a two-course sequence and/or be treated in a more comprehensive way in a third course. 19 20 AR. Architecture and Organization (0 Core-Tier 1 hours, 16 Core-Tier 2 hours) Core-Tier 1 Core-Tier 2 Includes hours Hours Elective AR/Digital logic and digital systems 3 N AR/Machine level representation of data 3 N AR/Assembly level machine organization 6 N AR/Memory system organization and 3 N architecture AR/Interfacing and communication 1 N AR/Functional organization Y AR/Multiprocessing and alternative Y architectures AR/Performance enhancements Y 21 22 AR/Digital logic and digital systems 23 [3 Core-Tier 2 hours] 24 Topics: 25 • Overview and history of computer architecture 26 • Combinational vs. sequential logic/Field programmable gate arrays as a fundamental combinational + 27 sequential logic building block 28 • Multiple representations/layers of interpretation (hardware is just another layer) 29 • Computer-aided design tools that process hardware and architectural representations 30 • Register transfer notation/Hardware Description Language (Verilog/VHDL) 31 • Physical constraints (gate delays, fan-in, fan-out, energy/power) 32 33 Learning outcomes: 34 1. Describe the progression of computer technology components from vacuum tubes to VLSI, from 35 mainframe computer architectures to the organization of warehouse-scale computers [Knowledge]. 36 2. Comprehend the trend of modern computer architectures towards multi-core and that parallelism is inherent 37 in all hardware systems [Knowledge]. 38 3. Explain the implications of the “power wall” in terms of further processor performance improvements and 39 the drive towards harnessing parallelism [Knowledge]. 40 4. Articulate that there are many equivalent representations of computer functionality, including logical 41 expressions and gates, and be able to use mathematical expressions to describe the functions of simple 42 combinational and sequential circuits [Knowledge]. 43 5. Design the basic building blocks of a computer: arithmetic-logic unit (gate-level), registers (gate-level), 44 central processing unit (register transfer-level), memory (register transfer-level) [Application]. 45 6. Use CAD tools for capture, synthesis, and simulation to evaluate simple building blocks (e.g., arithmetic- 46 logic unit, registers, movement between registers) of a simple computer design [Application]. 47 7. Evaluate the functional and timing diagram behavior of a simple processor implemented at the logic circuit 48 level [Evaluation]. 49 50 AR/Machine-level representation of data 51 [3 Core-Tier 2 hours] 52 Topics: 53 • Bits, bytes, and words 54 • Numeric data representation and number bases 55 • Fixed- and floating-point systems 56 • Signed and twos-complement representations 57 • Representation of non-numeric data (character codes, graphical data) 58 • Representation of records and arrays 59 60 Learning outcomes: 61 1. Explain why everything is data, including instructions, in computers [Knowledge]. 62 2. Explain the reasons for using alternative formats to represent numerical data [Knowledge]. 63 3. Describe how negative integers are stored in sign-magnitude and twos-complement representations 64 [Knowledge]. 65 4. Explain how fixed-length number representations affect accuracy and precision [Knowledge]. 66 5. Describe the internal representation of non-numeric data, such as characters, strings, records, and arrays 67 [Knowledge]. 68 6. Convert numerical data from one format to another [Application]. 69 7. Write simple programs at the assembly/machine level for string processing and manipulation [Application]. 70 71 AR/Assembly level machine organization 72 [6 Core-Tier 2 hours] 73 Topics: 74 • Basic organization of the von Neumann machine 75 • Control unit; instruction fetch, decode, and execution 76 • Instruction sets and types (data manipulation, control, I/O) 77 • Assembly/machine language programming 78 • Instruction formats 79 • Addressing modes 80 • Subroutine call and return mechanisms 81 • I/O and interrupts 82 • Heap vs. Static vs. Stack vs. Code segments 83 • Shared memory multiprocessors/multicore organization 84 • Introduction to SIMD vs. MIMD and the Flynn Taxonomy 85 86 Learning outcomes: 87 1. Explain the organization of the classical von Neumann machine and its major functional units 88 [Knowledge]. 89 2. Describe how an instruction is executed in a classical von Neumann machine, with extensions for threads, 90 multiprocessor synchronization, and SIMD execution [Knowledge]. 91 3. Describe instruction level parallelism and hazards, and how they are managed in typical processor pipelines 92 [Knowledge]. 93 4. Summarize how instructions are represented at both the machine level and in the context of a symbolic 94 assembler [Knowledge]. 95 5. Demonstrate how to map between high-level language patterns into assembly/machine language notations 96 [Knowledge]. 97 6. Explain different instruction formats, such as addresses per instruction and variable length vs. fixed length 98 formats [Knowledge]. 99 7. Explain how subroutine calls are handled at the assembly level [Knowledge]. 100 8. Explain the basic concepts of interrupts and I/O operations [Knowledge]. 101 9. Explain how subroutine calls are handled at the assembly level [Knowledge]. 102 10. Write simple assembly language program segments [Application]. 103 11. Show how fundamental high-level programming constructs are implemented at the machine-language level 104 [Application]. 105 106 AR/Memory system organization and architecture 107 [3 Core-Tier 2 hours] 108 [Cross-reference OS/Memory Management--Virtual Machines] 109 Topics: 110 • Storage systems and their technology 111 • Memory hierarchy: importance of temporal and spatial locality 112 • Main memory organization and operations 113 • Latency, cycle time, bandwidth, and interleaving 114 • Cache memories (address mapping, block size, replacement and store policy) 115 • Multiprocessor cache consistency/Using the memory system for inter-core synchronization/atomic memory 116 operations 117 • Virtual memory (page table, TLB) 118 • Fault handling and reliability 119 • Coding, data compression, and data integrity 120 121 Learning outcomes: 122 1. Identify the main types of memory technology [Knowledge]. 123 2. Explain the effect of memory latency on running time [Knowledge]. 124 3. Describe how the use of memory hierarchy (cache, virtual memory) is used to reduce the effective memory 125 latency [Knowledge]. 126 4. Describe the principles of memory management [Knowledge]. 127 5. Explain the workings of a system with virtual memory management [Knowledge]. 128 6. Compute Average Memory Access Time under a variety of memory system configurations and workload 129 assumptions [Application]. 130 131 132 AR/Interfacing and communication 133 [1 Core-Tier 2 hour] 134 [Cross-reference OS Knowledge Area for a discussion of the operating system view of 135 input/output processing and management. The focus here is on the hardware mechanisms for 136 supporting device interfacing and processor-to-processor communications.] 137 Topics: 138 • I/O fundamentals: handshaking, buffering, programmed I/O, interrupt-driven I/O 139 • Interrupt structures: vectored and prioritized, interrupt acknowledgment 140 • External storage, physical organization, and drives 141 • Buses: bus protocols, arbitration, direct-memory access (DMA) 142 • Introduction to networks: networks as another layer of access hierarchy 143 • Multimedia support 144 • RAID architectures 145 146 Learning outcomes: 147 1. Explain how interrupts are used to implement I/O control and data transfers [Knowledge]. 148 2. Identify various types of buses in a computer system [Knowledge]. 149 3. Describe data access from a magnetic disk drive [Knowledge]. 150 4. Compare common network organizations, such as ethernet/bus, ring, switched vs. routed [Knowledge]. 151 5. Identify interfaces needed for multimedia support, from storage, through network, to memory and display 152 [Knowledge]. 153 6. Describe the advantages and limitations of RAID architectures [Knowledge]. 154 155 AR/Functional organization
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