Silicon Carbide High Temperature Logic

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SILICON CARBIDE HIGH TEMPERATURE LOGIC

TE-HAO LEE

Submitted in partial fulfillment of the requirements

for the degree of Doctor of Philosophy

Dissertation Advisor: Professor Mehran Mehregany

DEPARTMENT OF MATERIALS SCIENCE AND ENGINEERING

CASE WESTERN RESERVE UNIVERSITY

JANUARY, 2011

CASE WESTERN RESERVE UNIVERSITY

SCHOOL OF GRADUATE STUDIES

We hereby approve the thesis/dissertation of

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candidate for the ______degree *.

(signed)______(chair of the committee)

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(date) ______

*We also certify that written approval has been obtained for any proprietary material contained therein.

To my mother and sister

Table of Contents

Table of Contents ...... i List of Tables ...... iv List of Figures ...... v Acknowledgment ...... xi Abstract ...... xiii

CHAPTER 1 Introduction...... 1 1.1 Motivation ...... 1 1.2 Existing High Temperature Logic Devices ...... 3 1.2.1 GaN Technology ...... 5 1.2.2 SiC Technology ...... 5 1.3 State-of-the-Art Device Structures Based on NEMS Switches ...... 8 1.3.1 Suspended Gate MOSFET (SG-MOSFET) ...... 8 1.3.2 All-Mechanical NEMS Devices ...... 11 1.3.2.1 Carbon Nanotubes ...... 13 1.3.2.2 Metals ...... 15 1.3.2.3 Compound Materials and Compound Semiconductors ...... 16 1.4 Sacrificial Layers and Releasing Techniques ...... 18 1.4.1 Silicon Dioxide ...... 19 1.4.2 Silicon and Organic Materials ...... 20 1.5 Summary of Developed NEMS switches ...... 22 1.6 Reliability Issues ...... 24 1.6.1 Fatigue and Wear ...... 24 1.6.2 Adhesion ...... 26 1.7 High Temperature Dielectric ...... 27 1.8 Thesis Organization ...... 28 CHAPTER 2 Design and Fabrication of 2-Terminal Poly-SiC NEMS Switches ...... 29 2.1 Introduction ...... 29 2.2 Design Criteria ...... 30

2.2.1 Spring Constant and Resonating Frequency of Cantilever ...... 30 2.2.2 Threshold Voltage ...... 31 2.2.3 Switching Time ...... 33 2.3 Dimensions of the Designed 2-Terminal SiC NEMS Switches ...... 35 2.4 Fabrication Process ...... 37 2.4.1 Deposition of Poly-SiC Thin Film ...... 41 2.4.2 SiC Dry Etching ...... 42 2.4.3 Oxidation of Poly-SiC...... 43 2.4.4 Vapor HF Release ...... 43 CHAPTER 3 Characterization of the 2-Terminal SiC Switches ...... 45 3.1 Introduction ...... 45 3.2 I-V Characteristics as a Function of Temperature ...... 47 3.3 Surface Oxide ...... 51 3.4 Contact Resistance ...... 53 3.5 Failure Mechanism ...... 59 3.5.1 Effect of Surface Roughness on Stiction ...... 59 3.5.2 Mechanical Fracture ...... 68 3.6 Graphitization of Poly-SiC ...... 70 3.6.1 Surface Analysis After Laser Processing ...... 70 3.6.2 TEM Observation...... 73 3.7 Graphitization of Single Crystalline 4H-SiC ...... 76 3.8 Summary ...... 78 CHAPTER 4 3-Terminal Poly-SiC NEMS Switches for High Temperature Logic ...... 80 4.1 Introduction ...... 80 4.2 Dimensions of the Designed Switch ...... 81 4.3 Fabrication Process ...... 83 4.4 I-V Characterization ...... 84 4.5 Inverter Operation ...... 88 4.6 Nanofabrication Challenges ...... 91 4.7 Summary ...... 93 CHAPTER 5 6H-SiC JFET-Based Logic ...... 94 5.1 Introduction ...... 94 5.2 Fabrication Process ...... 95 5.3 Characterization of 6H-SiC JFET ...... 99

5.4 Channel Leakage Current ...... 104 5.5 Logic Gates ...... 106 5.6 Gate Leakage Current ...... 112 5.7 Summary ...... 113 CHAPTER 6 Development of Dielectric Layers for High Temperature Applications .. 115 6.1 Introduction ...... 115 6.2 Silicon Dioxide and Silicon Nitride ...... 116 6.2.1 Films Deposited by LPCVD ...... 116 6.2.2 Films Deposited by PECVD ...... 117 6.3 Design and Fabrication of MIM Capacitors ...... 118 6.3.1 Design Criteria ...... 118 6.3.2 Deposition of PECVD TEOS Oxide and Nitride ...... 119 6.3.3 Fabrication Process of MIM Capacitors ...... 121 6.4 Characterization of the MIM Capacitors ...... 121 6.4.1 Capacitance at Room Temperature ...... 122 6.4.2 Capacitance at High Temperature ...... 126 6.4.3 Leakage Current at Room Temperature ...... 127 6.4.4 Leakage Current at High Temperature ...... 129 6.5 Breakdown Field ...... 131 6.6 Summary ...... 131 CHAPTER 7 Conclusion ...... 134 Bibliography ...... 137

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List of Tables

Table 1.1 Relevant electrical and mechanical properties of 6H-SiC, 4H-SiC, 3C- SiC and GaN measured at 300K [14]...... 4 Table 1.2 A summary of recently developed NEMS switching devices...... 23 Table 2.1 Key design parameters for the vertically-actuated SiC NEMS switch and some important material properties of SiC used in this chapter...... 35 Table 2.2 Process parameters for LPCVD SiC deposition...... 41 Table 3.1 Adhesion forces and energies calculated from AFM pull-off tests for SiC surfaces of different roughness...... 65

Table 4.1 Simulated VTH for devices with different dimensions...... 83 Table 5.1 Physical constants, parameters and some electrical properties of 6H- SiC used in this chapter to model the fabricated JFETs...... 100 Table 6.1 Process parameters for PECVD oxide (top) and nitride (bottom) depositions...... 120 Table 6.2 Quadratic and linear terms representing the voltage dependence of the two MIM capacitors under different testing frequencies...... 125 Table 6.3 Summary of the dielectric properties of the fabricated MIM capacitors...... 133

List of Figures

Figure 1.1 Typical GaN HEMT formed on a foreign substrate [15]...... 3 Figure 1.2 6H-SiC JFET logic circuits [27]: (a) optical micrograph of a NAND gate; (b) optical micrograph of a NOR gate; (c) test waveform of the NAND gate at 600 °C; and (d) test waveform of the NOR gate at 600 °C...... 7 Figure 1.3 Schematics of [4]: (a) the structure of a SGFET; (b) the cross-section of the device in OFF state; and (c) a SEM photo of a fabricated SGFET with four supporting arms [5]...... 10 Figure 1.4 Basic operation of CNEMS switches [10] (a) OFF state; and (b) ON state...... 12 Figure 1.5 Layouts of a NAND gate based on the CNEMS architecture using four nano-scale cantilevers (red beams in the figure)...... 12 Figure 1.6 SEM photo of a switch using a CNT. The length of the suspended CNT is ~800 nm [41]...... 14 Figure 1.7 SWNT switch [42]: (a) global SEM photo; and (b) high magnification image showing the CNT suspended over the pull-down electrode (trench)...... 14 Figure 1.8 SEM photo of a TiN NEMS switch with a 15 nm air gap. The beam deflection shown in the inset was caused by residual stress in the TiN layer and was reduced by high temperature annealing...... 17 Figure 1.9 SEM photos showing (a) a blanket coated silicon nitride film after vapor HF etch evidencing an abundance of etch residues on the film surface; and (b) a clean surface of amorphous SiC after 30 mins of

HF vapor etching, also evidencing that the underneath SiO2 layer is well protected...... 21

Figure 1.10 SEM photo showing the mechanical failure of a tungsten NEMS switch fabricated by ALD [45]. The length, width and thickness of the beam are 2000 nm, 700 nm and 32 nm, respectively...... 25 Figure 2.1 Deflection versus applied voltage simulation results for SiC NEMS switches of varying lengths...... 36 Figure 2.2 Fabrication process for the 2-terminal, vertically-actuated switches: (a) a 300 nm-thick, low-stress silicon nitride layer is deposited on a silicon substrate; (b) a 300 nm-thick layer of poly-SiC is deposited using LPCVD and patterned by standard lithography and etched by

RIE; (c) a 75 nm-thick layer of sacrificial SiO2 is grown thermally, and an anchor window is patterned in the sacrificial oxide; (d) another layer of poly-SiC is deposited by LPCVD to a thickness of ~100 nm. The poly-SiC is patterned by standard lithography and etched by RIE to define the top electrode cantilever beam; and (e) the sacrificial oxide is removed by vapor HF...... 38 Figure 2.3 Schematics of the customized set up for vapor HF releasing...... 44 Figure 3.1 SEM photos of: (a) a 10 µm-long, vertically-actuated SiC NEMS switch with 75 nm gap; and (b) focus ion beam section of the highlighted white rectangle in (a)...... 46 Figure 3.2 Test set up for: (a) measurement between 25 °C and 400 °C; and (b) measurement at 600 °C...... 49 Figure 3.3 I-V characteristics showing (a) room temperature and 400 °C operation and (b) 600 °C operation...... 50 Figure 3.4 XPS data showing the evolution of native oxide on the poly-SiC surface with increasing temperature...... 52 Figure 3.5 Contact resistance as a function of applied voltage...... 56 Figure 3.6 Comparison of measured contact resistance with those calculated using Sharvin’s model...... 57 Figure 3.7 Schematic showing a conduction path formed by electron traps

(shaded) in the SiO2 layer...... 57

Figure 3.8 Log I versus log V plot used to calculate the coefficients of the I-V

power law for post-breakdown SiO2...... 58 Figure 3.9 Contact resistance can be expressed in terms of contact force. For voltages higher than 20 V, contact resistance is almost inversely proportional to contact force...... 58 Figure 3.10 Obtained z-height schematics from AFM measurements of device surfaces with: (a) Ra = 1 nm; (b) Ra = 5 nm; and (c) Ra = 8 nm (unpolished). The scanned size was 10 µm × 10 µm...... 61 Figure 3.11 Data from testing at room temperature for 20 switches, each with different electrode contact surface roughness: (a) 1 nm; (b) 5 nm; and (c) 8 nm...... 63 Figure 3.12 A histogram of the 12 switches (i.e., 60 % of 20 in Fig. 3.10(c)) with Ra = 8 nm showing cycles of operations before failure from fracture...... 64 Figure 3.13 Schematics showing the difference in the distance between the non-

contacting portion of switches (Dave): (a) smoother contacting surfaces; and (b) rougher contacting surfaces [57]...... 65 Figure 3.14 Pull-off force test data for a switch with 1 nm roughness on contact surfaces. The pull-off force was obtained from F = k·x, where x is the distance between “a” and “e” labeled in the schematics...... 66 Figure 3.15 Failure mechanisms observed at 300 °C in switches with Ra = 8 nm...... 67 Figure 3.16 SEM photos of: (a) a switch after 5 billion cycles of operation, wherein the red circles point out the fracture location and irregularities likely due to mass transport; and (b) a virgin switch...... 69 Figure 3.17 Optical micrograph showing the difference in surface morphologies between the laser treated and untreated regions...... 71 Figure 3.18 XPS depth profile showing the composition change of the sample treated by XeCl laser with a fluence of 1.2 J/cm2...... 72

Figure 3.19 TEM photo showing crack formation in a SiO2 layer after laser treatment...... 73

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Figure 3.20 TEM photo of the poly-SiC sample subject to 1.3 J/cm2 laser energy with a magnified view of the formed nanographite ribbons. The inset in the magnified photo shows the SAED of the nanographite...... 75 Figure 3.21 Optical micrograph showing the effect of laser energy on a 4H-SiC wafer surface...... 77 Figure 3.22 Confocal microscopy image showing the rough surface of 4H-SiC after laser treatment...... 77 Figure 3.23 TEM photo showing the nanographite structure of the 4H-SiC surface after laser treatment...... 79 Figure 4.1 The complementary 3-terminal switch: (a) schematic representation; (b) a SEM photo of a released SiC NEMS switch with L = 3 µm, t =

200 nm; and g1 = 150 nm; and (c) a SEM photo showing the ON state of the 3-terminal SiC NEMS switch...... 81 Figure 4.2 I-V characteristics showing room temperature actuation. The current reaches the set current limit (30 nA) when the applied DC voltage is higher than 6 V...... 86 Figure 4.3 SEM photo showing switch failure due to a clean fracture at the support end of the cantilever beam after 21+ billion cycles...... 87 Figure 4.4 Photos showing the high temperature test setup...... 87 Figure 4.5 SEM photo showing switch failure after 2+ billion cycles at 500 °C. The reason for the melting-like feature is not known...... 88 Figure 4.6 The complementary inverter logic showing the pull up and pull down stages: (a) schematic; and (b) layout...... 89 Figure 4.7 SEM photos of a fabricated inverter. The magnified photo shows the

cantilever connected to VSS and the corresponding actuation gap...... 90 Figure 4.8 Input-output voltage waveform of the inverter at 500 °C...... 90 Figure 4.9 SEM image showing the deflection phenomenon of a released cantilever due to residual stress...... 92 Figure 4.10 Material re-deposition in a 80 nm gap...... 92 Figure 5.1 Schematic diagram of the cross section of an as-received SiC wafer...... 95

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Figure 5.2 Fabrication process of JFET-base circuits: (a) RIE was used to form the gates of the JFET; (b) the channel region of the JFET was isolated using RIE; (c) a 1 μm-thick LTO was deposited and patterned as ion implantation mask for the source and drain contacts; (d) nitrogen ion implantation was conducted using a box profile (see table) to create the source and drain contacts; (e) the LTO was removed, and a 20

nm-thick SiO2 was grown thermally to passivate the SiC surfaces,

followed by openning contact holes; (f) a stack of Ti, TaSi2 and Pt was sputtered as Ohmic contact metal, followed by the deposition of a

300 nm Si3N4 passivation layer; and (g) two additional metallization steps using the same metal stack and an additional interlayer dielectric composed of PECVD silicon dioxide/nitride/dioxide sandwich structure were used to connect the transistors and passives to realize the circuits...... 96 Figure 5.3 Measured I-V behaviors of a representative JFET (W/L = 100 µm ×

10 µm) as a function of temperature up to 450 °C: (a) VDS-IDS data

with VGS and substrate biases both 0 V; (b) VGS-IDS data with VDS and substrate biases 20 V and 0 V, respectively...... 103 Figure 5.4 Measured channel leakage current of a JFET with W/L = 100 µm × 10 µm as a function of temperature up to 450 °C. This current was the

measured IDS value at VGS = -15 V, VDS= 20 V and Vsub = 0 V...... 105 Figure 5.5 Circuit schematics and corresponding truth tables of the designed SiC logic gates: (a) inverter; (b) NAND; and (c) NOR...... 107 Figure 5.6 Optical micrograph of the fabricated 6H-SiC JFET-based NOR gate constructed from 3 resistors and 4 transistors...... 108 Figure 5.7 Test waveforms for the SiC inverter at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and inputs are set at 1 kHz frequency during testing...... 109 Figure 5.8 Test waveforms for the SiC NAND gate at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and inputs are set at 1 kHz frequency during testing...... 110

Figure 5.9 Test waveforms for the SiC NOR gate at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and inputs are set at 1 kHz frequency during testing...... 111 Figure 5.10 Measured gate leakage current of a SiC NOR gate as a function of

temperature with Vsub = 0 V, VDD = +14 V and VSS = -14 V...... 114 Figure 6.1 Layout of the designed MIM capacitor with 200 µm × 200 µm area...... 119 Figure 6.2 The frequency dependence of capacitance measured at room temperature: (a) Capacitor A; and (b) Capacitor B...... 123 Figure 6.3 Measured capacitance of Capacitors A and B as a function of temperature...... 127 Figure 6.4 Measured room temperature leakage current density as a function of applied DC voltage for Capacitors A and B...... 128 Figure 6.5 Comparison of the leakage current density in Capacitors A and B measured at: (a) 300 °C; and (b) 525 °C...... 130 Figure 6.6 Breakdown field of Capacitor A (PECVD TEOS oxide) and Capacitor B (stack of PECVD TEOS oxide/nitride/TEOS oxide) as a function of temperature...... 132

Acknowledgment

I would like to express my deepest gratitude to my research advisor, Professor

Mehran Mehregany for his guidance, support and encouragement for the past 4 years.

Without his supervision and guidance, I would not have had the opportunity to explore and complete this project. I am grateful to Professors Arthur Heuer, Pirouz Pirouz, Frank

Ernst and Swarup Bhunia for not only serving as my committee members, but also for providing many scientific insights and valuable comments throughout my study.

I would like to thank Ed Jahnke, Ron Jezeski and Shubin Yu for their help in microfabrication, equipment setup and device packaging. I thank all members of

Swagelok Center for Surface Analysis of Materials including Prof. Hal Kahn, Dr. Wayne

Jennings, Dr. Alan McAlwain, Dr. Reza Sharghi- Moshtaghin, Dr. Amir Avishai, and Dr.

David Hovis for their assistance in characterizing material properties and morphologies. I am thankful to Dr. Ryan Lu, Dr. Christopher Huynh, Dr. Ayax Ramirez, and Dr. Stephen

Russell in Space and Naval Warfare Systems Center, Pacific for their help in XeCl laser processing.

I would also like to thank all MINO Lab members, Dr. Xiaoan Fu, Dr. Li Chen, Hari

Rajgopal, Noppasit Laotaveerungrueng, Grant McCallum, Man I Lei, Mohammed

Aloglah, Sheng Jin, Shih-Shian Ho, Kevin Speer, Kenji Okino, Cathy Soong and Chia-

Hua Lin for help and valuable discussions.

A special thanks goes to Chris Roberts for his help in test setup, valuable suggestions and friendship. I would also like to thank Prof. Steven Garverick and his group members

including Dr. Amita Patil, Chompoonoot Anupongongarch and David Tien for their guidance and help in testing and characterizing the electronic devices.

I would like to take this opportunity to express my appreciation to my mother and sister. Without their support, I could not focus on my research.

This work was supported by Defense Advanced Research Projects Agency (DARPA) under grants # N66001-07-12031 and NBCH2050002.

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Silicon Carbide High Temperature Logic

Abstract

TE-HAO LEE

This thesis explores the development of high temperature logic based on silicon

carbide (SiC) semiconductor technology, using nano-electro-mechanical systems

(NEMS) switches or junction field effect transistors (JFETs). NEMS switches have the

advantage of essentially zero leakage current in the OFF state, i.e., no leakage power, a short coming of electronic-based logic implementation. In the case of high temperature operation, the JFET leakage current in OFF state increases substantially with operating temperature. Hence, it is attractive to explore implementation of high temperature logic using an all-mechanical NEMS switch architecture or a hybridization of JFET devices with the NEMS switches wherein the NEMS switch is used to eliminate the JFET leakage current in the OFF state by opening the NEMS switch.

As a first step, and a potential candidate for hybridization with JFETs, 2-terminal, cantilever-type SiC NEMS switches operating from 25 °C to 600 °C, with threshold voltages ≤5 V, were designed, fabricated and characterized. These switches, fabricated by standard surface micromachining using a silicon dioxide sacrificial layer, are actuated electrostatically wherein a suspended cantilever electrode bends downward to contact a

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second electrode positioned on the substrate. The length, width and actuation gap of a typical switch are 10 µm, 5 µm and 75 nm, respectively. Sample switches operated more than 40 billion cycles at room temperature before failure. Typical contact resistance was

5 MΩ after the first several cycles of operation. Operation of these switches at 600 °C was verified, but cycles to failure could not be determined due to wire bond detachment from the contact pad prior to switch failure. Plausible models for the observed contact resistances are: (i) native oxide on the SiC electrodes for low applied voltages; and (ii)

Sharvin’s model for higher applied voltages.

Stiction of the switch electrodes during sacrificial layer release and later in operation is of critical importance and strongly correlated to the roughness of the contacting surfaces. 60% of switches with 8 nm roughness on the contacting surfaces could operate over billions of cycles, at which point the cantilever electrodes fractured at their support ends. In contrast, 85% of the switches with 1 nm roughness on the contacting surfaces were stuck after release.

To achieve all-mechanical computing, 3-terminal switches are required in order to have independent gate control. In this work, a 3-terminal SiC switch fabricated by E- beam lithography has been demonstrated to operate in the temperature range of 25 °C to

550 °C. Switches with length = 8 µm, width = 150 nm and gap = 200 nm have operated

21+ billion cycles at 25 °C and 2+ billion cycles at 500 °C. Moreover, inverter operation by connecting two 3-terminal switches at 500 °C has been demonstrated.

This thesis reports the electrical characteristics of inverter, NAND and NOR logic gates using 6H-SiC JFETs and capable of high temperature operation. The fabricated SiC inverter consists of three n-channel normally-on JFETs with -7 V threshold voltage. The

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unit transistor size is 160 µm wide and 10 µm long. Universal gates (NAND and NOR) are composed of four transistors. All logic gates operate in the temperature range of 25

°C to 550 °C. In addition to demonstrating logic operation, a SiC NOR gate is used to study the leakage current as a function of temperature.

Silicon dioxide/nitride/dioxide stack dielectrics deposited by PECVD have been developed here for the foregoing high temperature devices. Capacitors formed using these dielectric stacks show acceptable leakage current density (~1×10-4 A/cm2) under high electrical potential (e.g., 250 V) at 525 °C. On the other hand, capacitors formed by

PECVD silicon dioxide exhibit 10× higher leakage current density at 525 °C.

CHAPTER 1

Introduction

1.1 Motivation

One of the major challenges of the integrated circuits (ICs) industry is how to

effectively suppress the increasing leakage power consumption with aggressive

technology scaling. In fact, leakage power is predicted to constitute nearly 50% of chip

power beyond 65nm CMOS technology nodes. Existing circuit techniques for leakage

reduction either suffer from reduced effectiveness at nanometer technologies (such as

dual-Vth assignment, adaptive body biasing, etc. [1-2]) or affect performance and gate

oxide reliability (such as supply gating, multi-threshold-voltage CMOS, etc. [3]).

Mechanical switches have virtually zero leakage current in the OFF state since the conduction is based on physical contact of the switching terminals. Because of their potential to eliminate OFF-state power losses, switching systems based on nano- electrical-mechanical systems (NEMS) are of recent interest as an alternative to comparatively leaky electronics-based circuits – including in high temperature applications where leakage current in electronic devices increases markedly. NEMS switches are being explored for: (i) hybridization with transistors in order to shut off the leakage current in the OFF state in electronic logic circuits [4-7]; and (ii) realization of

all-mechanical logic circuits [8].

High temperature measurement and control instrumentation requires microcontrollers, in addition to sensors and interface electronics. Applications are, for example, in automobile and aerospace engines where the ambient temperature is usually higher than

300 °C. Instrumentation reaching 600 °C is particularly attractive because it can be moved closer to the point of use, enabling measurements otherwise not possible and reducing overhead associated with electronics cooling requirements. However, silicon- based technologies are quite limited for use above 300 °C since silicon is not a wide band gap semiconductor.

Because of its wide bandgap, high thermal conductivity, mechanical robustness and high electric breakdown field, we have pursued silicon carbide (SiC) as a platform material for sensors [9] and related interface electronics [10-12] for high temperature applications. One pathway to high temperature digital logic is to extend our analog SiC electronics to digital design. An alternative approach is to explore an all-mechanical digital design methodology, wherein SiC NEMS switches replace the transistors. In the latter approach, leakage current in the OFF state is substantially eliminated, and SiC’s excellent electrical and mechanical stability at elevated temperatures extend the operational temperature regime to 600 °C – and possibly beyond.

Therefore, this work is motivated to develop SiC high temperature logic gates based on NEMS switches or junction field transistors (JFETs).

1.2 Existing High Temperature Logic Devices

Though some commercially-available silicon logic circuits using silicon-on-insulator

(SOI) technology can extend operating temperature to 250 °C [13], applications like engines, spacecraft, and deep-well drilling require electronics working at even higher temperatures. At such high temperatures, the amount of intrinsic carriers in silicon excited by the thermal energy exceeds the amount of doped carriers and the device ceases to function properly. To this end, wide bandgap semiconductors like silicon carbide (SiC) and gallium nitride (GaN) have been of interest. Table 1.1 [14] lists physical and electrical properties of GaN and the three most commonly used polytypes of SiC (4H, 6H and 3C).

Figure 1.1 Typical GaN HEMT formed on a foreign substrate [15].

GaN Property 6H-SiC 4H-SiC 3C-SiC (Wurtzite)

Bandgap (eV) 3.0 3.23 2.36 3.39

Effective conduction band 8.9×1019 1.7×1019 1.5×1019 2.3×1018 density of states (cm-3)

Effective valence band 2.5×1019 2.5×1019 1.2×1019 4.6×1019 density of states (cm-3)

Density (g/cm3) 3.21 3.21 3.21 6.15

Relative dielectric constant 9.66 9.66 9.72 6.15

Thermal conductivity 4.9 3.7 3.6 1.3 (W/cm·K)

Electron mobility ≤ 400 ≤ 900 ≤ 800 ≤ 1000 (cm2·V-1·s-1)

Commercially available 4 4 N/A N/A wafer size (inch)

Table 1.1 Relevant electrical and mechanical properties of 6H-SiC, 4H-SiC, 3C-SiC

and GaN measured at 300K [14].

1.2.1 GaN Technology

Most GaN crystals can only be grown on other substrates (hetroepitaxy). Gallium-

nitride high electron mobility transistor (GaN HEMT) is widely used in satellite

transceivers, mobile phones, GPS-based navigation systems, and broadband wireless

networking systems. Recently, AlGaN/GaN HEMTs (Fig. 1.1) capable of high

temperature operation and formed on sapphire, Si and SiC substrates have been reported

[16-19]. In addition to developing transistors, GaN digital integrated circuits have been demonstrated as well. In 2007, Yong et al. [20-21] reported an AlGaN/GaN HEMTs based inverter and a 17-stage ring oscillator exhibiting reliable operation at 375 °C. A 31- stage ring oscillator working at 265 °C has also been achieved [22].

1.2.2 SiC Technology

Though forming single crystalline substrates is challenging for SiC, 4-inch SiC

wafers have recently become available [23]. As a result, much interest has focused on

SiC electronic platforms such as metal-oxide-semiconductor field-effect-transistor

(MOSFET), metal-semiconductor field-effect-transistor (MESFET) and JFET. Among

these three electronic device structures, SiC JFET is the most promising candidate for

high-temperature logic applications because lack of good quality gate-insulator has

limited the development of SiC MOSFETs [24-26]; Shottky-based MESFETs exhibit

notable gate-to-channel leakage at elevated temperatures.

Neudeck et al. [27] demonstrated operating NOR and NAND gates at 600 °C using

6H-SiC JFETs (Fig. 1.2). They subsequently showed a reliable NOR gate operation at

500 °C for more than 2000 hours [10]. The fabricated NOR gate was composed of three

W/L = 40 /10 µm transistors and three resistors. The input high (VIH) and low (VIL) were

-2.5 V and -7.5 V, respectively. VDD and VSS were +20 V and -24 V. Additionally, they

demonstrated more than 7000 hours of JFET operation at 500 °C with less than 10% degradation in linear I-V characteristics. A 6H-SiC JFET based inverter was also verified to work more than 3600 hours at the same temperature [28]. Note that during the first

2000 hours demonstration, although the leakage currents measured from JFETs decreased with increasing operating time (reason unclear), the power consumption during OFF state

was still considerable. In addition to 6H-SiC, 4H-SiC JFET based devices, with higher

bandgap and electron mobility, have also been used for logic applications. In 2007, a

resistive load n-type 4H-SiC JFET based inverter was reported [29]. This low-voltage inverter circuit operated at VIH = 3.2 V and VIL = 2 V with VDD = 4.1 V.

Overall, SiC JFET based logic devices have been verified to operate reliably at

elevated temperature. However, an issue needs to be addressed is how to effectively

suppress the leakage power consumption rising with the temperature.

Figure 1.2 6H-SiC JFET logic circuits [27]: (a) optical micrograph of a NAND gate;

(b) optical micrograph of a NOR gate; (c) test waveform of the NAND

gate at 600 °C; and (d) test waveform of the NOR gate at 600 °C.

1.3 State-of-the-Art Device Structures Based on NEMS

Switches

As discussed previously, in order to reduce leakage power, NEMS switches are explored for integration with electronics used to implement all-mechanical logic circuits.

Since NEMS switches have a nearly zero OFF-state leakage, they can possibly break the

energy efficiency barrier of conventional CMOS devices [30].

1.3.1 Suspended Gate MOSFET (SG-MOSFET)

The structure of the SG-MOSFET, as shown in Fig. 1.3 [4], is a combination of an

electrically-actuated gate with a MOSFET. The gate with supporting arms is physically

suspended over the channel area over an air gap. Figure 1.3(c) shows a fabricated SGFET

with four supporting arms [5]. The gate stays in the original not-deflected position (OFF state) in the absence of a gate bias; it deflects toward the underneath gate oxide layer when a voltage is applied. If the gate bias reaches a threshold voltage (VTH), the electrostatic actuation force overcomes the stiffness of the supporting arms, and as a result, the gate collapses onto the oxide layer (ON state) [31].

After the gate contacts the oxide, the current-voltage characteristics can be obtained using the conventional MOSFET model. Since the leakage current in the OFF state is only determined by the vacuum tunneling current [32], the NEMS-based device yields a superior ION/IOFF ratio. Simulation has shown that the NEMS-CMOS hybrid device

provides more than five orders of magnitude reduction in IOFF compared to a fixed-gate

accumulation-mode FET with the same ION [7]; hence, it is a promising direction for

ultra-low power circuits.

Figure 1.3 Schematics of [4]: (a) the structure of a SGFET; (b) the cross-section of

the device in OFF state; and (c) a SEM photo of a fabricated SGFET with

four supporting arms [5].

1.3.2 All-Mechanical NEMS Devices

The basic idea of an all-mechanical logic using NEMS switches is similar to the

SGFET discussed in the previous section. However, instead of forming a conducting

channel with gate bias, the ON state is a physical contact of two electrodes which

represent the source and the drain, when the gate bias is greater than the threshold voltage

(VTH), as shown in Fig. 1.4. Building block logic circuits are being developed in this

thesis based on a complementary NEMS (CNEMS) switch architecture. Figure 1.5

illustrates the basic layout of a NAND gate using the CNEMS architecture relying on electrostatically actuated cantilevers that deflect in the plane of the substrate. As will be seen, the CNEMS architecture can also be based on beams that deflect normal to the plane of the substrate.

To realize this proposed device structure, the material used as the switching component has to be robust with high wear resistance for high endurance. Carbon nanotubes (CNTs), metals and compound semiconductors are the three main material platforms utilized for this application. The following sections will introduce and discuss current developments and achieved performance of these three platforms.

It should be addressed here that even though NEMS switches can potentially operate at microwave frequencies [33-36], it is challenging to compete with the switching speed of CMOS technology. However progress can be made as the nano fabrication technique advances. In spite of the speed limitation of mechanical switches, Chen et al. [37] has demonstrated a 10× lower energy platform than CMOS by using NEMS-electronic hybridization.

Figure 1.4 Basic operation of CNEMS switches [10] (a) OFF state; and (b) ON state.

Figure 1.5 Layouts of a NAND gate based on the CNEMS architecture using four

nano-scale cantilevers (red beams in the figure).

1.3.2.1 Carbon Nanotubes

Due to their exceptional stiffness and current carrying ability, many designs and

related analytical models have been developed for CNT-based NEMS logic [8, 38-39]. In

2004, Lee et al. [40] demonstrated the first three-terminal NEMS switch based on multi-

wall carbon nanotubes (MWNT). The nanotubes were synthesized in cantilever geometry

by plasma enhanced chemical vapor deposition (PECVD), with switch air gaps of ~135

nm. The measured VTH was about 5 V, but it varied from device to device because the

placement of the CNTs was not reproducible. For example, some CNTs were suspended

with an angle toward the substrate resulting in a smaller gap. As shown in Fig. 1.6, a

doubly-clamped CNT NEMS switch has been reported as well [41]. A 100 nm gap was

achieved by releasing the Al sacrificial layer, and the device was turned ON when gate

bias exceeded 3.6 V.

In 2006, another group reported a single-wall carbon nanotube (SWNT) NEMS

switching device (Fig. 1.7) with ~20 nm gap in doubly-clamped geometry [42]. The

nanotubes were grown in a CVD furnace at 850 °C using Fe as the catalyst. The device

exhibited a VTH (i.e., the gate bias that turns the device ON) of less than 2.5 V.

Rueckes et al. [43] has demonstrated the concept of molecular computing using CNT based non-volatile random access memory with the potential of operating at a frequency exceeding 100 GHz. Their preliminary experimental data indicated that the device

5 exhibited a 10 RON/ROFF (resistance) and was reversibly switchable for several days.

Figure 1.6 SEM photo of a switch using a CNT. The length of the suspended CNT is

~800 nm [41].

(a) (b)

Figure 1.7 SWNT switch [42]: (a) global SEM photo; and (b) high magnification

image showing the CNT suspended over the pull-down electrode (trench).

1.3.2.2 Metals

Though the remarkable mechanical and electrical properties of CNTs make them an

excellent candidate for NEMS switches, the complexities of formation and placement of

these nanotubes make the fabrication process extremely difficult, i.e., reproducibility

remains challenging. From this point of view, approaches based on micro/nanofabrication

using process compatible switch materials like AlN, SiC and some metals are of interest.

Since the device operation is based on the physical contact of two electrodes, the high

conductivity of metals is an advantage for lowering switch contact resistance. In 2009, a

2-terminal tungsten NEMS switch using a doubly-clamped beam with a 50 nm gap was

demonstrated based on atomic layer deposition (ALD) [44].The measured threshold

voltage was about 5 V, and a life time in excess of 50,000 cycles was observed before

mechanical failure occurred. However, a significant leakage current (few nA) was

measured when the gate voltage was less than VTH, i.e., the switch was in the OFF state.

Tunneling current between the top and bottom electrodes was believed responsible,

though the current was much higher than the tunneling current that would be expected under the given parameters (50 nm separation and < 2 V bias). In this “low-current tunneling” regime, the device was operated more than 660,500 cycles. Based on the obtained data and finite element analysis (FEA), the switch structure was subsequently refined and a device life time greater than 5×106 cycles was achieved [45].

Czaplewski et al. [46] reported a single-pole double-throw ruthenium (Ru) NEMS switch with a 5 V threshold voltage using a CMOS-compatible fabrication process. The measured transition time was 400 ns and the leakage current was less than 20 fA.

However, the process yield was limited due to the complexity of nanofabrication, and the

reported device lifetime was about a million cycles.

1.3.2.3 Compound Materials and Compound Semiconductors

SiC, because of its excellent material properties, is of interest here for an all-

mechanical logic for applications at high temperatures using NEMS switches [47].

Specifically, polycrystalline (poly)-SiC holds valuable related advantages over polysilicon, silicon-germanium and common integrated circuits (IC) metals. First, for the same geometry, poly-SiC nano-beams have a resonant frequency that is 25% to 80% higher than polysilicon (based on the higher elastic modulus of poly-SiC), enabling faster

switches; silicon-germanium and common IC metals are inferior to polysilicon in this

respect. Second, poly-SiC is mechanically robust and chemically inert, enhancing long-

term operational reliability. In addition, SiC contacting micro-components have less

tendency of stiction, hence operational reliability is improved. This thesis reports the first

ever SiC NEMS switches capable of operation from 25 to 600 °C [48-49]. Switches have

operated more than 40 billion cycles at room temperature and more than 2 million cycles

at 600 °C with threshold voltages of less than 5 V.

Aluminum nitride (AlN) is another attractive compound material for NEMS due to

the ease of deposition and processing. A piezoelectric actuator with a leakage current

density lower than 2 nA/cm2 using ultra-thin (100 nm) AlN has been reported [50]. The vertically deflecting device exhibited a 116 nm displacement under 6 V. With the help of

a body-bias design, a 100 nm-thick AlN piezoelectric nano-switch with 1 mV threshold

voltage was subsequently demonstrated [51].

In 2008, a titanium nitride (TiN) cantilever-type NEMS switch with 20 nm air gap

was reported for high density non-volatile memory applications [52]. The device was fabricated using conventional “top-down” CMOS technology with a width = 200 nm, length = 300nm and thickness = 30 nm. Residual stress in the CVD deposited TiN was addressed by annealing. The measured threshold voltage was about 13 V. The device

5 exhibited a superior ION/IOFF ratio (>10 ) with a sub-threshold slope less than 3

mV/decade in air. As depicted in Fig. 1.8, a 15 nm gap was achieved by later using the

same device architecture and fabrication process [53]. Demonstration of several hundred

hours of operation was reported as well.

Figure 1.8 SEM photo of a TiN NEMS switch with a 15 nm air gap. The beam

deflection shown in the inset was caused by residual stress in the TiN

layer and was reduced by high temperature annealing.

1.4 Sacrificial Layers and Releasing Techniques

In NEMS switches, the threshold voltage is determined by the spring constant of the

supporting arms/cantilever and the gap size between the activated electrodes. While most

RF MEMS switches require 20-80 V for reliable operation [54], a 10 nm switch gap is

needed in NEMS switches [55] to achieve CMOS-compatible threshold voltages (less

than 5 V). In micromachining, gaps are usually formed by selectively removing a

specific material called sacrificial layer. Polyimide, polysilicon, amorphous silicon and

SiO2 are most commonly-used materials for this purpose. However, in comparison to

most micromachined devices typically having a few micrometer gaps, realizing a nano-

scale gap is more challenging. Very thin sacrificial layers are more prone to pinholes and

other defects. Very small gaps lead to contacting surfaces during fabrication release,

aggravating stiction, a problem caused by the high adhesion force between two

contacting micromachined surfaces [56]. When a device is removed from the aqueous

solution after wet etching of an underlying sacrificial layer, the capillary force pulls the

microstructure towards the substrate or the adjacent surface and stiction occurs. In addition, the in-use stiction caused by short range van der Waals force after contact of the

surfaces is another obstacle [57].

1.4.1 Silicon Dioxide

Silicon dioxide (SiO2) has been used as a sacrificial material in a wide range of

micromachined devices, e.g., pressure and inertial sensors. It can be grown thermally on

silicon and SiC. For materials or processes with limited thermal budget, low-temperature-

oxide (LTO) and PECVD oxide can be used for lower processing temperatures. However, conventional HF or BOE wet etching release often results in sever stiction problems when the gap is reduced to the sub-micron range. To address this problem, supercritical

CO2 release technique can be used to reduce the capillary force induced from the drying process. Our laboratory has demonstrated a laterally-actuated SiC NEMS switch with 150 nm gap released by this method; the switch exhibits reproducible, long-term switching of billions of cycles without sticking. Dry HF vapor release is another promising way to etch the SiO2 sacrificial layer without inducing stiction [58-59]. Initial work of this thesis

has demonstrated reliable switching operation of a vertically-actuated SiC cantilever with

75 nm gap released by HF vapor. HF vapor, however, affects silicon nitride (Si3N4) and

leaves a residue [60]. Since Si3N4 is the most commonly used etch stop layer, developing

a new material inert to this corrosive release agent is crucial. As shown in Fig. 1.9, initial

work [61-62] has demonstrated that PECVD a-SiC is a suitable material for this application. Our results indicated that the PECVD a-SiC film, while being electrically insulating, exhibits excellent chemical resistance to liquid/vapor HF, KOH, and TMAH.

In addition, the low deposition temperature (350 °C) makes it suitable for process integration with a range of materials.

1.4.2 Silicon and Organic Materials

The conventional KOH or TMAH wet etching of a polysilicon sacrificial layer is not optimal for NEMS switches because of the adhesion problem during the release drying process. Similar to SiO2 release drying, critical point drying process can be applied in this case to address this problem.

(a)

(b)

Figure 1.9 SEM photos showing (a) a blanket coated silicon nitride film after vapor

HF etch evidencing an abundance of etch residues on the film surface; and

(b) a clean surface of amorphous SiC after 30 minutes of HF vapor etching,

also evidencing that the underneath SiO2 layer is well protected.

Because of simplicity in processing, SF6 or XeF2 plasma dry etch have been widely used in polysilicon and amorphous silicon releasing [63-64]. For some materials like silicon [65], dry etch can prevent the liquid meniscus formed on the hydrophilic surfaces.

Oxygen plasma can be utilized to remove organic sacrificial layers, like polyimide and

PMMA [66]; however, it oxidizes the surface.

It should be noted here that in order to achieve nano-scale gaps, other materials are sometimes chosen as the sacrificial layer for ease of integration of the fabrication process.

The typical releasing procedure is to wet etch such other materials (not all materials used as sacrificial layer have a corresponding dry etch), followed with critical point drying.

For example, in the tungsten NEMS switch mentioned in the previous section, Ni was used as a sacrificial layer and was released by Transene thin-film-B (TFB) Ni etchant

[44].

1.5 Summary of Developed NEMS switches

Table 1.2 shows a comparison of some NEMS switches with different actuation mechanisms, sacrificial layers and their reported threshold voltage. Most devices have achieved a ≤5 threshold voltage; the gap size is usually smaller than 100 nm.

Sacrificial Ref. Structural Layer / Releasing Reported Geometry Number Material Thickness Technique VTH (V) (nm) [40] Cantilever CNTs PMMA / 135 Oxygen Plasma 5 Doubly-clamped [41] CNTs Al / 100 Al wet etching 3.6 Beam Doubly-clamped PECVD [42] CNTs N/A 2.5 Beam TEOS / 20 Ni wet etching Doubly-clamped [45] Tungsten Ni / 50 + critical 5 Beam drying MEMS/CMOS [37] Si Ge SiO / 200 nm Vapor HF < 2 Hybridization 0.4 0.6 2 Cantilever / Wet etching + [52] Doubly-clamped TiN Si / 20 13 critical drying Beam Cantilever / Wet etching + [53] Doubly-clamped TiN Si / 15 13 critical drying Beam Wet etching +

[48] Cantilever SiC SiO2 / 75 critical drying / < 5 Vapor HF

Table 1.2 A summary of recently developed NEMS switching devices.

1.6 Reliability Issues

Unlike electronics, MEMS/NEMS switches suffer from mechanical effects, e.g., wear, friction, and fatigue. Additionally, switches can experience adhesion (stiction) failure induced during releasing process or during operation. The following sections will briefly introduce the abovementioned reliability challenges and some developed techniques to address them.

1.6.1 Fatigue and Wear

Fatigue and wear happen naturally because the operating mechanism of these devices

is based on the physical contact of two (or more) mechanical elements. After a certain

number of cycles, the accumulated stresses initiate a crack in the region of high stress and

eventually result in the device fracture. Figure 1.10 shows the typical mechanical failure

of a tungsten NEMS switch due to mechanical fracture after ~ 300 cycles [45]. However,

it is found that the conventional fatigue theory based on bulk materials is not applicable

to MEMS/NEMS scale due to the high surface-to-volume ratio and surface effects [67].

Although there is still lack of models for predicting fatigue behavior in MEMS/NEMS

devices, it is believed that lower cyclic (operating) stress leads to longer device lifetime.

The contact resistance usually increases due to deformation of the contact area caused

by wear and friction. Tribocompounds, like oxides, soaps and polymers, formed by the

thermal energy induced from friction can also contaminate the surface and, as a result,

further increased the contact resistance [68-69]. Once the contact resistance exceeds the

designed tolerance, the performance degrades. More specifically, for a NEMS switch, the 24

ION/IOFF ratio of a NEMS switch will decrease due to the higher contact resistance. Using

structure materials or thin film coatings with high wear resistance (e.g., SiC or W) is an

approach to overcome the wear challenge [70-71].

Figure 1.10 SEM photo showing the mechanical failure of a tungsten NEMS switch

fabricated by ALD [45]. The length, width and thickness of the beam are

2000 nm, 700 nm and 32 nm, respectively.

1.6.2 Adhesion

Stiction can be divided into two categories, i.e., during releasing and in-use. The

former has been discussed in Section 1.4. Generally speaking, the in-use stiction occurs

due to the high interaction energies between two surfaces; these energies include

capillary, van der Waals and Casimir forces [72]. For instance, when a cantilever-type

capacitive switch is actuated by an electrostatic force, the interface forces between the

two electrodes might overcome the restoring (elastic) force of the cantilever, and as a

result, the two surfaces are in contact permanently. van der Waals force is believed to be

the dominating adhesion force for MEMS devices; its interaction energy per unit area can

be defined as,

(1-1)

where A is the Hamarker constant and g stands for the distance between the two surfaces.

More recently some studies suggest that Casimir effect also plays an important role when

the device is miniaturized; its energy per unit area is expressed as [73],

2 ћ (1-2) 7203

where ћ is the Planck’s constant divided by 2π and c is the speed of light. Though it is challenging to distinguish the contributions of these interaction forces, modifying the surface to a less energetic state avoids the in-use stiction problem.

To achieve high device endurance, surface coating is often used on the contacting surface to lower its surface energy. Pott et al. [71] demonstrated that using a coating of ultra-thin TiO2 layer deposited by atomic layer deposition, NEMS switches with tungsten

contact electrodes exhibited a lifetime more than 109 cycles. By adding ammonium fluoride (NH4F) in HF, the surface energy of polysilicon can be tailored during release

(oxide removal) and the device reliability greatly improved [65, 74].

1.7 High Temperature Dielectric

The development of high temperature logic devices require reliable dielectric layer

for electrical isolation. There are very few reported studies investigating high temperature

dielectrics. Most dielectrics are developed for silicon technology platforms, tested at most

to 250 °C.

In 1999, a study investigated various dielectric materials including silicon dioxide,

silicon dioxide/nitride/dioxide (ONO stack) and AlN to improve high temperature

reliability [75]. Results indicated that the ONO stack showed a superior dielectric

strength to other tested materials at elevated temperatures. In addition, a metal-insulator-

semiconductor (MIS) capacitor based on ONO stack showed 10 days lifetime at 335 °C

under 15 V bias (10× longer than a device built up by oxide). Other published data [76-

78] also suggest the ONO stack to be a suitable dielectric for non-volatile RAM

applications.

Though the ONO stack seems promising for the high temperature SiC logic devices,

no data has been presented regarding its properties and stabilities at 400 °C and beyond.

To this end, we have designed and fabricated metal-insulator-metal (MIM) capacitors using ONO stack to examine its potential for high temperature application. The measured dielectric properties as a function of temperature are described in Chapter 6.

1.8 Thesis Organization

The objective of this thesis is to pursue SiC high-temperature logic with low leakage

power consumption by: (i) hybridization of SiC electronics with 2-terminal SiC NEMS

switches; and (ii) all-mechanical computing using 3-terminal complementary SiC NEMS

switches. This thesis is organized into seven chapters. Chapter 1 gives a brief

introduction about the state-of-the-art high temperature logics and their limitations.

Chapter 2 discusses the design considerations, simulations and fabrication process of

vertically-actuated 2-terminal SiC NEMS switches. Threshold voltage, contact resistance,

and failure mechanism of the 2-terminal SiC NEMS switches are described in Chapter 3.

Chapter 4 presents all-mechanical high temperature logic using 3-terminal

complementary SiC NEMS switches. Chapter 5 demonstrates logic gates capable of high

temperature operation using 6H-SiC depletion-mode JFETs. The source-to-drain and

gate-to-channel leakage currents as a function of temperature are discussed in this chapter. Silicon dioxide/nitride/dioxide stack dielectrics deposited by PECVD have been

reported in Chapter 6 for the SiC high temperature devices. The leakage current and

dielectric strength of these dielectric stacks are discussed as a function of temperature.

The key accomplishments of this thesis are summarized in Chapter 7.

CHAPTER 2

Design and Fabrication of 2-Terminal Poly-SiC

NEMS Switches

2.1 Introduction

To reduce leakage current, a first step would be to develop 2-termial switches that can be hybridized with electronics. In these switches, the ON and OFF states are physically controlled, therefore the leakage current at OFF state is nearly zero. As discussed earlier, the threshold voltage for the switch should be consistent with the threshold voltage (VTH) of the electronics. In this work, a cantilever-type 2-terminal SiC NEMS switch, actuated electrostatically, is demonstrated. The intended electronics for hybridization are JFET- based SiC integrated circuits (ICs) used in high temperature applications, discussed later in this thesis. For most SiC ICs, the threshold voltage is in the range of ±5 to ±10 V. To this end, the designed SiC NEMS switch should have a VTH less than 10 V. In high

temperature applications, power management for energy efficiency and reduction of

cooling provisions, is more important than switching speed because for example,

developing high temperature power sources (like battery) is a challenge.

This chapter describes the development of the 2-terminal, cantilever-type SiC

switches. Design considerations for achieving the desired VTH are discussed. The

fabrication process, including preparation of the requisite SiC films used as the structural

layer, is presented.

2.2 Design Criteria

The performance of NEMS switches strongly depends on the device dimensions,

including the actuation gap. For electrostatically-actuated switches, operating voltage and

switching time are adjusted primarily by varying the actuated beam’s length and

thickness. The overlapping area of the opposing surfaces that engage in actuation can be

used but has a comparatively less impact. More specifically, the dimensions of the

suspended cantilever determine the mechanical behavior, while the actuation force is

related to the gap and overlap area dimensions. The mechanical behavior can be modeled

by the well-known Hooke’s law:

∙ (2-1)

where F, k and x are applied force, spring constant and deflection of the cantilever,

respectively. The following sections will discuss the effect of these parameters on the

switch performance.

2.2.1 Spring Constant and Resonating Frequency of Cantilever

Assuming the distributed electrostatic force is uniform along the beam, and the beam

is initially flat, the spring constant of a cantilever can be expressed as:

(2-2)

where E , I and L are Young’s modulus, moment of inertial and beam length,

respectively. Moment of inertial is expressed as:

(2-3)

where w and t are beam width and thickness, respectively. For a given cantilever

dimension, its resonating frequency (f) is given by:

(2-4)

Here, ρ is the density of the cantilever structural material. Equation (2-4) shows that for

the same dimensions, a SiC cantilever has a higher resonating frequency than silicon, i.e.,

due to the higher value.

2.2.2 Threshold Voltage

For actuation, an electrostatic force is generated between the two electrodes of the

NEMS switch to overcome the restoring force of the cantilever beam. Just like two

parallel plates separated by air with a distance g, the electrostatic force generated by an applied electrical potential V for a cantilever-type switch is:

2 1 2 0 (2-5) 2 22

where C is the capacitance between the two electrodes, and ε0 and A stand for the

permittivity of vacuum and the overlap area of the electrodes, respectively. When the

cantilever tip deflects slightly (i.e., due to an applied voltage across the electrodes), the

separation distance changes to x. The force equilibrium between the electrostatic force

and the elastic force of the beam can then be written as,

(2-6)

(2-7)

It can be seen clearly from Eq. (2-6), when the deflection increases, both restoring

(elastic) force and electrostatic force also increase. However, an instability occurs at x =

2/3g and results in the spontaneous pull-in the cantilever. This happens because the increment in electrostatic force is larger than that in the elastic force at this tip position

[79]. Thus, the threshold voltage (VTH) of the switch can be approximated by:

= (2-8)

By putting Eqs. (2-2) and (2-3) into Eq. (2-8), it is clear that the beam length, thickness,

and the gap size are the dominating factors in determining the VTH.

(2-9)

Though smaller threshold voltages can be achieved using longer cantilevers, it results

in lower resonating frequencies, i.e., slower switching speeds. Therefore, there is a

tradeoff between low switching energy and high speed. As stated earlier, for high temperature applications, it is more important to manage power than speed. A possible way to reduce the VTH without affecting the speed is to shrink gap size. For a

polycrystalline 3C-SiC (poly-SiC) switch with length = 10 µm and thickness = 100 nm,

the calculated VTH can be lowered from 5.4 V to 1.9 V by reducing the gap size from 200

nm to 100 nm.

2.2.3 Switching Time

The switching speed of a NEMS switch is dominated by the resonating frequency and the damping of the environment. A simple calculation can be performed to predict the switching time (ts) [8]:

(2-10)

where g and L have been defined previously. ω is the resonant frequency in radians and can be expressed as,

(2-11)

Here, m is the mass of the cantilever.

Another proposed model for the switching time is to solve d' Alembert’s equation of motion [79]:

(2-12)

Ignoring the damping effect (i.e., set b = 0), the solution is obtained by putting Eq. (2-5) into Eq. (2-12) and x = g.

. (2-13)

2.3 Dimensions of the Designed 2-Terminal SiC NEMS

Switches

The proposed SiC NEMS switch is fabricated by optical lithography. Therefore, the

smallest feature size is limited by the capability of the exposure tool (Karl Suss

MA6/BA6) which is about 2 µm here. In spite of the micro-scale length and width of the

cantilever, the beam thickness and the gap size are controlled by film deposition and can

be controlled quite well, even for submicron thickness. Table 2.1 lists the range of the dimensions of the SiC NEMS switches presented in this work, as well as a few other key parameters.

Beam length (L) 3 – 10 µm

Beam width (W) 2 – 5 µm

Beam thickness (t) 100 nm

Gap (g) 75 nm

Young’s Modulus 330 GPa

Density 3300 kg/m3

Table 2.1 Key design parameters for the vertically-actuated SiC NEMS switch and

some important material properties of SiC used in this chapter.

Figure 2.1 shows simulation results for beam deflection under an applied DC voltage using COMSOL Multiphysics finite element analyzing (FEA) [80]. The dimensions of the simulated switches were L = 6 ~ 10 µm and W = 5 µm. As shown in Fig. 2.1, devices with shorter beam lengths require higher threshold voltages. The negative deflection values indicate downward motion of the cantilever. In all cases, the beams snap to the bottom electrode after a deflection of 25 ~ 30 nm, which is about 1/3 of the total gap size, consistent with the model discussed in Section 2.2.2.

L = 10 µm L = 9 µm L = 8 µm L = 7 µm L = 6 µm 0

-15

-30

-45 Deflection (nm) Deflection

-60

-75 00.511.522.5 Voltage (V)

Figure 2.1 Deflection versus applied voltage simulation results for SiC NEMS

switches of varying lengths.

2.4 Fabrication Process

The fabrications process (as depicted in Fig. 2.2) for the vertically-actuated switches

uses a silicon wafer, electrically isolated with a 300 nm-thick silicon nitride film (Fig.

2.2(a)). Atop the nitride film, the bottom electrode is formed by low pressure chemical

vapor deposition (LPCVD) of a nitrogen-doped poly-SiC film using a thickness of 300

nm; the film is subsequently patterned by reactive ion etching (RIE) in CHF3 and O2 using photoresist as etching mask (Fig. 2.2(b)). The actuation gap is determined by a ~75 nm-thick SiO2 layer grown thermally on the poly-SiC bottom electrode, in which a

window is defined to anchor the top cantilever electrode (Fig. 2.2 (c)). A 100 nm-thick poly-SiC film is then similarly deposited and patterned (Fig. 2.2 (d)) to form the 10 µm- long, 5 µm-wide beam that, after a sacrificial release of the oxide (Fig. 2.2 (e)), serves as the suspended cantilever electrode. To avoid stiction during releasing given the very small actuation gaps, vapor HF is used instead of the conventional BOE or HF etching.

The key processing techniques are presented in the following subsections.

Figure 2.2(a) A 300 nm-thick, low-stress silicon nitride layer is deposited on a silicon

substrate.

Figure 2.2(b) A 300 nm-thick layer of poly-SiC is deposited using LPCVD and

patterned by standard lithography and etched by reactive ion etching (RIE).

Figure 2.2(c) A 75 nm-thick layer of sacrificial SiO2 is grown thermally, and an anchor

window is patterned in the sacrificial oxide.

Figure 2.2(d) Another layer of poly-SiC is deposited by LPCVD to a thickness of ~100

nm. The poly-SiC is patterned by standard lithography and etched by RIE

to define the top electrode cantilever beam.

Figure 2.2(e) Sacrificial oxide is removed by vapor HF.

2.4.1 Deposition of Poly-SiC Thin Film

20 -3 A low stress, heavily-nitrogen doped (ND ~ 10 cm ) polycrystalline 3C-SiC (poly-

SiC) film is deposited in a horizontal, hot-wall LPCVD reactor using SiH2Cl2 and C2H2 as precursors and NH3 as the doping gas. The deposition recipe is presented in Table 2.2

[81]. The film shows strong (111) orientation, and the microstructure does not change by

annealing up to 1000 °C, which is well above the requirements of high temperature

applications (up to 600 °C). For film thicknesses less than 500 nm, the surface roughness

is about 8 nm (Ra); the film becomes rougher with increasing film thickness.

Pressure 3 – 5 Torr

SiH2Cl2 35 sccm

C2H2 180 sccm (5% in H2)

NH3 16 – 100 sccm (1% in H2)

Deposition Temperature 900 °C

Table 2.2 Process parameters for LPCVD SiC deposition.

2.4.2 SiC Dry Etching

Due to its excellent chemical inertness, it is very difficult to pattern SiC by wet

etching. To this end, RIE was used to pattern the top and bottom SiC electrodes using a

mixture of CHF3 and O2 diluted in He. This step was conducted in a commercial plasma etcher (RIE-8000, Technics). The RF power was set to 400 W; the flow rates of CHF3

(Freon 23), O2, and He were 10, 25, and 10 sccm, respectively. The etch mask was

photoresist (AZ 9245). A possible chemical reaction describing Si and C atoms removed

during the dry etching in fluorinated gases and oxygen environment has been reported in

[82]:

Si + m F → SiFm (m = 1 ~ 4) (1)

C + m F → CFm (2)

C + n O → COn (n = 1 ~ 2) (3)

SiC + m F + n O → SiFm + COn + CFm (4)

During the etching process, the chamber was maintained at a pressure under 220 mTorr.

The average etching rate of the poly-SiC film was about 25 nm/min.

2.4.3 Oxidation of Poly-SiC

One of the most attractive features of SiC is the fact that its native oxide is SiO2, which can be formed using the same technology developed for silicon. As described previously, the thickness of the sacrificial layer (gap size) has a significant influence on the performance of NEMS switches; it typically has to be less than 100 nm for the desired low threshold voltage. To this end, dry oxidation was performed to grow an ultra-thin layer of high quality SiO2 on the SiC films. The reaction is described as [83],

SiC + O2 → SiO2 + CO2 (1)

The oxidation process was conducted at 1050°C for 4 hours, and a 75 nm-thick SiO2 layer was obtained. Similar to silicon oxidation process, SiC serves as the silicon source for SiO2, i.e., the thickness of the underneath SiC layer will decrease during oxidation.

2.4.4 Vapor HF Release

As shown in Fig. 2.3, vapor HF releasing was performed in a fume hood using a

flexible resistor heater. We have successfully demonstrated free standing cantilevers over

the 75 nm actuation gap for varying beam lengths from 2 to 100 µm. To accomplish this,

the temperature of the device surface was set 12 °C higher than room temperature during

the release in order to prevent water condensation on the device surface. During the releasing step, we did observe the residue layer discussed earlier. Given that the etching

time was short because the thin (75 nm) sacrificial layer, the formation of this residue did

not affect the operation of the devices. However, as stated in Section 1.4.1, PECVD SiC is a promising replacement for the silicon nitride insulator.

Figure 2.3 Schematics of the customized set up for vapor HF releasing.

CHAPTER 3

Characterization of the 2-Terminal SiC

Switches

3.1 Introduction

This chapter reports the performance of the fabricated 2-terminal SiC NEMS switches from room temperature to 600 °C. Current-voltage (I-V) behavior, is measured using a

Keithley Source-Measurement-Unit (SMU). Threshold voltage is extracted from the measured I-V curve. Contact resistance is measured as a function of applied voltage and modeled by Sharvin’s contact theory. The effect of the existence of a thin SiO2 layer on contact behavior is also included. Maximum operation cycle and failure mechanism are studied. In addition, the effect of roughness of the switch contacting surfaces on reliability is discussed.

To improve the conductivity of the SiC switch’s contacting surface, XeCl laser is used to graphitize the SiC surface. The laser-treated surface is then analyzed by optical microscopy (OM), atomic force microscopy (AFM), confocal microscopy and transmission-electron-microscopy (TEM) observations, as well as X-ray photoemission spectroscopy (XPS) studies.

(a)

(b)

Figure 3.1 SEM photos of: (a) a 10 µm-long, vertically-actuated SiC NEMS switch

with 75 nm gap; and (b) focus ion beam section of the highlighted white

rectangle in (a).

3.2 I-V Characteristics as a Function of Temperature

Most data shown below was obtained from a 10 µm-long SiC NEMS switch with 75

nm gap, as shown in Fig. 3.1. Temperature testing up to 400 °C was performed on a

probe station with a customized hot stage, as shown in Fig. 3.2(a). For 600 °C testing,

device were packaged in a ceramic package and heated in a tube furnace (Fig 3.2(b)). All measurements were conducted in room air and at atmospheric pressure.

To examine the threshold (also referred as pull-in) voltage VTH, the top and bottom

SiC electrodes were subject to a DC voltage sweeping from 0 V. When the applied

potential reached VTH, the top SiC cantilever was actuated and contacted the bottom

electrode, resulting in a detectable current passing through. Similar techniques have been

used to characterize other reported NEMS switches [41-42]. The measured VTH was 10-

15 V for the first several cycles; subsequent cycles, however, exhibited VTH of less than 5

V – a value that remained consistent up to 600 °C, as can be seen in Fig. 3.3. We believe

that after the first several cycles, the native oxide layer on the SiC surface (discussed later) undergoes soft dielectric breakdown [84-86], resulting in a finite resistance and measureable current flow at lower VTH.

Switches operated more than 40 billion cycles at room temperature and more than 60

million cycles at 400 °C. Additionally, a vertical switch was actuated more than 2 million

cycles at 600 °C at a frequency of 10 kHz before the aluminum bonding wire failed. It was thought that the aluminum wire should withstand the tested temperature range given that the melting point of aluminum is about 660 °C. It is likely that joule heating, defined as I2R, during the device operation further increased the temperature and expedited the

failure.

To measure the lifetime of the SiC NEMS switches, a Labview program was used to measure the ON current with a sampling rate of 5 MHz. If the variation in ON current exceeded 10% (i.e., the I-V behavior of the switch varied more than 10%), the program was designed to stop testing and report the number of cycles of operation. However, the measured change in the ON current of the 2-terminal SiC switches was always smaller than 10%, even for the devices that operated more than 40 billion cycles. The Labview program stopped primarily due to stiction and beam fracture.

(a)

(b)

Figure 3.2 Test set up for: (a) measurement between 25 °C and 400 °C; and (b)

measurement at 600 °C.

25°C 400°C 200

160 120

80 40 Current [nA] 0

02468

Voltage [V]

(a)

600°C

2.5 2

1.5

1 0.5 Current [nA] 0 02468

Voltage [V]

(b)

Figure 3.3 I-V characteristics showing (a) room temperature and 400 °C operation

and (b) 600 °C operation.

3.3 Surface Oxide

X-ray photoemission spectroscopy (XPS) studies (Fig. 3.4) revealed that the surface

was almost oxide free right after HF etching. However, a 1 nm-thick native oxide layer

was formed on the poly-SiC surfaces—and thus, the device’s contacting surfaces—

during exposure to a room-temperature air for 1 hour. As expected, the thickness of this

native oxide layer increased with increasing measurement temperature (in room air). The

thickness exceeded 6 nm after testing at 400 °C for about 25 minutes. This thin oxide

layer leads to a high contact resistance. The thicker oxide layer formed at the higher operating temperatures leads to a lower ON current, as seen in Fig. 3.3.

Subsequent experiments showed that the oxidation phenomenon can be greatly improved by testing the device in a nitrogen environment. Hence, native oxiede complication can be addressed by vacuum or hermatic packaging of the devices.

After 400°C testing t= 6.1 nm

After 25°C testing t= 0.77 nm

After release t= 0.12 nm

Figure 3.4 XPS data showing the evolution of native oxide on the poly-SiC surface

with increasing temperature.

3.4 Contact Resistance

Extracted from the I-V data in Fig. 3.3, for a 10 µm-long switch with a 75 nm gap,

the contact resistance is about 5 MΩ at 10 V and 2 MΩ at 15 V after the first few cycles,

which is higher than that for common metal-based switches. In MEMS/NEMS switching devices, the contact resistance (Rc) depends primarily on: (i) the resistivity of the material

coming into contact; and (ii) the radii of contact asperities (rC). With regard to (i), the

native oxide layer (discussed in the previous section) dramatically increases the contact

resistance. As for (ii), the contact force increases with increasing actuation voltage,

resulting in a lower contact resistance.

rc is proportional to the contacting force [87], which is determined by the applied voltage. This explains the voltage-controlled behavior of the measured contact resistance as seen in Fig. 3.5. Given that the calculated rc of the switch is smaller than the electron mean free path in SiC, instead of the Maxwell spreading resistance, Sharvin’s formula

[88] is used to model the contact resistance of the fabricated switch:

(3-1)

where ρ and l denote the resistivity and electron mean free path of SiC, respectively.

At higher actuation voltages (e.g., 12 V to 17 V), Sharvin’s model fits the

experimental data well (Fig. 3.6). For actuation voltages less than 10 V, however,

calculated contact resistance values are much lower than measured values. We believe

that at lower actuation voltages (e.g., 5 V to 11 V), the surface native oxide resistance

(ROX) dominates, even though the oxide has undergone soft breakdown. The concept of

soft breakdown was first introduced in 1990’s when ultra-thin (< 5nm) SiO2 was intensively studied for high density logic devices [89-94]. Compared to hard breakdown, the leakage current of ultra-thin SiO2 after soft breakdown is much smaller (i.e., the

resistivity is higher) at low applied bias. The measured contact resistance in this low

voltage region can be defined as the sum of the resistance from the contacting area and

the resistance of the thin oxide layer.

+ Rox (3-3)

and

2 (3-4)

where ρox and t are resistivity and thickness of the oxide layer, respectively. At higher actuation voltages, the post-breakdown native oxide behaves like a voltage-controlled resistor, following a power law [91] and can be described by:

∙ (3-5)

The power law behavior of the ultra-thin oxide after soft breakdown can be explained

by the percolation theory of nonlinear conductor networks with a distribution of percolation thresholds [95]. When the oxide layer is under electrical stress, electron traps are generated in this oxide layer and at its interface. Degraeve et al. [96] reported that when the distance between two electron traps is less than 0.9 nm, electrical conduction becomes possible through these traps and the current can be expressed as,

ν (3-6)

where σab and ν are the bound conductivity and electron drift velocity, respectively. As

illustrated in Fig. 3.7, when the density of electron trap reaches a critical value, a

conduction path may be created to trigger the soft breakdown event. It is believed that

there are multiple percolation thresholds (paths) contributing to conduction when the

ultra-thin oxide layer is under constant current or voltage stress. Roux et al. [95] have

studied the percolation theory in a disordered system. They have reported that if the I-V

behaves quadratically between two sites of the lattice (i.e., two electron traps), as stated

in Eq. (3-6), the relation between leakage current and applied voltage of the whole system

follows a power law. Extracted from the log I-log V plot (Fig. 3.8), the c and d values

-12 were 10 and 6, respectively. ROX can be neglected at higher actuation voltages (> 20

V), and the contact resistance is determined purely by the contact asperities and

materials.

Contact resistance can be expressed in terms of the contact force, F [97],

∝ (3-7)

Using the Holm contact model [97], b = 1/3 and 1/2 when contact asperities undergo elastic and plastic deformation, respectively. The b value approaches unity when the contact force is sufficiently large, and the contact resistance is dominated by surface condition of the contact material. As seen from Fig. 3.9, the b value is very close to 1, suggesting that the contact resistance in this region (voltages greater than 20 V) is determined by surface contamination.

400

] Ω 300

200

100

Resistance [M 0 0 5 10 15 20 25 30 Voltage [V]

Figure 3.5 Contact resistance as a function of applied voltage.

Caculated Measured 4

] Ω 3

2 1

0 Resistance [M 11 13 15 17 19

Voltage [V]

Figure 3.6 Comparison of measured contact resistance with those calculated using

Sharvin’s model.

Figure 3.7 Schematic showing a conduction path formed by electron traps (shaded) in

the SiO2 layer.

-7.3

-7.4

-7.5

-7.6 log I -7.7

-7.8

-7.9 0.68 0.7 0.72 0.74 0.76 0.78 0.8 log V

Figure 3.8 Log I versus log V plot used to calculate the coefficients of the I-V power

law for post-breakdown SiO2.

1 ]

Ω 0.8

0.6 Resistance [M 0.4 19 21 23 25 Voltage [V]

Figure 3.9 Contact resistance can be expressed in terms of contact force. For voltages

higher than 20 V, contact resistance is almost inversely proportional to

contact force.

3.5 Failure Mechanism

Compared to electronics, NEMS switches usually exhibit a shorter operational

lifetime since the operating mechanism is physical contact. As stated in Chapter 1,

mechanical fatigue and stiction are the two causes affecting the operating lifetime and

reliability of NEMS switches. During the testing of the 2-terminal SiC NEMS switches,

both failure mechanisms were observed. Stiction of the switch electrodes during

fabrication and in operation is strongly correlated to the roughness of the contacting

surfaces. On the other hand, device fracture occurs after a large number of switching

cycles (usually > billion cycles).

3.5.1 Effect of Surface Roughness on Stiction

Previous studies have indicated the surface interaction forces, such as capillary force,

electrostatic force and van der Waals force are the dominating factors for stiction [98]. It

is also well known that the roughness of the contacting surfaces strongly affects stiction.

Yee et al. [99] demonstrated the work of adhesion between two polysilicon surfaces can be greatly reduced by roughing the surface. Though some analysis models already take the roughness into account [100-101], it is still difficult to predict or calculate the adhesion energy accurately. To this end, we have verified the effect of the roughness experimentally.

Switches with different roughness (Ra) on the SiC electrode contacting surface were fabricated, released and tested at room temperature to study this correlation. As stated

previously, the as-deposited film has a roughness of 8 nm for the thickness here. To tailor 59

the surface roughness, chemical-mechanical polishing (CMP) was performed (using

Logitech PM5) on the as-deposited films, obtaining Ra = 5 nm and Ra = 1nm films after

40 and 90 minutes polishing, respectively. All surface roughness values were confirmed

by atomic force microscopy (AFM), as shown in Fig. 3.10. The polishing step was

performed after the deposition of the lower electrode SiC film and prior to its patterning.

The roughness of the under-surface of the top electrode follows the roughness of the

surface of the lower SiC electrode, given that the thermally-grown sacrificial oxide is

very thin, conformal and smooth.

For each Ra, 20 identical switches with length = 10 µm and width = 5 µm were

tested. 85% (17 switches) of the switches with Ra = 1 nm were stuck to the bottom

electrode right after release. 65% of the switches with Ra = 5 nm experienced the same

failure. For switches with Ra = 8 nm, 90% of the switches released successfully and

operated at least 1 million cycles. Figure 3.11 presents the data for the failure

mechanisms of the switches for each Ra. Figure 3.12 presents data for switches with Ra =

8 nm that failed after billions of cycles of operation due to fracture. A plausible

explanation of the relation between surface roughness and stiction is as follows. In a

NEMS switch with a smoother contacting area, the average distance (Dave) between the

non-contacting portions is much shorter than that with rougher contacting surfaces

(see Fig. 3.13) [57]. Given that the van der Waals force is inversely proportional to

square of the distance (see Eq. 1-1), switches with smaller roughness on their contacting

surfaces experience a higher adhesion force, and as a result, their reliability affected more by stiction.

(a)

(b)

Figure 3.10 Obtained z-height schematics from AFM measurements of device surfaces

with: (a) Ra = 1 nm; (b) Ra = 5 nm; and (c) Ra = 8 nm (unpolished). The

scanned size was 10 µm × 10 µm.

(c)

Figure 3.10 Continued.

Figure 3.11 Data from testing at room temperature for 20 switches, each with different

electrode contact surface roughness: (a) 1 nm; (b) 5 nm; and (c) 8 nm.

55 44

switches 33

of 22

# of # of Switches 11

Number 00 01~051-5 05~10 5-10 15~2015-20 20~25 20-25 35~40 35-40 Cycles (billions) Billion cycles

Figure 3.12 A histogram of the 12 switches (i.e., 60 % of 20 in Fig. 3.10(c)) with Ra =

8 nm showing cycles of operations before failure from fracture.

To further study the effect of contacting surface roughness, AFM pull-off force test was conducted to determine the adhesion force between the Si3N4 AFM tip and the SiC surface. As shown in Table 3.1, the adhesion force calculated from Derjaguin-Muller-

Toporov (DMT) [102-103] model of the switch with Ra = 1 nm is almost 2.2 times higher than that of switch with Ra = 8 nm. This result explains the high probability in stiction of the Ra = 1 nm switches. The DMT model is described as,

F = 2πRWA (3-8)

where F, R and WA stand for the adhesion force, radius of the probe and adhesion energy.

The adhesion force was obtained from AFM pull-off testing using Hooke’s law (Fig.

3.14). The nominal radius and spring constant of the Si3N4 tip used in this study were 40

nm and 0.12 N/m, respectively. It should be noted here that the obtained adhesion

energies were the interacting energies between the silicon nitride and poly-SiC. The SiC-

SiC contacting energy could be obtained by using SiC tips, which not readily available

for this study.

Ra (nm) Adhesion Force (nN) Calculated Adhesion Energy (mJ/m2) 1 72.9 290 5 53.1 210 8 33.4 131

Table 3.1 Adhesion forces and energies calculated from AFM pull-off tests for SiC

surfaces of different roughness.

(a) (b)

Figure 3.13 Schematics showing the difference in the distance between the non-

contacting portion of switches (Dave): (a) smoother contacting surfaces;

and (b) rougher contacting surfaces [57].

b a c

Figure 3.14 Pull-off force test data for a switch with 1 nm roughness on contact

surfaces. The pull-off force was obtained from F = k·x, where x is the

distance between “a” and “e” labeled in the schematics.

Similar failure analysis was conducted at elevated temperature on switches with Ra =

8 nm. 300 °C testing was conducted in air using a probe station, with switches placed on a customized temperature controlled heating stage. Gold-coated tungsten probe tips were used to minimize probe degradation due to oxidation. Seen from Fig. 3.15, the probability of stiction during operation increased with temperature. Only 20 % of the tested switches exhibited a lifetime more than billion cycles. The best result obtained at 300 °C was 3.7 billion cycles before failure.

Figure 3.15 Failure mechanisms observed at 300 °C in switches with Ra = 8 nm.

3.5.2 Mechanical Fracture

As shown in Fig. 3.12, 12 switches with Ra = 8 nm operated more than a billion

cycles. The failure mechanism of these switches the fracture at the fixed end of the

suspended cantilever electrode, where bending stresses are a maximum and the

topography from the lower electrode creates a weak point. Figure 3.16 clearly shows the fracture location in a 9 µm-long switch after 5 billion cycles. The same photo also shows that compared to a virgin switch, some irregularities have appeared on the surface and edges of the cantilever electrode likely due to mass transport. These irregularities are likely caused by electron migration, a phenomenon that has been observed on silicon surfaces [104-105]. Though the current passing through the SiC device is low, the current density is relatively high, due to the extremely small cross section area. In addition, the temperature of the device may increase during operation due to joule heating. These effects potentially enhance the mass transport event observed in the SEM photo.

However, further study is needed to ascertain the cause(s).

(a)

(b)

Figure 3.16 SEM photos of: (a) a switch after 5 billion cycles of operation, wherein the

red circles point out the fracture location and irregularities likely due to

mass transport; and (b) a virgin switch.

3.6 Graphitization of Poly-SiC

Due to its potential of operating at 100 GHz and superior electron mobility, graphene

transistors obtained from graphitized SiC surface have received much recent attention

[106]. In most publications, solid-state graphitization of both α- and β-SiC was usually

conducted in ultra-high-vacuum (UHV) at a temperature higher than 1200 °C in order to

initiate the surface reconstruction processing [107-110].

As discussed in Section 3.4, the contact resistance of the fabricated SiC NEMS

switches is in MΩ range. To improve its conductivity, graphitized SiC surface is an

attractive solution since the electrical conductivity of graphite/graphene is exceptional.

The requisite processing does not alter the key dimensions of the device given that only a

few atomic layers of materials are affected. However, conducting the experiment under

UHV and at a temperature > 1200 °C requires an expensive vacuum chamber, pumping

system, and heating tool. Here, we report an alternative approach to graphitize the SiC

surface, i.e., using laser energy.

3.6.1 Surface Analysis After Laser Processing

The sample used in this experiment was a 6500 Å-thick 3C SiC layer deposited on a

Si wafer with a 0.5 µm SiO2 layer sandwiched in between for electrical isolation. The SiC

surface was then subjected to XeCl laser treatment with an incident energy of 1.2 J/cm2.

(The laser facility is located at Space and Naval Warfare Systems Command (SPAWAR) office in San Diego). The wavelength of XeCl was 308 nm [111], and the laser spot size was about 3 mm × 3.5 mm. Figure 3.17 depicts the surface morphology after laser 70

processing. The area subject to laser incidence exhibits a rougher surface. Measured by

AFM, the surface roughness of untreated and treated regions were 12 nm and 46 nm, respectively.

untreated area

treated area

Figure 3.17 Optical micrograph showing the difference in surface morphologies

between the laser treated and untreated regions.

XPS depth profile (Fig 3.18) indicated that a 3 nm-thick carbon rich layer was formed after the laser treatment, i.e., based on the obtained atomic ratio. After sputtering deeper into the specimen, the Si to C ratio changed to 1:1, i.e., the unaffected bulk SiC.

Subsequent experiments showed that the thickness of that C-rich layer could be manipulated by adjusting the incident laser energy. The results support our assertion that graphitization through laser treatment can be integrated into our NEMS switch fabrication process without affecting the designed dimensions. However, additional work is needed to extend the process to the underside of the suspended cantilever electrode. It

should be noted that the laser energy is extremely high; as a result, materials other than

SiC may be damaged during the laser treatment if exposed to the laser spot. Indeed, a crack in SiO2 layer was found (Fig. 3.19) after processing with higher incident energy.

C (at%) O (at%) Si (at%) 90 80 70 60 50 40

Atomic % 30 20 10 0 0 50 100 150 200 250 300 350 400 Depth (Å)

Figure 3.18 XPS depth profile showing the composition change of the sample treated

by XeCl laser with a fluence of 1.2 J/cm2.

Figure 3.19 TEM photo showing crack formation in a SiO2 layer after laser treatment.

3.6.2 TEM Observation

To observe the Carbon-rich layer created on the SiC surface and the interface, a

transmission-electron-microscopy (TEM) sample was prepared by the same XeCl laser

treatment. However, the dose was increased to 1.3 J/cm2, and the pulse was repeated five times in order to form a thicker carbon-rich layer for ease of observation.

From the TEM picture shown in 3.20, the affected layer is ~10 nm thick and featured with a ribbon-like carbon structure. The nano-crystallites, characterized by the stacking of lattice fringes, are randomly oriented. Similar structures have been reported by annealing SiC and other carbonaceous materials [112-113]; they have been referred as nanographite ribbons [114]. The increase of ordering to form planar graphite can be

achieved by annealing this structure at high temperature [109]. Based on select area electron diffraction (SAED) pattern (inset in Fig. 3.20) with camera length calibrated by single-crystalline silicon, the spacing between each layer is about 3.6 Å, which is very close to turbostratic carbon structure [115]. Turbostratic-carbon is generally considered as a variant of hexagonal graphite with different stacking ordering and spacing [116].

Figure 3.20 TEM photo of the poly-SiC sample subject to 1.3 J/cm2 laser energy with

a magnified view of the formed nanographite ribbons. The inset in the

magnified photo shows the SAED of the nanographite.

3.7 Graphitization of Single Crystalline 4H-SiC

To evaluate the effect of different crystalline types on graphitization, single

crystalline 4H-SiC wafer (mechanical grade) purchased from SiCrystal, Inc. was subject

to the same laser treatment. The wafer was semi-insulating with un-measureable

resistance at room temperature. The measured surface roughness of the as-received wafer

was about 8 nm. Figure 3.21 depicted the difference between the areas with and without laser fluence. Confocal microscopy was used to show both surface morphology and to measure the roughness (Fig. 3.22). After the laser treatment (20 pulses, 2.5 J/cm2), the

surface became much rougher, Ra = 122 nm. A rough 4-point-probe measurement

indicated that the resistivity of the laser treated area was 0.004 Ω-cm, lower than our

poly-SiC film [117]. This result confirms our expectation that using laser energy to

convert the SiC surface into a more carbon-rich layer will lower the contact resistance of

SiC NEMS switches.

Confirmed by both XPS depth profile and TEM observation (Fig. 3.23), a very

similar carbon-rich layer was created on the surface after the laser experiment. For the

sample subject to 20 pulses of 2.5 J/cm2 laser fluence, the carbon-rich region is about 8

nm thick. The observed morphology was almost identical to the image obtained from 3C-

SiC sample, composed of nanographite ribbons.

Figure 3.21 Optical micrograph showing the effect of laser energy on a 4H-SiC wafer

surface.

Figure 3.22 Confocal microscopy image showing the rough surface of 4H-SiC after

laser treatment.

3.8 Summary

Surface-micromachined, cantilever-type, electrostatic SiC NEMS switches have been

fabricated and characterized, having 75 nm gaps. The switches exhibited threshold/pull-in

voltages less than 5 V, a value generally constant up to 600 °C. Switches have been

operated more than 40 billion cycles at room temperature before mechanical failure

occurred. Operation at 400 °C and above was limited due to the package wire bond

failure. The nearly-zero leakage current of the switches in OFF state, even at high

operating temperatures, make them ideal for eliminating leakage power.

The contact resistance of the switches was dominated at low actuation voltages by the

native oxide formed on the switch contacting surfaces. At higher applied voltages, the

calculated contact resistance values using Sharvin’s model fit the measured values well.

Stiction and mechanical fracture are the observed failure mechanisms. 12 of the 20 (i.e.,

60 %) of the switches with Ra = 8 nm electrode surface roughness could be actuated

billions of cycles. In contrast, 85% (17 of 20) of the switches with Ra = 1 nm failed due

to stiction right after release. For switches lasting more than a billion cycles, failure

occurred due to fracture at the fixed end of the suspended cantilever.

To increase its conductivity, XeCl was used to convert the SiC surface into a more

conductive layer. Based on TEM and XPS studies, few nanometer nanographite ribbon

structure was obtained from both polycrystalline (3C) and single crystalline (4H) SiC.

The measured resistivity of this surface layer was 0.004 Ω-cm.

Figure 3.23 TEM photo showing the nanographite structure of the 4H-SiC surface

after laser treatment.

CHAPTER 4

3-Terminal Poly-SiC NEMS Switches for High

Temperature Logic

4.1 Introduction

Chapter 3 demonstrated proof of concept for 2-terminal SiC NEMS switches with a

threshold voltage (≤ 5 V) compatible with our SiC electronics described later in this thesis. However, to form all-mechanical computing elements, 3-terminal devices are needed for individual gate control. To this end, we have developed a complementary 3-

terminal SiC NEMS switch for high temperature logic applications.

This chapter reports the dimensions of the designed switches, the fabrication process, and device characterization. Operating lifetimes at room and high temperatures are studied and the failure mechanisms are discussed. A microfabricated electromechanical inverter using SiC complementary NEMS switches, capable of operating at 500 °C with

ultra-low leakage current, is also demonstrated here. This logic element, which is also

radiation tolerant, presents a technology basis for all-mechanical computation at high

operational temperature.

4.2 Dimensions of the Designed Switch

Figure 4.1 shows a schematic and SEM photos of the 3-terminal switch. The basic

design criteria are the same as discussed in Chapter 2, the only difference being that the spring constant changes due to the differing position of the Gate. The length (L) varies from 3 µm to 8 µm in the designs. The width (t) is 150 nm and the actuation gap (g1) is

set at 150 nm or 200 nm. The dimension parameter d shown in Fig. 4.1(a) is fixed at 300

nm. Table 4.1 lists the simulation results for the required threshold voltage switches with

L = 8 µm.

(a)

Figure 4.1 The complementary 3-terminal switch: (a) schematic representation; (b) a

SEM photo of a released SiC NEMS switch with L = 3 µm, t = 200 nm;

and g1 = 150 nm; and (c) a SEM photo showing the ON state of the 3-

terminal SiC NEMS switch.

source gate

drain

(b)

(c)

Figure 4.1 Continued.

L (µm) L1 (µm) t (nm) g0 (nm) g1 (nm) Simulated VTH (V)

8 7.5 150 100 110 3.0

8 7.5 150 150 160 5.3

8 7.5 200 190 200 11

8 7.5 150 190 200 7.2

Table 4.1 Simulated VTH for devices with different dimensions.

4.3 Fabrication Process

For the in-plane design here, the cantilever-type switch can be realized in one lithography step. A 4-inch silicon wafer was thermally oxidized at 1075 °C to form a 0.5

µm-thick SiO2 electrical isolation layer. The same LPCVD poly-SiC as in Chapter 3 was deposited to a thickness of 400 nm. A very thin (10~15 nm) Au layer was thermally evaporated as a charge dissipation layer for electron-beam (E-beam) lithography. The lithography process started with coating a 168 nm-thick 950 PMMA as resist. The resist was then subject to E-beam patterning. After developing the exposed resist, a 40 nm- thick Ni was thermally evaporated as the SiC etching mask. The lift-off process was performed at 75 °C using Microposit Remover 1165 to pattern the Ni. The unmask area of SiC was removed by Inductively Coupled Plasma (ICP) etching (STS multiplex

Etcher) using SF6 and Ar. This dry etching step was conducted at a pressure below 25 mTorr. The final step was to release the switch by HF wet etching of the SiO2 layer for

35 seconds; followed with CO2 critical point drying. Figure 4.1(b) shows a free-standing

3 µm-long SiC NEMS after releasing.

4.4 I-V Characterization

Each switch has three terminals: source, gate, and drain, where the gate is used as a

control terminal to create a conducting path between the drain and source through

electrostatic actuation of the cantilever beam (source). The threshold voltage of the 3-

terminal switches is obtained by sweeping a DC voltage between the gate and source

until the cantilever is pulled-in to contact the drain terminal, resulting in a detectable

current (i.e., the same technique as in Chapter 3). As shown in Fig. 4.1(c), the ON state of

the transistor-like switch is when the source cantilever contacts the drain terminal to

realize the conducting “channel”.

For a switch with L = 8 µm, t = 150 nm and g1 = 120 nm, the measured threshold

voltage is about 5 V at room temperature (see Fig. 4.2). The switch operated 21+ billion

cycles at room temperature before fracture occurred (see Fig. 4.3). The leakage current in

OFF state was lower than 100 fA (below the noise floor of the measuring tool).

High temperature testing was conducted in a nitrogen environment with devices

packaged in ceramic DIPs using gold wire bonds. Figure 4.4 illustrates the testing setup

for temperature up to 550 °C. Device has been verified to work at 550 °C with similar

threshold voltages as in room temperature. Due to the limitation of the designed heater,

lifetime testing at high temperature was conducted at 500 °C, with 2+ billion cycles the

most before cantilever beam fracture. The high temperature failure (Fig. 4.5) may be a

result of an electrical spike caused by the ambient temperature; further study is needed to

determine the cause with confidence.

Current (nA) 10

0 01234568 Voltage (V)

Figure 4.2 I-V characteristics showing room temperature actuation. The current

reaches the set current limit (30 nA) when the applied DC voltage is

higher than 6 V.

Figure 4.3 SEM photo showing switch failure due to a clean fracture at the support

end of the cantilever beam after 21+ billion cycles.

Figure 4.4 Photos showing the high temperature test setup.

Figure 4.5 SEM photo showing switch failure after 2+ billion cycles at 500 °C. The

reason for the melting-like feature is not known.

4.5 Inverter Operation

The electromechanical inverter was designed using two laterally-actuated NEMS

switches following a complementary static-CMOS logic style [118], which consisted of a

pull up and pull down stage. Figure 4.6 shows the schematic of the inverter. The

suggested logic style was chosen for its low noise sensitivity and power consumption.

The two laterally-actuated cantilevers of the inverter are connected to positive (VDD)

and negative (VSS) terminals, respectively (Fig. 4.7). When applying a positive input

(logic high), the electrostatic force between the input and the cantilever connected to VSS overcomes the restoring force of the beam. The cantilever then deflects laterally to

contact the output, providing logic low. Logic high can be obtained by supplying a negative input to actuate the cantilever beam connected to VDD. Due to the

complementary nature of logic, the output terminal (VOUT) is connected to either VDD (for logic “0” at VIN) or VSS (for logic “1” at VIN) but not both, thus preventing any direct path current at steady state. Inverter operation has been demonstrated at 500 °C (Fig. 4.8) with

VDD = 6 V and VSS = -6 V, at an operating speed of 500 kHz. The logic level is obviously

higher than the existing silicon logic devices operating usually at 3 V and lower.

However, the threshold voltage of the fabricated switches is compatible to our SiC high

temperature electronics discussed later; the logic level may be further reduced by

narrowing the actuation gap with advances in the nanofabrication.

Figure 4.6 The complementary inverter logic showing the pull up and pull down

stages: (a) schematic; and (b) layout.

Figure 4.7 SEM photos of a fabricated inverter. The magnified photo shows the

cantilever connected to VSS and the corresponding actuation gap.

Figure 4.8 Input-output voltage waveform of the inverter at 500 °C.

4.6 Nanofabrication Challenges

As in MEMS devices, the residual stress in the structural film (i.e., poly-SiC here)

will lower the fabrication yield. As shown in Fig. 4.9, the released cantilever bends in an

opposite direction due to residual stress in the film. For the poly-SiC film used in this

study, the residual stress is under 100 MPa. But for NEMS switches, tolerance to residual stress is very low because any deflection caused by localized stress will leads to failure given that the gaps are usually smaller than 100 nm.

As we aggressively scale down the actuation gap to realize CMOS-compatible threshold voltages, the nano-scale gap is difficult to delineate due to material re- deposition within the confined gap during etching of the film. More specifically, while all other switches with g1 > 120 nm were cleanly etched through, the three terminals of the

switch with 80 nm gap (Fig 4.10) were still connected, even after a 50 % overetch.

Figure 4.9 SEM image showing the deflection phenomenon of a released cantilever

due to residual stress.

Figure 4.10 Material re-deposition in a 80 nm gap.

4.7 Summary

Three-terminal SiC NEMS switches capable of operating in the temperature range of

25 °C to 550 °C having a threshold voltage ~ 5 V were reported in this chapter. Lifetimes of more than 21 billion and 2 billion cycles at 25 °C and 500 °C, respectively, were

achieved. The room temperature failure mechanism was mechanical fatigue characterized

by a clean fracture surface. Failure mechanism at high temperature was not clear and

requires further study. The first inverter capable of operating at 500 °C using SiC complementary NEMS switches was demonstrated and showed ultra-low leakage current.

SiC NEMS-based logic elements operating at previously inaccessible temperatures create a pathway toward energy-efficient high temperature computation.

CHAPTER 5

6H-SiC JFET-Based Logic

5.1 Introduction

Compared to the NEMS-based logic, electronics-based logic implementation may be

more reliable because of lack of mechanical. However, electronic devices suffer from

leakage currents (p-n junction, thermoionic), which increase markedly with temperature.

Silicon electronics technology is generally limited to operating temperatures below 300

°C due to its bandgap. Wide bandgap semiconductors, like SiC, with low intrinsic carrier

concentration (ni) at high temperatures are suited for applications that exceed 300 °C.

18 -3 More specifically, at 600 °C, the ni of silicon reaches 10 cm whereas for 6H-SiC, with

11 -3 a 3.03 eV bandgap, ni is 10 cm . As mentioned in Chapter 1, SiC junction-field-effect transistors (JFETs) are arguably the most promising choice for high-temperature logic applications among various FET architectures. Thus, in this chapter, we demonstrate logic gates capable of high temperature operation using 6H-SiC depletion-mode JFETs

The electrical characteristics of a single transistor, inverter, NAND and NOR gates based on SiC JFETs are reported in the following sections. The source to drain leakage in the temperature range of 25 °C to 450 °C of a single transistor is studied. In addition to demonstrating logic operation, a SiC NOR gate is used to investigate the gate-to-channel

leakage current as a function of temperature.

Figure 5.1 Schematic diagram of the cross section of an as-received SiC wafer.

5.2 Fabrication Process

P-type, 6H-SiC wafers having three epitaxial layers were purchased from Cree, Inc.

19 -3 for this study. The top p+ (ND ~ 1×10 cm ) layer served as the gate which controlled

17 -3 the depletion of the n-type (NA ~ 1×10 cm ) channel layer underneath. The 7 µm thick p-buffer layer between the channel and the substrate ensured that the channel thickness was primarily affected by gate bias. The fabrication process, described in more detail in

[119], is outlined in Fig. 5.2,

Figure 5.2(a) RIE was used to form the gates of the JFET.

Figure 5.2(b) The channel region of the JFET was isolated using RIE.

Figure 5.2(c) A 1 μm-thick LTO was deposited and patterned to act as ion implantation

mask for the source and drain contacts. 96

Figure 5.2(d) Nitrogen ion implantation was conducted using a box profile (see table) to

define the source and drain contacts.

p+ SiO2

+ n+ n n

SiC Substrate

Figure 5.2(e) The LTO was removed, and a 20 nm-thick SiO2 was grown thermally to

passivate the SiC surfaces. Contact holes were then opened.

Figure 5.2(f) A stack of Ti, TaSi2 and Pt was sputtered as Ohmic contact metal,

followed by the deposition of 300 nm Si3N4 passivation layer.

Interconnects Metal (layer 2) p+

+ n+ n n

SiC Substrate

Figure 5.2(g) Two additional metallization steps using the same metal stack and an

additional interlayer dielectric composed of PECVD silicon

dioxide/nitride/dioxide sandwich structure were used to connect the

transistors and passives to realize the circuits.

5.3 Characterization of 6H-SiC JFET

JFET is a three-terminal device composed of source, drain, and gate terminals. The

source is usually connected to ground, whereas the drain is biased with a positive voltage

(VDS). The ON/OFF state of a transistor is determined by the supplied gate voltage (VGS).

The designed n-channel JFET is a normally-on device, i.e., it needs a negative threshold voltage applied to the controlling gate to deplete (i.e., close) the channel. The threshold voltage (VTH) can be described as,

VTH = Vbi ̶ Vpo (5-1)

where Vbi is the built-in potential between the gate and the channel and Vpo is the pinch- off voltage.

V (5-2)

(5-3)

Table 5.1 describes all the abbreviations and their physical values used in this chapter to

derive the JFET electrical characteristics.

Parameters Physical Meaning Values

L Channel Length (cm) 1×10-3

W Channel Width (cm) 1×10-2

t Channel Thickness (cm) 3×10-5

T Temperature (°K) 300

k Boltzmann’s Constant (J/K) 1.38×10-23

q Electronic Charge (C) 1.602×10-19

kT/q Thermal Voltage (V) 0.02586

-3 -17 ND Donor Concentration (cm ) 1×10

-3 -19 NA Acceptor Concentration (cm ) 4×10

-3 -6 ni Intrinsic Carrier Concentration (cm ) 1.61×10 (@ 300K)

n Carrier Concentration (cm-3) 3.91×1016 (@ 300K)

2 µn Electron Mobility (cm /V·s) 272 (@ 300K)

-14 ε0 Permittivity of Vacuum (F/cm) 8.854×10

εr Relative Dielectric Constant 9.66

Table 5.1 Physical constants, parameters and some electrical properties of 6H-SiC

used in this chapter to model the fabricated JFETs.

100

Typical current-voltage (I-V) behavior of a JFET can be divided into two regions: (1) the triode (linear) when the drain voltage (VDS) is low and (2) the saturation region when VDS is applied. The drain current, IDS, also termed as channel current, obtained from triode

and saturation regions can be described by Eqs. (5-4) and (5-5), respectively,

2 (5-4)

1 3 2 (5-5)

Here, Ip stands for the pinch-off current and is expressed as,

(5-6)

Detailed design considerations and modeling of the fabricated JFETs can be found in

[12]. To examine the I-V behavior, a JFET with width (W) / length (L) = 100 × 10 µm was tested at different temperatures. Figure 5.3 shows the drain current (IDS) versus gate-

to-source voltage (VGS) and drain-to-source voltage (VDS) characteristics at 25 °C, 300 °C

and 450 °C. All measurements were conducted in room air on a probe station with a

customized heating stage. The JFET performed well within this temperature range, and

the extracted threshold voltage remained nearly constant at about -7 V. From the IDS-VDS plot, it is clear that the saturation current decreases with testing temperature due to 101

degradation in carrier mobility; the IDSS measured at 25 °C under VGS = 0 V and VDS = 20

V was about 1.5 mA, 3 times higher than that obtained at 450 °C under same conditions.

102

25 °C 300 °C 450 °C 1.8 1.6 1.4 1.2 1 (mA) 0.8 DS I 0.6 0.4 0.2 0 0 5 10 15 20 25 30 35 40

VDS (V)

25 °C 300 °C 450 °C 1.6 1.4 1.2 1

(mA) 0.8 DS

I 0.6 0.4 0.2 0 -17 -14 -11 -8 -5 -2 1

VGS (V)

Figure 5.3 Measured I-V behaviors of a representative JFET (W/L = 100 µm × 10

µm) as a function of temperature up to 450 °C: (a) VDS-IDS data with VGS

and substrate biases both 0 V; (b) VGS-IDS data with VDS and substrate

biases 20 V and 0 V, respectively.

103

5.4 Channel Leakage Current

Channel leakage of the JFET, IOFF, is defined as the measured drain current when the

channel is completely depleted (applied VGS is more negative than VTH). As depicted in

Fig. 5.4, the measured channel leakage current increased significantly with temperature.

At 450 °C, this leakage current has reached 2 µA, about 100 times larger than that at

room temperature. It has been reported in [10] that this severe channel leakage associated

with high temperature can be greatly improved by annealing the device for a few hundred

hours at 500 °C. Compared to NEMS based switches with nearly-zero leakage in OFF

state, the leakage current in the JFETs leads to notable power consumption in circuits

with multiple transistors operating at higher temperatures.

In spite of the leakage current, the fabricated JFETs still yield a satisfying ION/IOFF ratio at elevated temperatures. More specifically, the ION/IOFF ratio is about 250 at 450 °C

(75,000 at 25 °C), ensuring the functionality of the transistor. In addition to drain to

source leakage, the gate to channel leakage is examined next.

104

Measured Channel Leakage 1600 1400 1200 1000 800 600 400

Leakage Current (nA) 200 0 25 150 300 450 Temperature (°C )

Figure 5.4 Measured channel leakage current of a JFET with W/L = 100 µm × 10 µm

as a function of temperature up to 450 °C. This current was the measured

IDS value at VGS = -15 V, VDS= 20 V and Vsub = 0 V.

105

5.5 Logic Gates

The circuit schematics and their functionalities (truth table) of the SiC JFETs based

inverter, NAND and NOR gates are shown in Fig.5.5. The fabricated SiC inverter

consists of three JFETs where a unit transistor size (1X) is 160 µm wide and 10 µm long,

Universal gates (NAND and NOR) are composed of four transistors, as shown in Fig. 5.6.

All logic gates have an integrated depletion load which consists of two JFETs and three

resistors. These components control the bias current of the logic gate and hence the

output voltage. The resistors are fabricated from the n-channel epitaxial layer, and their

sizes are given in number of squares for sheet resistance (Rsh) 13.8 kΩ/□ at room

temperature.

Devices were packaged in ceramic DIPs using gold bond wires. For high-temperature

testing, a customized resistive heater (same as the one shown in Fig. 4.4) was used to heat

the entire package from both front and back sides. All testing was performed in room air.

During testing, the input logic high was 0 V and logic low -7 V; VDD and VSS were

+14 V and -14 V, respectively. All three logic gates were operated at temperatures from

25 °C to 550 °C (see Fig. 5.7 to Fig. 5.9). It can be seen that the output voltage levels are

well matched to the input levels at room temperature. The output high level becomes

more negative, however, as the temperature increases. More specifically, the measured

output logic high levels of the inverter are -0.1 V, -0.9 V, and -2.9 V at 25°C, 300 °C, and

550 °C, respectively. The kink shown in the 550 °C NAND output high level is likely

caused by the substrate leakage passing through the transistor when input A is OFF and

input B is ON.

106

(a)

(b)

(c)

Figure 5.5 Circuit schematics and corresponding truth tables of the designed SiC

logic gates: (a) inverter; (b) NAND; and (c) NOR.

107

The temperature dependence of the output high level is caused by a mismatch between the resistor and the current-source variation over temperature, which degrades the stability of the level shifter circuit. This temperature dependence of the output high level can potentially be corrected by improving the circuit design or by adjusting the substrate bias (Vsub) and VDD.

Figure 5.6 Optical micrograph of the fabricated 6H-SiC JFET-based NOR gate

constructed from 3 resistors and 4 transistors.

108

Figure 5.7 Test waveforms for the SiC inverter at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and

inputs are set at 1 kHz frequency during testing.

109

Figure 5.8 Test waveforms for the SiC NAND gate at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and

inputs are set at 1 kHz frequency during testing.

110

Figure 5.9 Test waveforms for the SiC NOR gate at 25 °C, 300 °C and 550 °C.

Substrate bias, VDD and VSS are 0, +14 V and -14 V, respectively, and

inputs are set at 1 kHz frequency during testing.

111

5.6 Gate Leakage Current

A SiC NOR gate was used to study the input leakage current, i.e. the current passing

through input A (Fig. 5.5c) when both inputs are OFF (biased by -14 V). As depicted in

Fig. 5.10, the leakage current increases significantly with temperature. Theoretically, the

leakage current of a p-n junction is the sum of the minority carrier diffusion current in the neutral zone and the thermal generation current in the depletion region, as expressed by

[120],

Jleakage = Jdiffusion + Jgeneration (5-7)

For SiC p-n junctions, the dominant contribution is the thermal generation current when

ambient temperature is below 900K and this term can be described as:

≅ (5-8)

where q is the charge of the electron. WD and τg are width of the depletion region and the mean time to generate an electron-hole pair, respectively.

For the W/L = 640 µm/10 µm SiC JFET used as the input A of the NOR gate, the

calculated width of depletion region was about 155 nm. The intrinsic carrier

concentration can be obtained by the well known formula:

112

2 (5-9)

Eg is the energy bandgap of 6H-SiC and its temperature dependence can be found in

[121]. NC and NV stand for the effective density of states in the conduction and valence band, respectively; both values at elevated temperatures are reported in [121]. Based on the abovementioned information, the intrinsic carrier concentration of 6H-SiC is about

2×1011 cm-3 at 550 °C. By inserting all known parameters into Eq. (5-9), the calculated leakage current under reverse bias of a 640 µm/10 µm SiC JFET at 550 °C will not exceed 1 nA, which is several orders of magnitude lower than the measured data (9.4

µA). The cause of the unexpectedly measured high leakage current is unclear.

5.7 Summary

6H-SiC JFETs based inverter, NAND and NOR gates capable of operating at temperatures from 25 °C to 550 °C have been demonstrated in this chapter. These logic building blocks open a path way for high temperature computation. The remaining challenges include the development of reliable Ohmic contacts, robust interconnect and interlayer dielectrics, and packaging for such high temperatures. Input leakage current at high temperature must also be improved, but this is likely to occur naturally as crystal quality improves.

113

A) 8 

2 Leakage Current ( 0 0 100 200 300 400 500 600 Temperature (C)

Figure 5.10 Measured gate leakage current of a SiC NOR gate as a function of

temperature with Vsub = 0 V, VDD = +14 V and VSS = -14 V.

114

CHAPTER 6

Development of Dielectric Layers for High

Temperature Applications

6.1 Introduction

For both electronic and mechanical SiC high-temperature logic devices, the ability to

utilize multiple film layers enables additional design flexibility and capability, i.e., design space is expanded and more complex/functional architectures become possible. To electrically isolate different electrically conducting layers, dielectric materials capable of

operating at 300 °C to 600 °C are required.

In contrast to the recent focus on achieving higher capacitance densities by using thinner dielectric layers and higher dielectric constants (high-k) with materials like Al2O3 and HfO2 [122-123], this work focuses on the high temperature dielectric properties of

the most mature materials used in VLSI applications — silicon dioxide (SiO2) and silicon

nitride (Si3N4). Though there are tremendous amount of studies discussing the dielectric properties and reliability of SiO2 and Si3N4, very few present the capabilities of these two

materials for temperature application. The reason is that silicon electronic technology is

generally focused on the temperature range below 250 °C. Thus, we are motivated to

115

examine whether SiO2 and Si3N4 are promising dielectrics for high-temperature

applications by using metal-insulator-metal (MIM) capacitors.

6.2 Silicon Dioxide and Silicon Nitride

6.2.1 Films Deposited by LPCVD

SiO2 and Si3N4 have been widely used in both electronics and MEMS applications as

gate dielectric, passivation, inter-metal dielectric, mask and even structure material.

Among various thin film deposition techniques, chemical-vapor deposition (CVD) is a

preferred method to grow these two dielectric materials because of its excellent step

coverage and ease of controlling the film stress.

For the past three decades, low-pressure CVD (LPCVD) has been extensively utilized

to form both SiO2 and Si3N4, especially in the front-end processing stage because this

technique can provide excellent uniformity and high throughput. Low-temperature oxide

(LTO) deposited in a LPCVD tube furnace has been commonly used in the

semiconductor industry when thermal oxide is not suitable. The LTO deposition reaction

can be expressed as,

SiH4 + O2 → SiO2 + 2 H2 (1)

Though LTO is attractive because of its relatively low deposition temperature (~ 450 °C),

it is very challenging to lower the pin-hole density in this oxide film. As a result, LTO is

116

no longer a preferred SiO2 source in semiconductor manufacturing process.

Either dichlorosilane (DCS) or silane and ammonia are the gas sources for LPCVD of

silicon nitride films. The reaction for this process usually takes place at 700 to 850 °C

and is expressed as,

3 SiH2Cl2 + 4 NH3 → Si3N4 + 6 HCl + 6 H2 (2)

or 3 SiH4 + 4 NH3 → Si3N4 + 12 H2 (3)

6.2.2 Films Deposited by PECVD

Though LPCVD offers the best film quality, the deposition procedure is sometimes

too high for some back-end manufacturing steps, e.g., after metal deposition. To address

this problem, plasma-enhanced CVD is an attractive alternate to deposit SiO2 and Si3N4 at much lower temperatures. With the help of plasma excitation, the deposition temperature of both dielectric materials can be reduced to a temperature range of 300 °C to 400 °C.

Tetraethoxysilane (Si(OC2H5)4, TEOS) and oxygen are used as the precursors to form

PECVD TEOS silicon dioxide. The deposited films often incorporate some nitrogen and

hydrogen. The film stress and the concentration of H and N can be controlled by

adjusting the deposition parameters and by post-annealing. The chemical reaction during

PECVD TEOS silicon dioxide formation is described below:

117

Si(OC2H5)4 + 12 O2 → SiO2 + 10 H2O + 8 CO2 (4)

PECVD nitride is obtained by the decomposition of the gas sources, silane (SiH4) and

ammonia (NH3). During the deposition process, the reaction usually takes place at 300

°C to 350 °C:

3 SiH4 + 4 NH3 → Si3N4 + 12 H2 (5)

6.3 Design and Fabrication of MIM Capacitors

6.3.1 Design Criteria

In this study, we have explored two MIM capacitors with different PECVD dielectric

films. One MIM uses only PECVD TEOS silicon dioxide film (hereafter referred to as

Capacitor A); the other MIM is composed of a stack of PECVD TEOS Oxide/Nitride/

TEOS Oxide (ONO stacking, referred to as Capacitor B).

Because most of the leakage mechanisms are related to temperature, the designed dielectric layer is much thicker than conventional MIM capacitors. The thickness of both

Capacitors A and B is set to 600 nm in order to suppress leakage current with rising temperatures. TiAl is used for both bottom and top electrodes because of its excellent thermal stability and oxidation resistance [124]. Since any defect present in the dielectric

film will easily lead to capacitor failure (shorting, breakdown), especially at high

temperature, the size of the designed square capacitor (Fig. 6.1) is made relatively large

118

(200 µm × 200 µm) to verify if there is any pin holes or particles are formed during deposition.

6.3.2 Deposition of PECVD TEOS Oxide and Nitride

Both PECVD TEOS oxide and nitride films used in this work were deposited in an

UltraDep 1000 PECVD system. The equipment incorporates dual frequency reactors for

precise stress control. The high frequency supply (HF) is set at 13.6 MHz with a

maximum power output of 1000 W. The low frequency supply (LF) operates at 400 kHz

with a 200 W output.

TEOS and oxygen were used as the precursors of the PECVD TEOS oxide. The

process was conducted at 365 °C using N2 as the carrier gas. The deposition rate was

about 1800 Å/min. PECVD nitride films were deposited at 300 °C with silane and ammonia as gas sources. The deposition rate for the PECVD nitride film was about 1000

Å/min. Detailed film deposition parameters of PECVD TEOS oxide and nitride

)including flow rates, power settings and pressure) are listed in Table 6.1.

Figure 6.1 Layout of the designed MIM capacitor with 200 µm × 200 µm area.

119

PECVD TEOS Oxide

N2 1500 sccm

O2 950 sccm

TEOS 150 sccm

HF (13.56 MHz) 400 W

LF (400 kHz) 34 W

Pressure 3 Torr

Temperature 365 °C

PECVD Nitride

N2 1600 sccm

SiH 1000 sccm 4 NH 600 sccm 3

HF (13.56 MHz) 350 W

LF (400 kHz) 0 W

Pressure 2.5 Torr

Temperature 300 °C

Table 6.1 Process parameters for PECVD oxide (top) and nitride (bottom)

depositions.

120

6.3.3 Fabrication Process of MIM Capacitors

The fabrication process started with high resistivity, 100 mm-diameter silicon wafers.

A 0.5 µm-thick silicon dioxide layer was thermally grown to electrically isolate the substrate. TiAl was sputtered using a Ti30Al70 target purchased from Kurt J. Lesker company to a thickness of 3000 Å and was patterned by lift-off to serve as the bottom electrode for both Capacitors A and B. For Capacitor A, a 5850 Å-thick PECVD TEOS oxide film was deposited, followed with BOE etching to define the capacitor area using photo resist as etching mask. A 3000 Å-thick top TiAl electrode was then formed using the same technique as the bottom electrode. The dielectric film in Capacitor B is a

PECVD ONO stack. The thicknesses of these three layers were 2050 Å (TEOS oxide),

1200 Å (nitride) and 2600 Å (TEOS oxide), respectively. The thickness of PECVD silicon nitride layer was chosen to be thin because of the high residual tensile stress in the film (>700 MPa), which can lead to cracking. Based on experiment, this nitride film exhibits cracks at 300 °C if the thickness exceeds 1500 Å. All three layers were patterned by BOE etching. The same TiAl top electrode was applied to Capacitor B.

6.4 Characterization of the MIM Capacitors

Confirmed by both electrical testing and microstructure observation, most of the fabricated Capacitors A and B were pin-hole free and work up to 525 °C. The capacitance drift, leakage current and breakdown field as a function of testing temperature are discussed in the following sections. The capacitance of both MIMs was measured by

Agilent E4980 Precision LCR Meter. Each capacitance data point shown in this chapter 121

was an average of 10 measurements. Leakage current was obtained by Keithley 237 High

Voltage SMU.

6.4.1 Capacitance at Room Temperature

Figure 6.2 depicts the room temperature capacitance-voltage (C-V) characterizations

of Capacitors A and B at different frequencies (10 kHz, 100 kHz and 1 MHz). The

applied DC bias was swept from -25 V to 25 V. Due to the existence of the thin nitride

layer, Capacitor B showed a slightly higher capacitance than that of Capacitor A. Based

on the experiments conducted at 10 kHz with zero DC bias, the measured capacitance of

Capacitors A and B were 2.805 pF and 2.935 pF, respectively. The dielectric constants

(εr) of PECVD TEOS oxide and nitride calculated from the measured capacitances at room temperature were 4.67 and 5.66, respectively. The calculation was based on,

(6-1)

where C, ε0, A and d are capacitance, permittivity of air, area of the capacitor and

thickness of the dielectric layer, respectively. The εr of PECVD nitride was calculated

from the capacitance of ONO stack using the formula for a multilayer capacitor:

(6-2)

Clayer 1 and Clayer 3 can be obtained by inserting the εr from Capacitor A into Eq. (6-2).

122

It can be seen that both capacitors exhibited a frequency-dependent behavior, i.e., the

measured capacitance decreased with increasing frequency. However, the variation in

10 kHz 100 kHz 1 MHz 2.808

2.804

2.8

2.796 Capacitance (pF)

2.792 -30 -20 -10 0 10 20 30 Voltage (V)

(a)

10 kHz 100 kHz 1 MHz 2.944

2.94

2.936

2.932

Capacitance (pF) 2.928

2.924 -30 -20 -10 0 10 20 30 Voltage (V)

(b)

Figure 6.2 The frequency dependence of capacitance measured at room temperature:

(a) Capacitor A; and (b) Capacitor B.

123

capacitance measured at different frequencies is smaller than 0.4 % in both cases.

Precision MIM capacitors are key building blocks for many analog, mixed-signal and

RF applications, e.g., switched capacitor circuits, digital-to-analog converters and analog frequency tuning circuits. However, nonlinearity in capacitance with different operating bias is a major obstacle because shifts in capacitance may lead to distortion in analog signals. This nonlinearity can be expressed by voltage coefficients of capacitance (VCC)

[125],

2 CV = C0 (α×V + β×V + 1) (6-3)

where CV is the measured capacitance under a given bias and C0 is the capacitance at zero

DC voltage. The quadratic term (α) indicates the variance of the capacitance for a given

applied bias, whereas the linear term (β) shows the balance of the capacitance. These two

coefficients can be extracted from second order polynomial curve fitting of the measured

data.

124

Capacitor A Capacitor B Frequency α (ppm/V2) β (ppm/V) α (ppm/V2) β (ppm/V)

1 MHz -2.5 51.6 21.9 13.6

100 kHz -6.1 56.7 22.2 13.2

10 kHz -6.4 53.3 17.4 2.6

Table 6.2 Quadratic and linear terms representing the voltage dependence of the two

MIM capacitors under different testing frequencies.

Table 6.2 lists α and β values for both structures at different testing frequencies. The

voltage range used in determining α and β of the designed MIM capacitors was from -5 V

to 5 V. The quadratic term in Capacitor A (αA) has a negative value and the low absolute

number (│α│) indicates that the SiO2 is insensitive to the DC bias. This agrees with the

data published elsewhere [126]. Though the ONO structure exhibited a higher │α│, it is

believed that by adjusting the thickness of those three layers, the VCC values of ONO

structure can be improved [127]. Despite the variation caused by the structural difference,

both capacitors meet the VCC requirements set by International Technology Roadmap

for Semiconductors (ITRS) [122] that α and β values should not exceed 100 ppm/V2 and

1000 ppm/V, respectively for a precision analog capacitor.

125

6.4.2 Capacitance at High Temperature

In addition to room temperature testing, capacitance of both MIM capacitors were

measured at elevated temperatures (up to 525 °C), as shown in Fig. 6.3. The measured

capacitances in both devices decrease with temperature. At 525 °C, the capacitance of

Capacitors A and B were 2.214 pF and 2.329 pF, respectively. Extracted from Fig. 6.2,

the temperature coefficients of capacitance (TCC) of Capacitors A and B from 25 °C to

525 °C were -1182 ppm/°C and -1218 ppm/°C, respectively. The obtained TCC values

were larger than other reported data; however, the highest test temperature was about 300

°C higher than previous studies. εr of PECVD TEOS oxide and nitride obtained at 525 °C

were 3.66 and 4.82, respectively.

126

Capacitor A Capacitor B 3.2

2.8

2.6

2.4 Capacitance (pF)

2.2

2 0 100 200 300 400 500 600 Temperature (˚C)

Figure 6.3 Measured capacitance of Capacitors A and B as a function of temperature.

6.4.3 Leakage Current at Room Temperature

In use with previously discussed SiC logic devices, leakage current is the most important parameter for the presented MIM capacitors. Figure 6.4 compares the measured leakage current densities of Capacitors A and B at room temperature under a

DC bias from 0 V to 250 V. It can be seen that both structures exhibit a very low leakage current at low electrical potential (< 100 V). The measured leakage current densities at 25

V were almost identical (Capacitor A: 9.15×10-7 A/cm2, Capacitor B: 8.20×10-7 A/cm2).

However, as the DC bias increased to 250 V, the leakage current density measured from

Capacitor B was about one order of magnitude lower than that of Capacitor A. Since there are very few logic applications requiring working voltages higher than 100 V, both

127

designed structures are suitable for room temperature operation under a moderate electrical potential.

Capacitor A Capacitor B 1.E-04

1.E-05 ) 2 1.E-06 (A/cm

1.E-07 0 50 100 150 200 250 300 Leakage Current Density Voltage (V)

Figure 6.4 Measured room temperature leakage current density as a function of

applied DC voltage for Capacitors A and B.

128

6.4.4 Leakage Current at High Temperature

Temperature testing was conducted on a probe station with a customized hot stage in

room air. All test conditions were the same as the room temperature measurement. From

the data obtained at 300 °C (Fig. 6.5(a)), both capacitors can still yield a leakage current

density lower than 1.8×10-6 A/cm2 when the applied voltage is smaller than 50 V. But as

the bias voltage increases to 150 V, the leakage current densities increase to 5.58 ×10-5

A/cm2 and 1.88 ×10-5 A/cm2 in Capacitors A and B, respectively. At 250 V, the measured

leakage currents reach 305 nA (7.63×10-4 A/cm2) and 68 nA (1.69×10-4 A/cm2). At 525

°C, the measured leakage current density (Fig. 6.5(b)) at 25 V increases slightly in both capacitors compared to the data at 25 °C and 300 °C. The difference observed at 525 °C between the two structures can still be ignored at this low bias region. However,

Capacitor B shows a much lower leakage current density (about 10× smaller) than

Capacitor A under higher applied voltage (from 100 V to 250 V).

Overall, Capacitor B exhibited a superior performance in terms of leakage current at all tested temperatures. Under a low working voltage (< 25 V), both structures are promising candidates for integration with our high temperature SiC devices. But the capacitor composed of a stack of PECVD oxide/nitride/oxide is preferred for high- voltage applications.

129

Capacitor A Capacitor B 1.E-02

1.E-03 ) 2 1.E-04

1.E-05 (A/cm

1.E-06

Leakage Current Density Density Current Leakage 1.E-07 0 50 100 150 200 250 300 Voltage (V)

(a)

Capacitor A Capacitor B 1.E-02

1.E-03 )

2 1.E-04

(A/cm 1.E-05

1.E-06 Leakage Current Density Density Current Leakage 1.E-07 0 50 100 150 200 250 300 Voltage (V)

(b)

Figure 6.5 Comparison of the leakage current density in Capacitors A and B

measured at: (a) 300 °C; and (b) 525 °C.

130

6.5 Breakdown Field

To determine the breakdown field, a DC voltage was swept from 0 V to 500 V with 1

V increment across top and bottom electrodes of both MIM capacitors. Each data point

was recorded 20 ms after the corresponding voltage was first applied.

Due to the presence of the thin PECVD nitride layer, Capacitor B exhibited a higher

breakdown field at all tested temperatures, as shown in Fig. 6.6. However, the difference

was small. At room temperature, the observed breakdown fields of Capacitors A and B were 7.47 MV/cm and 7.73 MV/cm, respectively. Both devices suffered from degradation in dielectric strength as the temperature increased. However, both Capacitors

A and B still held a breakdown field higher than 6 MV/cm at 525 °C.

6.6 Summary

The dielectric properties of two MIM capacitors using PECVD oxide (Capacitor A)

and PECVD oxide/nitride/oxide (Capacitor B) as dielectric layers were characterized at

room and high temperatures. Capacitor B showed higher capacitance and lower leakage current density at elevated temperatures. However, Capacitor A exhibited less voltage dependence and smaller TCC value. Table 6.2 summarizes all of the measured dielectric properties of these two capacitors.

131

Capacitor A Capacitor B 8

7.5

6.5

Breakdown Field (MV/cm) 6

5.5 0 100 200 300 400 500 600 Temperature (˚C)

Figure 6.6 Breakdown field of Capacitor A (PECVD TEOS oxide) and Capacitor B

(stack of PECVD TEOS oxide/nitride/TEOS oxide) as a function of

temperature.

132

Capacitor A Capacitor B

Capacitance at 25 °C 2.805 2.935 Measured at 10 kHz (pF)

Capacitance at 525 °C 2.214 2.329 Measured at 10 kHz (pF)

Leakage Current Density at 1.28×10-6 9.23×10-7 25 °C under 100 V (A/cm2)

Leakage Current Density at 5.05×10-5 5.18×10-6 525 °C under 100 V (A/cm2)

Breakdown Field at 25 °C 7.47 7.73 (MV/cm)

Breakdown Field at 525 °C 6.01 6.39 (MV/cm)

α = -6.4 ppm/V2 α = 17.4 ppm/V2 VCC at 10 kHZ β = 53.3 ppm/V β = 2.6 ppm/V

TCC -1182 ppm/°C -1218 ppm/°C

Table 6.3 Summary of the dielectric properties of the fabricated MIM capacitors.

133

CHAPTER 7

Conclusion

Extending the operational temperature of integrated circuits is an effective solution to

expensive thermal management and heat sinking requirements, which pose a major barrier to continued shrinking of electronics. Additionally, logic circuits that can operate to 600 °C are enabling for advanced propulsion systems. This dissertation has demonstrated both electric and mechanical SiC logic devices capable of operating at 500

°C and above.

Surface-micromachined, 2-terminal, cantilever-type, electrostatic SiC NEMS

switches having 75 nm gap were fabricated and characterized. The design envelop for the

length and width of the cantilever was 10 µm and 5 µm, respectively. These switches

exhibited threshold voltages less than 5 V, a value generally constant up to 600 °C. They

were operated more than 40 billion cycles at room temperature before mechanical failure

occurred. Operation at 400°C and above was limited due to the package wire bond

failure. The nearly-zero leakage current of these switches in OFF state, even at high

operating temperatures, presents the potential for their hybridization with electronics to

eliminate leakage power associated with transistors.

The contact resistance (usually in few MΩ range) of the forgoing switches was

dominated by the native oxide formed on the switch contacting surfaces at low actuation

134

voltages. At higher actuation voltages, the contact resistance values calculated using

Sharvin’s model fit the measured values well. Stiction (during release and in operation) and mechanical fracture were the observed failure mechanisms. Sticiton, however, was correlated to the roughness (Ra) of the switch contact surfaces. 60% of the switches with

Ra = 8 nm could be actuated billions of cycles. In contrast, 85% of the switches with Ra

= 1 nm failed after release because of stiction. For the switches operating more than a billion cycles, failure occurred due to fracture at the support end of the suspended cantilever electrode.

To explore improving the contact resistance of poly-SiC switches, XeCl laser exposure was performed on poly-SiC films in order to graphitize their surface. Confirmed by TEM studies, a 10 nm-thick, highly conductive turbostratic -carbon layer was formed as a result. Similar laser treatment of a semi-insulating single-crystalline 4H-SiC wafer led to a conductive surface with a measured ρ ≈ 0.004 Ω-cm.

Laterally-actuated, 3-terminal SiC NEMS switches fabricated by E-beam lithography with length = 8 µm, width = 150 nm and gap = 150nm were also demonstrated. Typical switches operated 21+ billion cycles at 25 °C and 2+ billion cycles at 500 °C; the measured leakage current was less than 100 fA. The first ever electromechanical inverter, operating at 500 °C was demonstrated, formed by two 3-terminal SiC NEMS switches with a switching speed of 500 kHz. This achievement creates a pathway toward energy- efficient high temperature computation.

Electrical characteristics of an inverter, NAND and NOR logic gates capable of high temperature operation using 6H-SiC depletion-mode JFETs were studied. The fabricated

SiC inverter consisted of three n-channel normally-on JFETs with -7 V threshold voltage.

135

The unit transistor size is 160 µm wide and 10 µm long. Universal gates (NAND and

NOR) were composed of four transistors. All logic gates operated in the temperature range of 25 °C to 550 °C. Though the fabricated SiC electronics exhibited reliable functionalities in the temperature range of 25 °C to 550 °C, as expected, the measured leakage current increased significantly with temperature.

Two MIM capacitors were fabricated and studied to characterize the high temperature dielectric properties of PECVD TEOS silicon dioxide and PECVD silicon dioxide/nitride/dioxide (ONO) stack used in the mechanical and electrical SiC logic devices. The MIM capacitor with ONO stack exhibited a higher capacitance and lower leakage current at both room temperature and 525 °C. On the other hand, the PECVD

TEOS silicon dioxide capacitor showed less temperature and voltage dependences in the same temperature range.

136

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