Silicon Carbide Pressure Sensors for High Temperature Applications

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SILICON CARBIDE PRESSURE SENSORS FOR HIGH TEMPERATURE APPLICATIONS

by SHENG JIN

Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy

Dissertation Adviser: Dr. Mehran Mehregany

Department of Materials Science and Engineering

CASE WESTERN RESERVE UNIVERSITY

May, 2011

To my wife and my son

Contents

CONTENTS I

LIST OF TABLES IV

LIST OF FIGURES V

ACKNOWLEDGEMENT X

ABSTRACT XII

CHAPTER 1 INTRODUCTION 1

1.1 Problem to be addressed 1

1.2 Objective 5

1.3 Review of SiC materials and technology 6 1.3.1 Material properties of SiC 6 1.3.2 Processing technologies 8 1.3.2 SiC surface micromachining 11 1.3.3 SiC reactive ion etching 12 1.3.4 MEMS packaging 13

CHAPTER 2 HIGH-TEMPERATURE SIC PRESSURE SENSOR DEVELOPMENT 18

2.1 Literature review 18 2.1.1 State-of-the-art, high-temperature pressure sensors 18

2.2 Pressure sensing mechanisms 25

2.3 Prior related work in our group 28

2.4 Challenges and limitations 32

CHAPTER 3 DESIGN OF SIC CAPACITIVE PRESSURE SENSOR35

3.1 Introduction 35

3.2 Pressure sensor design 37

3.2.1 Small-deflection mode, circular diaphragm 37 3.2.2 Contact mode, circular diaphragm 46 3.2.3 Analytical design of 50 mmHg pressure sensor 52

CHAPTER 4 FINITE ELEMENT ANALYSIS 57

4.1 Introduction 57

4.2 COMSOL simulation for diaphragm deflection 59 4.2.1 Small-deflection mode simulation 59 4.2.2 Contact mode simulation 60

4.3 Thermal mismatch stress effect 64 4.3.1 Background 64 4.3.2 Analytical model 65 4.3.3 COMSOL simulation 70

CHAPTER 5 FABRICATION OF SIC CAPACITIVE PRESSURE SENSORS 82

5.1 Introduction 82

5.2 Fabrication Process 82 5.2.1 Process Flow Overview 82

5.3 Fabrication challenges 95 5.3.1 Mask 1 Photolithography 95 5.3.2 Etch control of RIE to precisely stop on underlying film 96 5.3.3 Non-uniformity of BOE etch 98 5.3.4 RIE of SiC films 100

5.4 Fabrication verification 104

CHAPTER 6 METALLIZATION DEVELOPMENT 111

6.1 Introduction 111

6.2 Experimental 119 6.2.1 Selection of measurement techniques 119 6.2.2 Experiment 121

6.3 Result and discussion 125

CHAPTER 7 PRESSURE SENSOR CHARACTERIZATION 151

7.1 Introduction 151

7.2 Test setup 153 7.2.1 Basic theory 153 7.2.2 Measurement setup 154

7.2.3 Packages 156

7.3 Dielectric property study of SiNx 160

7.4 Sensor array testing 165 7.4.1 Analytical calculation versus experimental data 166 7.4.2 Comparison between sensors with different sensing gaps 170 7.4.3 Comparison between sensors fabricated on SiC and Si substrates 173 7.4.4 Comparison between small deflection mode and contact mode sensors 180 7.4.5 Testing of contact mode SiC substrate sensors for different pressure ranges 189

7.5 Conclusion 199

CHAPTER 8 CONCLUSION 200

APPENDIX A 204

BIBLIOGRAPHY 206

List of Tables

Table 1.1 Material properties of SiC, GaAs, Silicon, and Diamond at 300K. 8 Table 1.2 Properties of some ceramic substrates. 17 Table 3.1 Target sensor specifications for high temperature applications. 35 Table 3.2 Parameters and materials constants used in modeling the sensors. 37 Table 3.3 Performance comparison between pressure sensor arrays for different range and process parameters (small-deflection mode). 45 Table 3.4 Performance comparisons between pressure sensor arrays for different range and process parameters (contact mode). 52 Table 3.5 Analytical design of 0.108 MPa (15.7 psi) small deflection mode absolute pressure sensor. 53 Table 3.6 Analytical design of 0.108 MPa (15.7 psi) contact mode absolute pressure sensor. 54 Table 5.1 Process parameters of 9245 Photoresist. 86 Table 5.2 Test process and the corresponding criteria. 97 Table 6.1 Experimental methods for specific contact resistance ρc measurement. 119 Table 6.2 Atomic concentration of elements at line scan points. 149 Table 7.1 Performance comparison between SiC-S-15-54-500 and SiC-S-05-37-500. 173 Table 7.2 Performance comparison between SiC-S-15-47-700 and Si-S-15-47-700 at room temperature. 175 Table 7.3 Performance comparison between SiC-S-15-47-700 and Si-S-15-47-700 at 500 ºC. 176 Table 7.4 Performance of Si-T-15-68-1200 at different temperatures. 179 Table 7.5 Performance of SiC-S-05-37-500 at different temperatures. 183 Table 7.6 Performance of SiC-T-05-70-500 at different temperatures. 188 Table 7.7 Performance comparison between SiC-S-05-37-500 and SiC-T-05-70-500. 189 Table 7.8 Sensor array performance of SiC-T-15-70-1000 at different temperatures. 194 Table 7.9 Performance of SiC-T-15-95-300 at different temperatures. 198

List of Figures

Figure 2.1 Sensor fabrication process ...... 29 Figure 2.2 Type A die layout ...... 31 Figure 2.3 Type B die layout ...... 31 Figure 2.4 Plan view micrograph of Type B die ...... 32 Figure 2.5 Delamination of metal pads and interconnections of the sensor array ...... 33 Figure 3.1 Simulation plot of capacitance versus pressure for r=17 μm ...... 40 Figure 3.2 Simulation plot of capacitance versus pressure for r=20 μm ...... 40 Figure 3.3 Simulation plot of capacitance versus pressure for r=28 μm ...... 41 Figure 3.4 Simulation plot of capacitance versus pressure for r=41 μm ...... 41 Figure 3.5 Simulation plot of capacitance versus pressure for r=45 μm ...... 42 Figure 3.6 Simulation plot of capacitance versus pressure for r=54 μm ...... 42 Figure 3.7 Simulation plot of capacitance versus pressure for r=68 μm ...... 43 Figure 3.8 Simulation plot of capacitance versus pressure for r=80 μm ...... 43 Figure 3.9 Simulation plot of capacitance versus pressure for r=95 μm ...... 44 Figure 3.10 Schematic drawing of an equivalent capacitor model in contact mode ...... 48 Figure 3.11 Plot of capacitance versus pressure for r=70 μm ...... 49 Figure 3.12 Plot of capacitance versus pressure for r=58 μm ...... 50 Figure 3.13 Plot of capacitance versus pressure for r=47 μm ...... 50 Figure 3.14 Plot of capacitance versus pressure for r=38 μm ...... 51 Figure 3.15 Plot of capacitance versus pressure for r=31 μm ...... 51 Figure 3.16 Performance of a 0.5 μm-gap, 90 μm-radius, 1 μm-thick diaphragm pressure sensor with 0.46fF/Pa (3.2 pF /psi) sensitivity and 0.94% nonlinearity ...... 56 Figure 4.1 A schematic of the 3D COMSOL model ...... 58 Figure 4.2 Deflection of a r=48 μm diaphragm under 3.4 MPa (500 psi) pressure from FEA. r=0 always at the diaphragm center ...... 59 Figure 4.3 FEA compared with analytical model for deflection of a diaphragm under pressure (r=48 μm and gap=2 μm)...... 59 Figure 4.4 Deflection of a diaphragm with r=58 μm under different pressures from FEA (0.4 μm gap) ...... 61 Figure 4.5 Comparison between FEA and analytical models at 2.8 MPa (400 psi) pressure ...... 62 Figure 4.6 Comparison between FEA and analytical models at 3.4 MPa (500 psi) pressure ...... 62 Figure 4.7 Comparison between FEA and analytical models at 4.1 MPa (600 psi) pressure ...... 63 Figure 4.8 A simple structure for film stress calculation ...... 65 Figure 4.9 Temperature dependent linear expansion coefficient of poly-SiC and Si .....67 Figure 4.10 Thermal expansion stress for a poly-SiC film on Si wafer as a function of temperature by analytical calculation ...... 68

Figure 4.11 Thermal mismatch stress impact on a small-deflection mode sensor designed for a pressure range of 5.2 MPa (750 psi), wherein the substrate is Si (50 μm radius and 1.5 μm gap) ...... 69 Figure 4.12 Thermal mismatch stress impact on a small-deflection mode sensor designed for a pressure range of 1.7 MPa (250 psi), wherein the substrate is Si (67 μm radius and 1.5 μm gap) ...... 69 Figure 4.13 The initial gap size change caused by thermal expansion mismatch stress based on COMSOL simulation (58 μm radius and without the LSN layer) ...... 72 Figure 4.14 Thermal stress in the poly-SiC diaphragm based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer) ...... 72 Figure 4.15 The performance of a SiC substrate sensor accounting for the thermal mismatch stress based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer) ...... 73 Figure 4.16 The performance of a Si substrate sensor accounting for the thermal mismatch stress based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer) ...... 74 Figure 4.17 The initial gap size change caused by thermal mismatch stress based on COMSOL simulation, with the substrate bottom fixed in x, y and z directions (58 μm radius and 2 μm gap and the LSN layer) ...... 75 Figure 4.18 The thermal mismatch stress in the diaphragm poly-SiC film based on COMSOL simulation, with substrate bottom fixed in x, y, and z directions (58 μm radius and 2 μm gap and with the LSN layer) ...... 75 Figure 4.19 The initial gap size change caused by thermal mismatch stress based on COMSOL simulation, with substrate bottom fixed in z-direction (58 μm radius and 2 μm gap and with the LSN layer) ...... 76 Figure 4.20 Thermal expansion mismatch stress in the diaphragm poly-SiC film based on COMSOL simulation, with bottom fixed in z-direction (58 μm radius and 2 μm gap and with the LSN layer) ...... 77 Figure 4.21 COMSOL simulation of a 3.4 MPa (500 psi) small-deflection mode sensor on a Si substrate under thermal mismatch stress (58 μm radius and 2 μm gap and with the LSN layer) ...... 78 Figure 4.22 COMSOL simulation of a 3.4 MPa (500 psi) small-deflection mode senor on a SiC substrate under thermal mismatch stress (58 μm radius and 2 μm gap and with the LSN layer) ...... 78 Figure 4.23 The temperature-dependent LSN dielectric constant ...... 79 Figure 4.24 Experimental data from a 5.2 MPa (750 psi) small-deflection mode sensor on a Si substrate under thermal mismatch stress (50 μm radius and 1.5 μm gap) ...... 81 Figure 5.1 Cross-sectional schematic view of the sensor fabrication process ...... 84 Figure 5.2 The SiC bottom electrode patterned by Technics 800 after the photoresist mask is removed (on Si substrate) ...... 88 Figure 5.3 The SiC bottom electrode patterned by Technics 800 after the photoresist mask is removed (on SiC substrate) ...... 89 Figure 5.4 Tapping mode AFM image of a 3 μm-thick poly-SiC film surface before polishing ...... 91

Figure 5.5 Tapping mode AFM image of a 3 μm-thick poly-SiC film surface after polishing ...... 92 Figure 5.6 The C-V features used for BOE release monitoring ...... 93 Figure 5.7 Optical micrograph showing proper pattern definition from Mask 1 ...... 95 Figure 5.8 Test die for process monitoring ...... 97 Figure 5.9 Non-uniformity of the BOE etch for the anchor features ...... 98 Figure 5.10 Non-uniformity of BOE etch of square cavities ...... 99 Figure 5.11 Uniformity of BOE etch after ashing in an Oxygen Plasma the test features ...... 99 Figure 5.12 Uniformity of BOE etch after ashing in an Oxygen Plasma the anchor features ...... 100 Figure 5.13 The formation of a suspended stringer ...... 102 Figure 5.14 Optical micrograph of a broken stringer ...... 103 Figure 5.15 Features without stringers after poly-SiC etch by deep RIE ...... 103 Figure 5.16 Optical micrograph of pressure sensors in an array on a Si substrate ...... 104 Figure 5.17 Optical micrograph of pressure sensors in an array on a SiC substrate ...... 104 Figure 5.18 SEM image of pressure sensors in an array on a Si substrate ...... 105 Figure 5.19 Cross-sectional SEM of a pressure sensor on a SiC substrate ...... 106 Figure 5.20 Cross-sectional SEM of a pressure sensor on a SiC substrate ...... 107 Figure 5.21 Magnified view of Fig. 5.20 ...... 108 Figure 5.22 Cross-sectional SEM showing the anchor region of a pressure sensor diaphragm ...... 108 Figure 5.23 Cross-sectional SEM of a sensor with a 0.5 μm gap on a SiC substrate ....109 Figure 5.24 10 minute leakage test at 6.9 MPa (1,000 psi) for a sensor on a SiC substrate with a70 μm-radius diaphragm operating in contact mode, where (1) is the initial measurement and (2) measurement after 10 minutes ...... 110 Figure 6.1 Energy levels and band structure of semiconductor-metal Schottky contacts ...... 111 Figure 6.2 Energy levels and band structure of semiconductor-metal Ohmic contacts ...... 112 Figure 6.3 Ternary phase diaphragm of Ni-Si-C at 900ºC ...... 113 Figure 6.4 Ternary phase diaphragm of Ti-Si-C at 700ºC ...... 116 Figure 6.5 L-TLM structure for Ohmic contact measurement ...... 123 Figure 6.6 I-V data between two nearby contact pads for a typical as-deposited contact ...... 125 Figure 6.7 Total resistance versus contact pad separation for a typical as-deposited contact ...... 127 Figure 6.8 ρc as a function of post-deposition anneal temperature in a nitrogen ambient. All anneals are for 30 minutes...... 128 Figure 6.9 ρc as a function of post-deposition anneal time at 600ºC in a nitrogen ambient ...... 129 Figure 6.10 Aging time test of ρc at 550ºC in air, following a 45-min anneal at 600ºC in nitrogen ambient ...... 130 Figure 6.12 Surface morphology of Ohmic contact after 30 min anneal at 500ºC ...... 133 Figure 6.13 Surface morphology of Ohmic contact after 30 min anneal at 600ºC ...... 134

Figure 6.14 The Auger analysis on the surface after 600ºC anneal in N2 ...... 135 Figure 6.15 Surface morphology of Ohmic contact after 30 min anneal at 700ºC ...... 135 Figure 6.17 Surface morphology of Ohmic contact after 30 min anneal at 800ºC ...... 136 Figure 6.18 The Auger analysis on the surface after 800ºC anneal in N2 ...... 137 Figure 6.19 AES depth profile of the metal surface after 800ºC anneal in N2 ...... 138 Figure 6.20 AES depth profile for a typical as-deposited contact ...... 139 Figure 6.21 AES depth profile of a typical contact following a 120-min anneal at 600ºC in a nitrogen ambient...... 141 Figure 6.22 AES depth profile of a typical contact following a 100-hours aging test at 600ºC in air ...... 142 Figure 6.23 Binding energy shift of the Ta4f photoelectron peak along depth profile ..143 Figure 6.24 Binding energy shift of the Pt4f photoelectron peak ...... 144 Figure 6.25 Binding energy shift of the Si2s photoelectron peak ...... 145 Figure 6.26 Binding energy peak of the O1s at surface ...... 146 Figure 6.26 TEM sample prepared by FIB ...... 147 Figure 6.27 STEM cross-sectional image of the multilayer metallization ...... 148 Figure 6.28 STEM line scan profile ...... 148 Figure 7.1 Sensor types used for characterization along with their nomenclature ...... 152 Figure 7.2 Model for a capacitor with parasitic elements ...... 154 Figure 7.3 Schematic of the test measurement setup ...... 154 Figure 7.4 Rendering of heating fixture ...... 155 Figure 7.5 Individual brass bar showing thermocouple placement ...... 156 Figure 7.6 Packages used for pressure sensor packaging and testing ...... 157 Figure 7.7 Thermal reliability tests at 550ºC in air for the metal flatpack package .....158 Figure 7.8 Thermal reliability tests at 550ºC in air for the ceramic DIP package ...... 159 Figure 7.9 The C-V structure used for dielectric constant study of SiNx ...... 161 Figure 7.10 Measured result of C-V structure compared with the calculation ...... 162 Figure 7.11 Leakage current measurements on sensor arrays ...... 162 Figure 7.12 D measurements of a SiC sensor array at different temperatures ...... 164 Figure 7.13 Measured response versus analytical calculations for SiC-S-15-54-500 ....167 Figure 7.14 Measured response versus analytical calculation for SiC-S-05-37-500 .....167 Figure 7.15 Measured response versus analytical calculation for SiC-S-15-47-700 .....168 Figure 7.16 Measured response versus analytical calculation for SiC-T-15-70-1000 ...169 Figure 7.17 Measured response versus analytical calculation of device SiC-T-15-95-300 ...... 169 Figure 7.18 Measured response versus analytical calculation for SiC-T-05-70-500 .....170 Figure 7.19 Measured response versus analytical calculation for Si-T-15-68-1200 ...... 170 Figure 7.20 Capacitance versus pressure (C vs. P) plot for SiC-S-15-54-500 at room temperature (decreasing load) ...... 171 Figure 7.21 C vs. P plot for SiC-S-05-37-500 at room temperature (decreasing load) ..172 Figure 7.22 C vs. P plot for SiC-S-15-47-700 at room temperature (decreasing load) ..174 Figure 7.23 C vs. P plot for Si-S-15-47-700 at room temperature (decreasing load) ....174 Figure 7.24 C vs. P plot for SiC-S-15-47-700 at 500 ºC (decreasing load) ...... 175 Figure 7.25 C vs. P plot for Si-S-15-47-700 at 500 ºC (decreasing load ...... 176 Figure 7.26 C vs. P plot for Si-T-15-68-1200 at room temperature (increasing load) ...177 Figure 7.27 C vs. P plot for Si-T-15-68-1200 at 300ºC (increasing load) ...... 177

Figure 7.28 C vs. P plot for Si-T-15-68-1200 at 400ºC (increasing load) ...... 178 Figure 7.29 Capacitance measurements repeated 40 times at 400ºC ...... 179 Figure 7.30 Hysteresis plot for SiC-S-05-37-500 at room temperature over four cycles...... 181 Figure 7.31 C vs. P plot for SiC-S-05-37-500 at 100ºC (increasing load) ...... 181 Figure 7.32 C vs. P plot for SiC-S-05-37-500 at 200ºC (increasing load) ...... 182 Figure 7.33 C vs. P plot for SiC-S-05-37-500 at 400ºC (increasing load) ...... 183 Figure 7.34 Repeatability test for SiC-T-05-70-500 at room temperature over 5 days (increasing load) ...... 184 Figure 7.35 C vs. P plot for SiC-T-05-70-500 at 100ºC (increasing load) ...... 185 Figure 7.36 C vs. P plot for SiC-T-05-70-500 at 200ºC (increasing load) ...... 185 Figure 7.37 C vs. P plot for SiC-T-05-70-500 at 300ºC (increasing load) ...... 186 Figure 7.38 C vs. P plot for SiC-T-05-70-500 at 400ºC (increasing load) ...... 186 Figure 7.39 C vs. P plot for SiC-T-05-70-500 at 500ºC (increasing load) ...... 187 Figure 7.40 C vs. P plot for SiC-T-05-70-500 at 550ºC (increasing load) ...... 187 Figure 7.41 C vs. P plot for SiC-T-05-70-500 for temperatures up to 550ºC (increasing load) ...... 188 Figure 7.42 C vs. P plot for SiC-T-15-70-1000 at room temperature (increasing load) 190 Figure 7.43 C vs. P plot for SiC-T-15-70-1000 at room temperature (decreasing load) 191 Figure 7.44 Hysteresis plot for SiC-T-15-70-1000 at 100ºC ...... 192 Figure 7.45 C vs. P plot for SiC-T-15-70-1000 for temperatures up to 200ºC (increasing load) ...... 192 Figure 7.46 C vs. P plot for SiC-T-15-70-1000 at 500ºC (increasing load)...... 193 Figure 7.47 C vs. P plot for SiC-T-15-70-1000 for temperatures up to 500ºC (increasing load) ...... 194 Figure 7.48 C vs. P plot for SiC-T-15-95-300 at room temperature (increasing load)...195 Figure 7.49 C vs. P plot for SiC-T-15-95-300 at 100ºC (increasing load) ...... 195 Figure 7.50 C vs. P plot for SiC-T-15-95-300 at 200ºC (increasing load) ...... 196 Figure 7.51 C vs. P plot for SiC-T-15-95-300 at 500ºC (increasing load) ...... 196 Figure 7.52 C vs. P plot for SiC-T-15-95-300 at 550ºC (increasing load) ...... 197 Figure 7.53 C vs. P plot for SiC-T-15-95-300 for temperatures up to 550ºC (increasing load) ...... 197

Acknowledgement

I own a deep sense of gratitude to my research advisor, Professor Mehran Mehregany, for his guidance, encouragement and support (both technical and financial) throughout this project. I am grateful to my committee, Professors Arthur Heuer, Pirouz Pirouz and

James Cawley, for their guidance, as well as educating me with fundamental coursework.

I would like to thank Dr. Li Chen for his prior work, which was an invaluable resource and provided a solid foundation for this thesis. Drs. Xiao-an Fu and Jigong Lee educated me about MEMS and electronics. Special thanks to Mr. Hari Rajgopal for his support in fabrication work and continued research guidance. I appreciate the technical assistance of Ron Jezeski, Li Chen (MFL) and Ed Jahnke for instrument maintenance and operating instruction. It is my pleasure to thank others who made this thesis possible: Dr.

Wayne Jennings for XPS and Auger; Alan K McIlwain for SEM; Mr. Shubin Yu for sputtering and packaging; and Dr. Reza Shaghi-Moshtaghin and Dr. Amir Avishai for

TEM and FIB. The assistance of administrative staff including Meredith Stanton, Patsy

Harris, Annette Messina and Vickie Nichols is also appreciated.

I would like to acknowledge Amita Patil, Grant McCallum, Noppasit

Laotaveerungrueng for their assistance with electronics and instrumentation. Special thanks go to David Tian for his help in developing test circuit boards. I am indebted to many of my colleagues for their various technical and friendship support, including

Te-Hao Lee, Man-I Lei, Shih-Shian Ho, Kevin Speer, Charlie Lin and Chia-Wei Soong.

I would like to thank my wife and my parents. This thesis would not be possible

without their encouragement and support. I am grateful to my parents-in-law, who have sacrificed a lot to help take care of my son during my doctoral study. I would like to dedicate this thesis to my son for bringing happiness to my life.

Finally, I would like to acknowledge financial support from Case Western Reserve

University through the Case Prime Fellowship. This work was also supported in part by

DARPA Grant #NBCH1050002.

Silicon Carbide Pressure Sensors for High Temperature Applications

Abstract

SHENG JIN

Leveraging the superior properties of silicon carbide (SiC) for harsh environment and demanding applications, a series of SiC capacitive pressure sensors have been developed and characterized for use up to 550ºC . To address the related high-temperature-capable metallization need, a thermally stable Ti/TaSi2/Pt Ohmic contact was developed for heavily-doped polycrystalline 3C-SiC films used in the construction of the pressure sensors. These contacts showed very good linearity with specific contact resistance as low as 5.710-6 Ω-cm2 without thermal annealing following metal sputtering. The metallization demonstrated robustness after being subjected to an aging test in air at 550ºC for 1000 hours. Specific contact resistance remained stable in the range of ~10-5 Ω-cm2.

A finite element analysis tool was used to model diaphragm displacement and study the thermal mismatch stress effect on sensor behavior for different substrates. The simulation confirmed that dielectric constant variation with temperature, rather than thermal expansion mismatch stress, dominated the capacitance change. SiC Sensors were fabricated on both SiC and Si substrates, and characterized at room temperature and

500ºC. Both sets of sensors demonstrated similar performance, which were in agreement with the simulation results.

The capacitance versus pressure behavior of fabricated capacitive SiC pressure sensors were characterized from 2.1 MPa (300 psi) to 8.3 MPa (1200 psi) and for

temperatures up to 550ºC. The measurement results were found to be in agreement with the analytical calculations.

Comparison tests were also performed for sensing capacitance gap sizes and operating modes (i.e., small deflection and touch mode of the diaphragm). Sensors with

0.5 μm sensing capacitance gap showed improved sensitivity, while allowing for smaller diaphragms for a given pressure. With respect to operating modes, contact mode sensors exhibited superior performance to small deflection mode sensors in terms of sensitivity, nonlinearity and resolution. Thus, for a single sensor on a SiC substrate with 0.5 μm gap and 70 μm diaphragm radius, a repeatable performance of 0.057 fF/Pa (0.39 pF/psi) sensitivity and 2.0% nonlinearity was obtained at 550ºC for contact mode operation.

Chapter 1

INTRODUCTION

1.1 Problem to be addressed

The potential of using silicon carbide (SiC) devices in harsh environment applications has long been recognized. Harsh environments include high temperatures, highly corrosive environments, strong vibrations and high radiation; these environments often occur in application fields such as aerospace, automotive, power and propulsion, down-hole oil/gas well logging, industrial process control, nuclear power and biomedical monitoring [1]. Unfortunately, its physical properties limit silicon (Si) in such applications. Due to its narrow band gap, the operating temperature and radiation tolerance of Si electronics are limited. The corrosion and erosion resistance of Si is also limited. Si is also relatively easily etched by chemicals, and its mechanical strength decays at high temperature. In contrast, SiC is a wide band gap semiconductor, making it capable of high temperature and radiation hard electronics realization. Its mechanical properties are superior to Si. SiC has high field breakdown limit, thermal conductivity and chemical tolerance to many acid and base solutions. These unique properties have made it an enabling platform for not only robust sensors but also for high temperature electronics.

Improvements to combustion control in gas turbine, diesel and internal combustion engines can benefit from harsh environment capable sensors and

1 electronics. The resulting benefits of advanced engine instrumentation are enhanced fuel efficiency, reduction of emissions and improved reliability. Sensors and electronics made from high-temperature capable and thermally-stable platform materials (such as SiC) may be keys to such advanced instrumentation.

Among several parameters related to combustion control, pressure is one of the most commonly measured physical variables. Diaphragm-based devices are commonly used for pressure measurement, in which pressure is determined by monitoring the diaphragm deflection induced by the applied pressure. Reference pressure is obtained by a sealed chamber or a pressure port in order to measure absolute or gauge pressures, respectively. Classified by the diaphragm deflection transduction mechanism, the most common schemes are piezoresistive and capacitive. The former has piezoresistors mounted on or in a diaphragm; for thin diaphragms and small deflections, the resistance change is linear with applied pressure. The latter is usually based on a parallel-plate capacitor configuration, translating a pressure change into a capacitance variation. The capacitive scheme provides comparatively higher sensitivity, lower temperature coefficient, higher overload pressure and lower power consumption.

As just described, to enhance fuel efficiency, reduce emissions and improve reliability of future vehicles, a pressure sensor with thermal stability, substantial performance and cost advantages over existing technology is in great need. A capacitive SiC pressure sensor promises the advantage of extending the operating

2 capability to high temperatures. However, as in all capacitive sensors, signal loss from parasitics is a disadvantage which has to be overcome by integrated (i.e., on-chip) or hybrid (i.e., in package) electronics to isolate the high impedance sensor node. For high temperature operation, the electronics must be high temperature capable. SiC integrated circuits (ICs), also developed in our laboratory[2], can be co-packaged with capacitive SiC pressure sensors to develop low-cost, miniature pressure sensors capable of reaching operating temperatures of 600ºC.

In this thesis, polycrystalline 3C-SiC (hereafter "poly-SiC") thin films are used to realize capacitive pressure sensors. Poly-SiC is a preferred material for low-cost

SiC microfabricated sensors (as compared to single-crystal SiC), as high quality films can be deposited in batch over large area substrates (as high as 6-inches) relatively inexpensively.

A key element in the development of high-temperature SiC devices that incorporate electrical elements is reliable and stable metal-SiC Ohmic contacts. The wide band gap of SiC, about 3 times higher than that of Si, results in a Schottky barrier height larger than 1 eV for almost all metals on 6H- and 4H-SiC (3C has a

0.6 eV lower bandgap energy than 6H-SiC). This presents a serious challenge in obtaining a good Ohmic contact with a low specific contact resistance (SCR).

Long-term contact performance stability is another challenge, arising from the metal-SiC reaction at the contact with time and temperature.

Nickel is the most widely used metal for Ohmic contacts on n-type SiC;

3 however, the required post-metallization anneal at high temperatures causes an undesirably rough interface morphology, inhibiting long-term reliability and leading to contact degradation [3]. Titanium-based contacts have also been widely investigated; in particular, Okojie, et al. [4] reported a thermally-stable Ohmic contact on n-type 4H- and 6H-SiC, which is extended here to poly-SiC. In his work, an SCR as low as 110-5 Ω-cm2 and reliable contact performance over 1000 hours at

600ºC in air were reported; furthermore, with a passivation Si3N4 layer deposited on top of the metallization, the 6H-SiC ICs in his work survived 3000 hours of operation at 500ºC in air [5].

As motivated in this thesis, poly-SiC is a preferred choice for low-cost sensors, particularly for mechanical devices such as pressure sensors. As a result, thermally-stable Ohmic contacts to poly-SiC are investigated in this thesis.

For reliable operation at elevated temperature, it is preferable to fabricate the main parts of the sensor with the same material to avoid thermal mismatch effects.

Chen, et al. reported the first all-SiC capacitive pressure sensor eliminating the thermal expansion mismatch between the diaphragm and the substrate [6]. However, it is beneficial to develop SiC sensors on Si substrate for the cost advantages, especially in cases where the effects caused by thermal expansion mismatch are tolerable. To the best of our knowledge, no study related to the thermal expansion mismatch in SiC capacitive pressure sensors with Si substrates has been reported. We investigate the mechanical and electrical effects caused by thermal mismatch stress in

4 both kinds of sensors (i.e., on Si or SiC) in this thesis.

1.2 Objective

The prime objective of this dissertation is to design, test and compare the performance of microfabricated SiC capacitive pressure sensors on SiC and Si substrates for operation up to 550ºC . The effect of thermal expansion mismatch stress through both analytical calculation and FEA is studied. Pressure sensors are designed for a wide range of operating pressures, 0 to 6895 Pa (1 psi) for medical applications and 0 to 34.5 MPa (0 to 5,000 psi) for industrial applications. Sensors with circular diaphragms operating in the small deflection and contact mode regimes have been designed. For improved sensor sensitivity, 0.5 μm gap sensors are prototyped in addition to 1.5 μm gap sensors.

A key step toward the foregoing objective above is to develop a thermally-stable Ohmic contact to poly-SiC to enable SiC sensors and electronics

capable of stable operation at high temperatures. A multi-layer Ti/TaSi2/Pt metallization is chosen for this purpose due to its promisingly stable contact chemistry with SiC and durability when heated in air. The effect of annealing on the specific contact resistance, long term stability, high temperature interface reactions, and other performance characteristics are studied.

1.3 Review of SiC materials and technology

1.3.1 Material properties of SiC

SiC occurs in many different crystal structures, called polytypes. Despite the fact that all SiC polytypes are chemically the same atomic composition of carbon and silicon, each polytype has its own distinct set of semiconductor properties depending on the stacking periodicity of similar planes. While more than 250 SiC polytypes have been identified to date, only three crystalline structures exist: cubic, hexagonal and rhombohedral. The cubic structure of SiC has been referred to as

β-SiC, and the hexagonal and rhombohedral structures have been called α-SiC. By adopting a more descriptive nomenclature that identifies both the crystalline symmetry and stacking periodicity, cubic SiC is denoted 3C-SiC, wherein ―3‖ indicates the number of stacking layer positions within one period and ―C‖ refers to cubic symmetry. 3C-SiC is the only known cubic polytype. In the same manner, the most common α-SiC polytypes are denoted as 2H-SiC, 4H-SiC, and 6H-SiC.

Compared with silicon, SiC has a larger band gap ranging from 2.3 eV to 3.4 eV, a higher breakdown field (0.8-3×106 V/cm), a higher thermal conductivity (4.9

Wcm-1K-1) and a higher saturation velocity (2×107 cm/s). These properties make SiC suitable for fabrication of high-temperature, high-power and high-frequency electronic devices. The electric properties of SiC differ according to different polytypes, for example, the band gap for SiC ranges from 2.3 eV for 3C-SiC to 3.4 eV for 2H-SiC. Despite having the smallest band gap, 3C-SiC has the highest 6 electron mobility (1000 cm2 /Vs) and saturation drift velocity (107 cm/s) [7].

Other well-known properties include high hardness, chemical inertness to most of acids and high melting point (sublimation), making SiC an attractive material for sensors operating in harsh environments. Compared with diamond, another wide band gap semiconductor, one of the attractive features of SiC is that it can be doped with p- and n-type, by which some important electric properties could be adjusted.

The surface of SiC can be passivated by the formation of a thermal SiO2 layer, but the oxidation rate is very slow when compared with Si. A summary comparing important semiconductor properties of 3C- and 6H-SiC along with other noted semiconductors is presented in Table 1.1 [8].

Table 1.1 Material properties of SiC, GaAs, Silicon, and Diamond at 300K.

Property 3C-SiC (6H-SiC) GaAs Si Diamond

Melting point (ºC) 2830*1 1238 1415 1400*2 Thermal Conductivity (W/cm ºC) 5 0.5 1.5 20

Coeff.Thermal Expan.(10-6/ ºC) 4.2 6.86 2.6 1 Young’s Modulus (GPa) 448 75 190 1035

Density (kg/m3) 3200 5320 2330 3520 Physical Stability excellent fair good fair

Bandgap (eV) 2.2(2.9) 1.424 1.12 5.5

Electron Mobility (cm2/Vs) 1000(600) 8500 1500 2200 Hole Mobility 40 400 600 1600

Breakdown Voltage (106 V/cm) 4 0.4 0.3 10 Dielectric Constant 9.72 13.1 11.9 5.5

1sublimation temperature, 2 phase change temperature

1.3.2 Processing technologies

SiC single crystal growth

To date, the commercial development of devices exploiting the attributes of SiC has been limited due to the lack of large-sized, defect free wafers in volume production at competitive prices. There are two primary technologies employed today to grow bulk SiC:

Physical Vapor Transport (PVT) – This is the most commonly used growth technique. The SiC source material sublimes and then the vapor condenses on the substrate. During PVT, high purity SiC powder is sublimed from a crucible in order to deposit SiC material along the length of a crystalline SiC seed. This method is used to

8 produce 4H- and 6H-SiC crystals. The major advantage of this approach is that the growth is comparatively inexpensive and provides high quality epitaxial layers. The primary disadvantage is that defects and polytype inclusions may form due to growth parameter instability. Much work has been done to improve sublimation epitaxy as an effective technique for growth of thick epitaxial layers [9, 10].

High Temperature Chemical Vapor Deposition (HTCVD) – In this technique, the solid source materials are replaced by gases such as silane and propane. The advantage of this approach is that it offers greater control over the sublimation process, resulting in fewer defects. It is possible to control native point defects and to realize excellent purity of the grown crystals. In addition, HTCVD is able to cover pre-existing cracks in material, leading to higher quality wafers. A significant challenge facing this approach is to reduce the impurities generated from the degradation of the graphite containers in which the material is produced, making it difficult to grow long boules.

Several companies have developed successful processes to grow electronic-grade bulk 4H- and 6H-SiC crystals, and wafers with diameters up to 6 inches are commercially available, but quite expensive at this time compared to similar Si wafers.

High volume sensor applications are very cost sensitive, requiring substantial price decreases from current levels for single-crystal SiC substrate to be viable in such opportunities.

Cubic SiC is attractive over other polytypes due to higher carrier mobility. Large area 3C-SiC wafers are not available, and 3C-SiC epitaxy is mostly developed from a

9 heteroepitaxial process employing Si wafers. Large mismatch in lattice parameter and thermal expansion coefficient between the SiC layer and Si substrate causes formations of lattice defects and residual stress. Although a variety of electronic devices have been fabricated from 3C-SiC on Si films, the performance of these devices is inferior to similar 6H-SiC devices, due mainly to the high defect densities in the 3C-SiC films.

Polycrystalline SiC deposition

Unlike single-crystal SiC, polycrystalline SiC (poly-SiC) can be deposited on a

wide variety of substrate materials such as SiO2 and Si3N4. This feature microsystem expands sensor design possibilities in combination with micromachining processes developed for Si. Poly-SiC can be deposited by Atmospheric Pressure Chemical

Vapor Deposition (APCVD) on Si substrates, polysilicon, SiO2 or Si3N4 substrate/film at temperatures above 1000ºC. It has been found that on amorphous layers such as

SiO2 or Si3N4 , the APCVD SiC films deposited from SiH4 and C3H8 are randomly oriented; while for oriented substrates such as polysilicon, the film is highly textured matching the substrate’s orientation [11].

Poly-SiC can also be deposited by Plasma Enhanced Chemical Vapor Deposition

(PECVD), sputtering and electron beam evaporation at substrate temperatures ranging from 200 to 1000°C [12-15]. The films can be either amorphous or polycrystalline with a temperature dependent distribution of grain orientation.

To date, another growth technology, Low-Pressure Chemical Vapor Deposition

(LPCVD), has been developed by several research groups [16-19]. A number of precursor combinations have been applied in the growth process, such as single source tetramethylsilane (TMS), 1, 3 disilabutane (DSB), dual sources such as

acetylene (C2H2) combined with dichlorosilane (SiH2Cl2 or DCS) or DCS combined with DSB [20]. The deposition temperatures are reported to be from 650°C to 1150°C.

In 2000, our group developed a LPCVD furnace system which deposited poly-SiC

using dichlorosilane (SiH2Cl2) and acetylene (C2H2) at 800-900°C. The stoichometric films proved to be highly textured (111) oriented polycrystalline 3C-SiC. Further, the residual stress of the films (in the range of tensile 700 MPa to compressive 100

MPa) could be optimized by adjusting the deposition pressure between 0.46 and 5.00

Torr.

1.3.2 SiC surface micromachining

Several IC compatible processing methods can be adopted for SiC sensor fabrication, including surface micromachining. In surface micromachining, the device structural layer is deposited on sacrificial layers on the surface of Si wafers or other substrates. These sacrificial layers are selectively etched by either a wet etch involving an acid or a dry etch involving an ionized gas or a plasma. Dry etching can combine chemical etching with physical etching, or ion bombardment of the material.

Surface micromachining can involve as many layers as needed with a different mask

(producing a different pattern) on each layer. A typical SiC surface micromachining 11 starts with a substrate prepared by first growing a thermal oxide on a silicon wafer.

Poly-SiC is then deposited on the surface of the SiO2. Conventional SiC reactive ion etching (RIE) is used in conjunction with photolithography to pattern the poly-SiC film into the desired structural shape. The device structure is released by etching

select regions of the SiO2 layer in buffered oxide etch (BOE), without damaging the

poly-SiC. Polysilicon and SiO2 are usually used for the sacrificial layers, since their etchants do not generally etch SiC. Recently, a new SiC sacrificial layer, SiGe, was announced by Behnel, et al. [21]. The extremely high etch selectivity of up to

1:1000000 between SiC and SiGe was achieved when using chlorine trifluoride (ClF3) as the etchant in a dry plasmaless etch process.

1.3.3 SiC reactive ion etching

Wet etching of SiC is difficult to achieve because it requires molten salts to be used at high temperatures due to the chemical stability of SiC. Furthermore, plasma-based dry etching possesses the advantage of relative anisotropy of plasma etching in precisely controlling feature line width. For these reasons, RIE of SiC in fluorinated plasmas is widely employed in both research and product fabrication [22].

A variety of fluorinated gases (CHF3, CBrF3, CF4, SF6, and NF3), usually in combination with oxygen, have been employed in 3C-, 4H- and 6H-SiC RIE.

Sub-millimeter features can be successfully patterned with an etch rate of 100 to 1000

Å /min and a high degree of etching anisotropy. However, residue can hinder subsequent processes. Utilizing the right material for the etch mask and avoiding 12 metal contamination from the etching chamber can prevent the formation of residues in the etch field. Etching of SiC in electron cyclotron resonance (ECR) [23, 24] and inductively coupled plasma (ICP) [25, 26] reactors has been reported by several groups, with fairly good etch rates and good anisotropy, as well as residue-free

(smooth) surface topography. The absence of residue in these processes indicates that there is negligible re-sputtering from the etch mask and electrode materials.

Recently, a new deep RIE process for SiC was developed at NASA Glenn that produces smooth, vertical sidewalls, while maintaining an adequately high etch rate

(2000 Å /min). By utilizing a time-multiplexed etch-passivate (TMEP), it alternates fluorine-plasma etching of the material with the deposition of a passivating polymer

layer to produce an anisotropic profile. Here, SF6 is used as the etching gas, and

octafluorocyclobutane (C4F8) is used to deposit a fluorocarbon polymer film that protects the sidewalls from lateral etching. The final etching quality, such as roughness and slope of the sides of etched feature, is thus controlled [27].

1.3.4 MEMS packaging

Most of the early packaging technologies of MEMS used ―off-the-shelf‖ packaging adopted from the semiconductor microelectronics field. Important criteria in evaluating the success of packaging are cost, performance and reliability. The ideal package is supposed to integrate all of the components required for a system application in a manner that minimizes size, cost, mass and complexity. Three main functions of the MEMS package should be satisfied, namely mechanical support, 13 protection from the environment and electrical connection to other system components.

Mechanical support

Similar to conventional semiconductor microelectronic packaging, sensor packaging should first afford strong protection from mechanical damage, such as mechanical shock and high acceleration during operation or storage. Once the electrical connections like wire bonds are made, the chip has to be encapsulated in a housing material to prevent scratches or other physical damage. The attachment between the chip and carrier needs to be uniform and reliable, resulting in reduced stress on the product and protection from damage.

Protection from environment

Since most sensors must interact with the surrounding environment, the packaging has to afford protection against chemical reactions, such as corrosion. The metal traces on the device are easily corroded by the presence of moisture in the environment. Although there is no moisture in some operating environments, the release of moisture trapped in the packaging material during fabrication can cause serious problems. The right selection of materials and packaging process is necessary to avoid this moisture absorption problem.

Electrical connection to other system components

Because the device has to be connected to the power system or signal modulating components, the electrical connection is an important function that packaging should

14 address. In some cases, the connections between chips of different functionality are also realized by using parts of the packaging. The final connections between the sensor and the system may be accomplished using wire bonds, flip-chip die attachments and multilayer interconnections using thin dielectrics. The connections through the package usually utilize metal lines passing through the package walls or metal leads penetrating apertures, insulated by sealing material.

High temperature applications considerations

Current commercialized packages are developed for Si-based devices, offering heat capability to a maximum temperature of about 175ºC, and a power density limited to around 200 W/cm2. This thermal capability is insufficient and severely constrains the level of power density and temperature at which a SiC device can operate. Packaging development leading to enhanced thermal management is essential in achieving the great potential offered by SiC devices.

First, the packaging material should be stable in a high temperature environment, with no swelling, peeling, melting, oxidation and destruction. Second, the stress induced by different thermal expansion of materials should be avoided as much as possible. It will cause the mechanical attachment to become compliant; the accumulated energy will then be transferred, eventually affecting the fragile parts. The deformation of these parts will negatively impact the performance of the device.

In recent years, research has led to the development of high-temperature packaging technology for SiC devices, capable of sustaining operation at temperatures

15 as high as 500ºC and/or a heat flux density of up to 1000 W/cm2. This high-temperature packaging utilizes an integration of a hybrid package module design, consisting of an AlN substrate and carbon foam heat sink [28].

NASA has also developed packaging for SiC-based electronics that can withstand

500ºC operating temperature. This packaging is similar to flip-chip packaging of silicon-based integrated circuits (ICs). The SiC-based circuit chips are mounted on an

AlN package substrate. The connections are made by direct bonding rather than by wire bonds to improve the reliability. Thick gold film circuit traces are utilized for conduction because the adhesion and sheet resistance is stable at 500ºC for long term.

Glass layers with high breakdown potential are used for passivation and sealing in this package [29].

In both packages, AlN was selected for the substrate material. The properties that make AlN ceramics an excellent candidate for high-temperature packaging are CTE

(coefficient of thermal expansion) closely matching that of SiC, high thermal conductivity, chemical inertness, high electrical resistivity and high mechanical strength.

Table 1.2 Properties of some ceramic substrates [30].

Properties AlN Al2O3 BeO Thermal Conductivity (W/mK) 200 20 250-300 Dielectric Strength (kV/cm) 140-170 100 100 Dielectric Constant (@ 1MHz) 8.8 8.5 6.5 Tan δ (×10-4 @1MHz) 5-10 3 5 CTE (×10-6 /ºC) (25-400ºC) 4.5 7.3 8 Density (g/cm3) 3.3 3.9 2.9 Flexure Strengh (MPa) 300-500 240-260 170-230

Another important factor that can limit sensor performance for high temperature applications is metallization. The traditional IC materials for contact metallization and interconnections are easily oxidized at 500ºC in air. Metallization with high temperature stability and good conductivity is necessary to make the device viable for high temperature applications. In Chapter 6, we will describe our investigation of multilayer metallization, especially in the formation of Ohmic contacts to the SiC conductor.

Chapter 2

HIGH-TEMPERATURE SIC PRESSURE SENSOR DEVELOPMENT

2.1 Literature review

2.1.1 State-of-the-art, high-temperature pressure sensors

Requirements for improving fuel efficiency and reducing emissions create numerous opportunities for pressure sensors. Silicon-based pressure sensors are the most extensively documented of such devices. As a mature technology, all facets including material properties, design, fabrications and testing are extremely well developed. Piezoresistors or capacitive electronic elements are used to measure changes in the deflection of the diaphragm under pressure loading. These sensors are interfaced with silicon integrated circuitry to output a voltage that corresponds to a particular pressure. Temperature compensation circuit techniques are usually applied to correct any drift in the output signal due to temperature effects.

At a temperatures less than 500ºC, silicon shows perfect elastic behavior and will only fracture in a brittle manner. It obeys Hooke’s law up to 1% strain and shows great advantage over traditional metal alloys in terms of hysteresis and creep behavior at elevated temperature. However, silicon micromachined structures suffer from mechanical performance degradation above 500ºC and are inadequate for building reliable high-temperature sensors [31] . 18

Furthermore, sensor electronic elements, together with the interface circuitry, suffer from rising leakage current at temperatures above 125ºC in conventional devices where device isolation occurs through reverse biased pn-junctions. This is due to the small band gap (1.1eV) of silicon; with temperature increase, the intrinsic carrier concentration increases exponentially, overwhelming the effect caused by intentional dopants. Generally, Si sensor and electronics are mainly suitable at working temperatures below 200ºC.

SOI sensors

Silicon-on-insulator (SOI)-based electronic and sensor devices have an extra embedded silicon dioxide layer in the substrate for improved leakage isolation.

Several pressure sensors based on SOI substrates have been demonstrated [32-34]. A piezoresistive pressure sensor based on silicon-on-sapphire (SOS) substrate was developed with excellent linearity, low temperature dependence and very good long-term stability at temperatures up to 350ºC. Another promising attempt for high temperature applications is the use of separation by implantation of oxygen

(SIMOX). Kasten, et al. [35] demonstrated a CMOS-compatible process to make a piezoresistive pressure sensor operating up to 340ºC. Zhao, et al. [36] developed a

SIMOX and LPCVD method to make a piezoresistive pressure gauge, possessing good linearity and sensitivity at temperatures up to 200ºC.

A silicon piezoresistive pressure sensor with the highest temperature excursion was developed by Guo, et al. [37] based on Smart-Cut SOI; it sustained 600ºC

19 operating temperature. A temperature compensation circuit is necessary to help eliminate the influence of temperature on pressure characteristics. Since the maximum operating temperature of a bulk silicon resistor is normally below 330ºC

(due to thermal generation of excessive charge carriers at high temperature), a very thin silicon film (~0.34 µm) on insulator was employed to eliminate this problem, utilizing the minority-carrier exclusion effect in a thin film.

Due to the high temperature shortcomings of Si-based devices at temperatures above 250ºC, there is a focus on developing sensors using new semiconductor platforms, mainly wide band gap semiconductors.

TaN pressure sensors

Ayerdi, et al. [38] reported a micro pressure sensor for high temperature operation based on a tantalum nitride thin film. The TaN Wheatstone bridge configuration was deposited and patterned onto thermally-oxidized silicon wafers with an aluminum interconnection layer and a silicon dioxide passivation layer. This microsensor showed a low temperature coefficient of resistance and good long-term stability. The sensitivity was 0.15 mV/(V bar) for 0 to 10 bar pressure range, operating from 25 to 300°C.

GaAs pressure sensors

GaAs is also an attractive material for high temperature applications. Thanks to its 1.4 eV band gap, it can operate at ambient temperatures up to 350°C. A group in

Germany [39] demonstrated a piezoresistive GaAs pressure sensor with a

20 compensation IC operating up to 300°C. They deposited GaAs/AlGaAs on a GaAs wafer with metal-organic CVD technique, and patterned the GaAs piezoresistors and

GaAs/AlGaAs diaphragm by selective etching.

The AlxGa1−xAs/GaAs heterostructure system has attracted more attention since a number of interesting properties and phenomena, such as high-mobility two- dimensional carrier gases, resonant tunneling and fractional quantum Hall effect, have been found. A GaAs Pressure Sensor with frequency output based on resonant tunneling diodes (RTD) was developed by Mutamba, et al. [40]. Hydrostatic pressure induces a variation of carrier effective mass which shifts the energy states in the quantum well. The variation in the position of the energy states due to pressure modifies the current-voltage characteristics of the RTD, leading to a shift of the peak and the valley voltages. The sensor output presents a sensitivity of up to 80 kHz/kbar at 113 kHz with stable oscillations. However, the effect of temperature on oscillation frequency and sensor sensitivity must be studied further.

GaN pressure sensors

Wide-band gap, large band offsets and strong lattice polarization effects in

GaN-based materials and heterostructures make them very attractive for applications in high temperature piezoelectronics and pyroelectronics. Gaska, et al. [41] reported a strong piezoresistive effect in metal–semiconductor–metal structures fabricated on p-type GaN. The maximum measured gauge factor was 260, which is nearly two times larger than for piezoresistive silicon transducers.

A pressure sensor based on AlGaN/GaN heterostructures with confined

2-dimensional electron gas (2DEG) was developed by Kang [42]. Pressure induced tensile diaphragm strain will lead to a change in the piezo-induced 2DEG density at the AlGaN/GaN interface. This in turn affects the capacitance of the high-electron-mobility transistor diaphragm. This sensor shows a sensitivity of 0.86 pF/bar and a hysteresis of 0.4% in the linear range.

Diamond pressure sensors

The unique combination of the material properties of diamond (such as wide band gap (5.4 eV), piezoresistivity, low thermal coefficient of expansion (1 ppm/ºC ), high thermal conductivity and mechanical hardness) are ideal for high temperature pressure sensors.

Darrel, et al. [43] reported the development of a monolithic all-diamond pressure sensor by fabricating CVD grown boron-doped polycrystalline diamond film resistors on a dielectric diamond diaphragm. The sensor showed a piezoresistance of 0.1% /

(100 mmHg) for 250 mmHg pressure range at room temperature.

A research group at Vanderbilt University announced that they had fabricated an all-diamond pressure sensor prototype utilizing a doped diamond piezoresistor on an undoped diamond flexing diaphragm, which is patterned by liftoff or subtractive techniques. The diamond pressure sensor operated at temperatures higher than 600ºC, with signal output 2 to 10 times that of silicon [44, 45].

SiC pressure sensors

SiC is an attractive material for high-temperature applications because of its mechanical robustness, chemical inertness and electrical stability at elevated temperatures. Earlier SiC pressure sensor development efforts were focused on the piezoresistive sensing scheme. Ned and Okojie [46] demonstrated a 6H-SiC piezoresistive pressure sensor operating at 600ºC. The typical room temperature full-scale output for maximum pressure of 6.9 MPa (l000 psi) was 66.41 mV, with a hysteresis and non-linearity of less than 1% full scale output across the range of operating temperature.

Piezoresistive sensors, however, exhibit strong temperature dependence and suffer from contact resistance variations at elevated temperatures. In contrast, capacitive pressure sensors tend to provide higher sensitivity, lower temperature coefficients, more robust structures and lower power consumption compared to piezoresistive devices.

In 2004, Young, et al. [31] developed a 3C-SiC touch-mode capacitive pressure sensor based on wafer bonding technology. A 0.5 µm-thick 3C-SiC film was grown epitaxially on a (100) silicon wafer by APCVD. This layer was transferred onto a patterned low temperature oxide (LTO) layer on another silicon wafer using wafer bonding. The fabricated sensor showed high-temperature sensing capability up to

400ºC, with a nonlinearity of 2%.

Fiber optic pressure sensors

Fiber optic pressure sensors offer advantages in harsh environments since sensitive readout electronics can be placed far away from the high temperature environment. These pressure sensors typically employ a configuration consisting of a pressure-sensitive diaphragm positioned in front of an optical fiber end surface. In between the diaphragm and the fiber surface, there is a reference pressure cavity.

Thus, the fiber, the diaphragm and the cavity form a Fabry–Perot interferometer, and the diaphragm displacement can be read by very sensitive interferometry.

Recently, Ceyssens [47] demonstrated an optical absolute pressure sensor fabricated directly on a fiber with a process based on thin film techniques and FIB (focused ion beam) machining. Its performance in high temperature is improved by applying monolithic construction to minimize thermal mismatch and using a vacuum reference pressure cavity. It can operate with a relative sensitivity of 5 to 7.5%/ bar above

600ºC. However, the measured curves displayed serious temperature dependence.

Ceramic cofireable tape pressure sensor

A well-developed ceramic packaging procedure using ceramic cofireable tape is also employed for realizing high temperature pressure sensors. A pressure sensor for high-temperature applications based on Low Temperature Cofireable Ceramic (LTCC) integrated with a passive wireless resonant telemetry scheme is realized by Fonseca, et al. [48]. The sensors are fabricated using multiple sheets of Dupont 951AT ceramic tape. The tape consists of alumina and glass particles suspended in an organic binder.

The inductor coils and capacitor electrodes of the pressure sensor were fabricated

24 using screen-printing. The sensor operated up to 400ºC with pressure ranging from 0 to 7 bar. The average sensitivity and accuracy of typical sensors were 141 kHz/ bar and 24 mbar, respectively.

2.2 Pressure sensing mechanisms

In addition to attempting to find more suitable materials for high temperature pressure sensing, researchers have also invested much effort into investigating efficient sensing mechanisms. There are several common sensing mechanisms currently in wide use, including capacitive, resistive, resonant, optical, etc.

Piezoresistive pressure sensors

A piezoresistive pressure sensor uses the piezoresistive effect of a bonded or formed strain gauge on a flexible diaphragm to detect strain due to applied pressures.

The piezoresistive effect describes the changing resistivity of a semiconductor due to applied mechanical stress. The piezoresistive effect of semiconductor materials can be several orders of magnitudes larger than the geometrical effect in metals and is present in materials like germanium, Si, polysilicon, amorphous silicon, silicon carbide, etc. Generally, IC processing is used to form the piezoresistors on a diaphragm. For thin diaphragms and small deflections, the resistance change is linear with applied pressure. The piezoresistive pressure sensor evolution started with metal diaphragm sensors with bonded Si strain gauges. However, they were quickly superseded by single-crystal Si diaphragms with diffused piezoresistors. The advantage of single-crystal Si diaphragm over traditional metal diaphragm can be 25 summarized as follows. Firstly, hysteresis and creep associated with metal diaphragms can be eliminated. Secondly, at low temperatures (<500ºC ), Si is perfectly elastic and will not deform plastically. Thirdly, the ultimate tensile strength of Si is three times higher than that of stainless steel wire. Finally, Si obeys Hooke’s law up to 1% strain, a tenfold increase over common metal alloys.

Si piezoresistive pressure sensors have the advantage of high sensitivity, high linearity and an easy-to-retrieve output signal through a bridge circuit. However, they also have some drawbacks. Any mechanical stress or thermal mismatch between the chip and substrate may cause a large offset voltage. The temperature sensitive resistance drift needs to be eliminated by a temperature compensation circuit.

Furthermore, piezoresistance is susceptible to junction leakage and surface contamination, which threatens long term stability.

Capacitive pressure sensors

Capacitive pressure sensors typically measure the capacitance change of a capacitor affected by external pressure. A thin diaphragm which deflects under pressure behaves as one electrode of the capacitor. A cavity with reference pressure is sealed on one side of this diaphragm, while ambient pressure affects the other side.

The diaphragm deflection causes the distance change of the two electrodes, leading to the final capacitance change. This change may present an approximate linearity in a specific range, and the value is on the order of attofarads (10-18 farad) or femtofarads (10-15 farad). Thus, amplifier electronics and converter electronics are

26 necessary to transform this small capacitance signal to a readable voltage, current or frequency output. To avoid the stray capacitance, the circuit is to be mounted as close as possible to the sensing chips. Capacitive absolute pressure sensors with a vacuum between the two electrodes are ideal, since the dielectric constant is stable in this way. It is preferable to build sensors with monolithic materials or materials with close coefficients of thermal expansion in order to minimize error caused by thermal mismatch.

Piezoelectric pressure sensors

Piezoelectric pressure sensors use the piezoelectric effect to measure pressure by converting it to an electric potential. Two main groups of materials are used for piezoelectric sensors, namely piezoelectric ceramics and single-crystal materials.

When pressure is applied to a piezoelectric material, it causes a mechanical deformation and a displacement of charges. The charge disturbances are highly proportional to the applied pressure. Since the piezoelectric effect is dynamic effect, an output is generated only when the input is changing. This means that these sensors can be used only for dynamic pressures such as rapid combustion chamber pressure monitoring.

Resonant pressure sensors

Resonant pressure sensors operate by monitoring the resonant frequency of a embedded doubly clamped bridge or comb drive. The resonant structure, which has also been called a resonating force transducer, acts as a sensitive strain gauge. As the

27 stress state of the diaphragm changes, the tension in the embedded structure changes and so does the resonant frequency. This kind of pressure sensor has the advantage of high stability and high resolution. However, it requires a driving power to apply alternating force, and a good vacuum is necessary for high Q factor.

Fiber optic pressure sensors

Many diaphragm-based optical sensors have been reported which measure pressure induced deflections by Fabry–Perot interferometry. These sensors utilize one or multiple optical fibers positioned in front of a flexing diaphragm. The optical gap between the diaphragm and the fiber is a Fabry-Perot cavity. Light interference resulting from the internal reflection of light at the fiber end face and reflected light off the bottom surface of the diaphragm is used to monitor the optical path length.

The optical gap varies with diaphragm deflection, which in turn varies with applied pressure. The fiber-optic pressure sensor demonstrates excellent qualities, including wide temperature range, high resolution and low combined uncertainties after temperature compensation. However, it often suffers from temperature sensitivity problems; aligning the optics and calibrating the sensors can be challenging and expensive as well.

2.3 Prior related work in our group

A prototype of a high-temperature, poly-SiC, capacitive pressure sensor was demonstrated by Chen [6]. The all-SiC sensor takes advantage of the excellent

28 harsh-environment material properties of SiC and is fabricated by surface micromachining.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

Si3N4 LTO SiC Metal Figure 2.1 Sensor fabrication process [6]: (a) SiC lower electrode patterned on LSN coated Si substrate; (b) LSN electrical isolation and contact window patterning; (c) LTO sacrificial layer deposition and anchor region definition; (d) SiC diaphragm deposition and patterning; (e) wafer-scale release in BOE; (f) diaphragm cavity sealing by LTO and seal ring formation; and (g) metallization.

Figure 2.4 briefly describes the sensor fabrication process [6]. First, an electrically insulating, 200 nm-thick, low-stress silicon nitride (LSN) layer is deposited, followed by the deposition of a 200 nm-thick, heavily-doped low pressure

LPCVD poly-SiC film, which is patterned by RIE to form the base electrode and electrical interconnections. Another 300-nm-thick LSN film is deposited and patterned to open the contact window. A 1.5 μm-thick LTO film is then deposited

29 and patterned for use as a sacrificial layer, later creating the sensing capacitance gap when it is dissolved. Next, a 2.7 μm-thick, heavily-doped, poly-SiC film is deposited and patterned by RIE to form the sensing diaphragm. Following a timed release in

BOE, another 2.5 μm-thick LTO film is deposited and patterned to form a ring for sealing the cavity. Finally, a Cr (50 nm)/Ni (300 nm)/Au (400 nm) multilayer is deposited for high-temperature contact metallization.

With a high-temperature ceramic package, static pressures of up to 4.8 MPa (700 psi) and temperatures up to 574ºC were measured in a custom chamber. At 574ºC, the achieved sensitivity and nonlinearity are 1.0E-3 fF/Pa (7.2 fF/psi) and 2.4%, respectively; the temperature coefficient of capacitance change is 0.05%. Two types of die layouts have been designed for two different strategies of data retrieval. Type A

(Fig. 2.2) dies have a Wheatstone-bridge structure, which includes two single sensing elements (variable capacitor) and two reference elements (fixed capacitor). The differential signal is picked up and amplified by an instrumentation amplifier IC.

Type B (Fig. 2.3) dies have an array of sensor elements to increase capacitance change, allowing capacitance readout directly by a LCZ meter. A plan-view micrograph of a Type B die is presented in Fig. 2.4.

Figure 2.2 Type A die layout (Wheatstone bridge structure).

Figure 2.3 Type B die layout (Array structure).

Figure 2.4 Plan view micrograph of Type B die.

2.4 Challenges and limitations

Sensitivity of pressure sensors

In Type A design, there are only a few of sensors in each bridge, which limit the sensor sensitivity. In Type B design, there is only a single array, without the

Wheatstone bridge implementation. This work implements a differential scheme, which combines the positive attributes from both of the above designs. Thus, tens of sensors in each bridge are arrayed. In addition, the sensing capacitance gap is reduced from 1.5 μm to 0.5 μm in order to enhance sensitivity and performance.

Metallization and packaging for high temperature

Metallization and wire bonding are necessary for electronic connection to and between the sensors and interface IC. Considering that the metallization and wire bonding have to work well at high temperature, many conventional metals are 32 deficient. High temperature Ohmic contact is especially necessary; the resistance of the contact must be negligible with respect to that of the device and must remain stable. High temperature packaging also requires die attach techniques that can reliably withstand high operating temperature, i.e., not only not fail but also not introduce stress relaxation.

The use of Cr (50 nm)/Ni (300 nm)/Au (400 nm) multilayer as the metallization for the prior generation pressure sensors in our group suffered from high residual stress, causing the metal to eventually delaminate (Fig. 2.5).

Figure 2.5 Delamination of metal pads and interconnections of the sensor array.

Pressure readout and temperature compensation schemes

For a practical sensor, a capacitance-to-voltage convertor IC must be included to transform capacitance to voltage, along with temperature compensation circuitry

33 to eliminate the temperature dependent effect. However, parasitic capacitance from the wire connections between the sensor and IC must be minimized by short connections, i.e., co-packaging. Since the typical commercialized Si-based IC will not survive at high temperature, SiC-based electronics have been developed in our group to function as a high temperature amplifier.

In the current work, the sensor array is designed so that the output signal may be measured with an LCZ meter. However, the development of the current differential array design makes it feasible to interface the sensor with the electronics under development in our group.

Chapter 3

DESIGN OF SIC CAPACITIVE PRESSURE SENSOR

3.1 Introduction

This chapter presents analytical design techniques for the pressure sensor. The sensor embodiment and target specifications in Table 3.1 are expanded here by building on the prior work by Chen [49]. The sensors cover a wider pressure range, from 0.10 MPa to 34.5 MPa (15 psi to 5,000 psi). An increase in sensitivity is also incorporated in the sensors designed for up to 750 psi.

Table 3.1 Target sensor specifications for high temperature applications. Combustion Cylinder Turbine This Thesis Engine Engine Engine Working 0~10 MPa 0-8.6 MPa 0~10MPa 0~0.1, 2.0,3.4…34 MPa range (0~1500psi) 0~1245psi (0~1500psi) 0~15,300,500…5000 psi Burst 2× 1.5× 2.5× 2× Pressure Sensitivity 3E-4mV/Pa 1E-3mV/Pa 1E-3mV/Pa 1.5E-3mV/Pa (for (2mV/psi) (7mV/psi) (6.8mV/psi) 10MPa) (10mV/psi for 1500 psi) Bandwidth 5Hz ~20KHz 0~20KHz ~20KHz Temperature 400ºC -55~200ºC -50~650ºC -60~550ºC

The total capacitance of the sensor is composed of an active part from the cavity gap under the diaphragm and a non-active part from the LSN insulating layers on the surface of the base electrode. For the chosen sensor embodiment, capacitance change (due to a change in pressure) is determined by the diaphragm deflection. 35

Diaphragm deflection is a function of material constants and dimensional parameters, including lateral dimensions, thickness and sensing capacitance gap size. The dimensional parameters are affected by fabrication process capabilities and limitations.

Circular diaphragm designs operating in small-deflection (non-contact) or large-deflection (contact) mode have been designed. Timoshinko’s plate theory [50] was applied to the analysis of micromachined thin-film diaphragms. Small deflection theory is applied when the deflection is less than 20% of the diaphragm thickness.

Large deflection theory is used for deflections of up to three times the diaphragm thickness. Residual stress in the diaphragm film is also considered in the model, leveraging our knowledge of heavily-doped poly-SiC thin film properties measured in our lab.

The initial design space is defined as follows: For a given gap size, the sensor pressure range is defined by the diaphragm radius. The larger the diaphragm radius, the smaller the pressure range of the sensor. But a large radius also results in a large capacitance. A large base capacitance is necessary to be able to interface with the appropriate sense electronics. Gap dimension is another design parameter. High sensitivity (capacitance change per unit deflection) requires a small gap (or large diaphragm radius). If the deflection is a very large percentage of the gap (> 50%), the capacitance versus pressure response becomes nonlinear (> 6%) which may be unacceptable. In addition for sensors operating in the small-deflection mode, the

36 maximum center deflection should be less than 20% of the diaphragm thickness

This initial design space is limited by the process/material constraints. Thus the gap dimension was targeted to be not less than 200 nm to ensure reliable etching of the sacrificial oxide for the sensing capacitance gap. With respect to diaphragm thickness, sensors with larger film thickness can withstand higher pressures.

However, thicker films take a longer time to deposit, which directly affect manufacturing costs. Thus a target film thickness of 3μm (or lower) was selected for all the designs.

3.2 Pressure sensor design

The design parameters and material constants for modeling the sensors are listed in Table 3.2.

Table 3.2 Parameters and materials constants used in modeling the sensors. Exp. Term Value Ref. E Yong’s modulus 401 GPa [51] ν Poisson’s ratio 0.168 [51]

ζmax Burst stress 1321 MPa [52] t LSN layer thickness 0.35 μm N/A

εi LSN layer relative 7.5 [5] permittivity

ε0 Electric constant 8.854 pF/m N/A

3.2.1 Small-deflection mode, circular diaphragm

The small-deflection model assumes that the middle plane of the plate coincident with the neutral axis does not change in length. For a uniformly loaded

37 circular plate with a clamped edge, the deflection under pressure P, can be expressed as [53]

(3.1)

where ω is the diaphragm deflection, r is the radial coordinate, R is the diaphragm radius and D is the flexural rigidity. D, essentially a measurement of stiffness, is given by

(3.2) ν where E, h, and ν are Young’s modulus, diaphragm thickness and Poisson’s ratio, respectively. The maximum deflection, ω(0) (at the center of the diaphragm), is given by

(3.3)

The mode shape of the deflection can be written as,

(3.4)

Taking into consideration the effect of film stress, Eq. (3.4) is modified to be [54]:

(3.5) ζ where ζi is the initial built-in stress. When both bending and initial stress are considered, the diaphragm center deflection is modified to be

ζ (3.6) ζ

ζ (3.7)

A safety factor of 2× maximum operating pressure was incorporated in the diaphragm designs. For the circular diaphragm with a clamped edge, the maximum

38 stress ζmax occurs at the edge of the diaphragm and is given by

ζ (3.8)

where Pmax is the maximum (i.e., burst) pressure and ζmax is the burst strength 1,321

MPa for SiC [52]. For a given pressure range, we can calculate the minimum diaphragm thickness as

(3.9) ζ

Mathematica was used for capacitance calculations. For convenience, only the active part of the sense capacitance was considered, since the rigid part only contributes a fixed value which does not change with pressure loading. The total

active capacitance is the series combination of the gap capacitance, Cgap and the low

stress nitride (LSN) insulation layer capacitance, Cins. Cgap can be calculated by splitting the circular area into a group of infinitesimal rings and integrating them along the diaphragm’s radius as follows:

(3.10)

ε ε (3.11) ω

ε ε (3.12)

ε ε ε (3.13) ε ε ω

Figure 3.1 to 3.9 plot the capacitance versus pressure for increasing diaphragm radii (and decreasing pressure range) in the small-deflection mode. The plots predict device performance parameters including sensitivity, nonlinearity. Note that the gap

39 and SiC thickness are kept constant at 0.5 μm and 3 μm respectively. Keeping the above parameters constant enables us to fabricate devices with different pressure ranges at the same time by implementing them on the same mask set.

r-17μm 34 MPa 9.75 9.70 9.65 9.60 9.55 9.50

9.45 Capacitance (pF) Capacitance 9.40 0 10 20 30 40 Pressure (MPa)

Figure 3.1 Simulation plot of capacitance versus pressure for r=17 μm.

r-20μm 17MPa 13.45 13.40 13.35 13.30 13.25 13.20 13.15 13.10

13.05 Capacitance (pF) Capacitance 13.00 0 5 10 15 20 Pressure (MPa)

Figure 3.2 Simulation plot of capacitance versus pressure for r=20 μm.

r-28μm 10MPa 26.2 26.0 25.8 25.6 25.4 25.2 25.0 24.8 24.6

Capacitance (pF) Capacitance 24.4 24.2 0 2 4 6 8 10 12 Pressure (MPa)

Figure 3.3 Simulation plot of capacitance versus pressure for r=28 μm.

r-41μm 5MPa 39 38 37 36 35 34

33 Capacitance (pF) Capacitance 32 0 1 2 3 4 5 6 Pressure (MPa)

Figure 3.4 Simulation plot of capacitance versus pressure for r=41 μm.

r-45μm 3.4MPa 45 44 43 42 41 40 39

38 Capacitance (pF) Capacitance 37 0 1 2 3 4 Pressure (MPa)

Figure 3.5 Simulation plot of capacitance versus pressure for r=45 μm.

r-54μm 1.7MPa 47 46 45 44 43 42 41 40

39 Capacitance (pF) Capacitance 38 0 0.5 1 1.5 2 Pressure (MPa)

Figure 3.6 Simulation plot of capacitance versus pressure for r=54 μm.

r-68μm 0.7MPa 50 49 48 47 46 45 44 43 42 Capacitance (pF) Capacitance 41 0 0.2 0.4 0.6 0.8 Pressure (MPa)

Figure 3.7 Simulation plot of capacitance versus pressure for r=68 μm.

r-80μm 0.34MPa 54 53 52 51 50 49 48 47

46 Capacitance (pF) Capacitance 45 0 0.1 0.2 0.3 0.4 Pressure (MPa)

Figure 3.8 Simulation plot of capacitance versus pressure for r=80 μm.

r-95μm 0.17MPa 58 57 56 55 54 53 52 51

50 Capacitance (pF) Capacitance 49 0 0.05 0.1 0.15 0.2 pressure (MPa)

Figure 3.9 Simulation plot of capacitance versus pressure for r=95 μm.

Sensitivity is determined from the slope of the capacitance versus pressure plots.

Nonlinearity is calculated from [49]

(3.14)

where ΔC+ and ΔC- are the maximum and minimum deviation from a linear fit of

the capacitance versus pressure plot. Cmax and Cmin are the maximum and minimum capacitance over the operational range.

Table 3.3 Performance comparison between pressure sensor arrays for different

range and process parameters (small-deflection mode).

Sensor Dimension R(μm) 17 20 28 34 37 41 45 54 68 80 95

H: 4μm pressure range(MPa) 34 17 10 5.2 3.4 1.7 6.9E-01 3.4E-01 1.7E-01 g: 0.5μm sensitivity (fF/Pa) 9.4E-06 7.0E-05 1.9E-04 4.4E-04 7.3E-04 1.6E-03 4.1E-03 8.4E-03 1.8E-02 NL 1% nonlinearity 0.36 0.70 0.94 1.00 0.95 0.98 0.97 0.90 0.87 H:3μm pressure range(MPa) 34 17 10 5.2 3.4 1.7 0.69 0.34 0.17 0.07 g: 0.5μm sensitivity (fF/Pa) 5.9E-06 1.4E-05 9.5E-05 2.8E-04 4.1E-04 1.2E-03 3.0E-03 9.6E-03 1.9E-02 4.2E-02 NL 1% nonlinearity 0.44 0.42 1.03 1.12 1.03 1.13 0.90 1.12 1.03 0.76 H:3μm pressure range(MPa) 34 17 10 5.2 3.4 1.7 6.9E-01 3.4E-01 1.7E-01 g: 0.5μm sensitivity (fF/Pa) 5.9E-06 1.4E-05 9.5E-05 8.6E-04 1.5E-03 3.6E-03 1.1E-02 2.2E-02 4.9E-02 NL 2-3% nonlinearity 0.44 0.42 1.03 2.81 2.66 2.73 2.64 2.38 2.22

H:1μm pressure range(MPa) 7.0E-02 3.4E-02 6.9E-03 g:0.5μm sensitivity (fF/Pa) 2.5E-02 5.5E-02 5.2E-01 NL 1% nonlinearity 0.91 0.83 0.94 pressure range(MPa) 10 5.2 3.4 1.7 1.5E-01 4.8E-02 H:3μm sensitivity (fF/Pa) 1.1E-04 3.2E-04 5.2E-04 1.2E-03 7.3E-02 4.6E-01 g:1.5μm NL 1% nonlinearity 2.01 1.99 2.08 1.78 3.11 3.78 sensor dimension(μm) 42 50 56 67 141 208

1NL is the nonlinearity. See the definition on page 54, Eq. (3.14).

Table 3.3 lists the calculated performance of the small-deflection mode pressure sensors and the corresponding process parameters. The designs are listed for two gap sizes. The appropriate diaphragm dimensions corresponding to a specific pressure range for a given gap size can thus be chosen. In addition, the table enables us to choose the most realizable sensors for given performance characteristics. Designs with SiC diaphragm thickness of 4 μm were not chosen since this would have required high deposition times (~10hrs), stressing the furnace hardware. The calculations are based on arrayed devices in order to meet the requirements of the interface electronics. The number of devices in each array is dependent on the pressure range.

3.2.2 Contact mode, circular diaphragm

Around the contact mode region, the capacitance versus pressure curve of the pressure sensor can be divided into three different zones: the region before the diaphragm touches the surface of the insulating layer (normal zone), a highly nonlinear C-P curve region around the touch point (transition zone) and when the diaphragm is in contact with the insulator layer (touch mode zone).

In the large deflection case, the middle plane of the diaphragm coincident with the neutral axis changes in length. The strain produced in the diaphragm can no longer be neglected and the strain energy method is used to analyze the diaphragm’s behavior, similar to the case of residual stress in the diaphragm. Thus, the rigidity of the diaphragm increases. The relationship between pressure and center deflection can be derived as [53]

(3.23)

Or (3.24)

The second term accounts for the additional strain caused due to large deflection. If an initial stress exists in the film, a third term is added. Equation (3.24) then becomes

ζ (3.25)

When the diaphragm and the insulator contact, the model can be separated into two distinct parts: (i) parallel flat plates with a fixed insulating layer gap, with the radius increasing with increasing pressure; and (ii) the remainder of the diaphragm not in contact with the bottom electrode and having a fixed outer radius but a varying

46 inner radius. After contact has occurred Eq. (3.25) needs to be adjusted. The radius R is replaced by the radial dimension c (remaining radius). If b is the radius of touch area, then

At the touch point, the maximum deflection (at diaphragm center) is equal to the sensing capacitance gap. The deflection equation then becomes

ζ (3.26)

The linear range of a contact mode capacitive sensor is typically in the range of 1.2 PT

to 2.5 PT [5], where PT is when the contact occurs. Based on the desired operating

pressure range, the proper PT is selected, and the radius R is calculated for a target PT.

To calculate the capacitance, the z-axis deflection profile of the diaphragm radius from touch point to the clamping edge is very important. Prior to contact, the deflection at any point r can be calculated from the following equation

(3.27)

After the contact, the shape of the untouched section can be assumed to follow as

(3.28)

The value of n is determined as follows [55]. For small deflection with respect to the thickness, pure-plate theory applies, and n is 2. In contrast, when the deflection is much larger than the diaphragm thickness, pure-membrane theory is used, and n is 1. In the case of deflection between these two extremes, n is between 1 and 2. In all of our contact mode models, the deflection is less than the diaphragm

47 thickness, and n is taken to be 2.

In contact mode, the total capacitor consists of two parallel capacitors, a contact part and a non-contact part. The non-contact part is formed by the sensing capacitance

gap (Cgap) connected in series with capacitor (Cins) formed by the insulator. The

contact part consists of just an insulator capacitor C0. This is illustrated in Fig. 3.10.

CCairgap GAirap gap capacitor capacitor

0 C0 CCinsins InsulatingInsulating layer layer capacitance capacitance

Figure 3.10 Schematic drawing of an equivalent capacitor model in contact mode.

Thus, the total capacitance is expressed as the sum of contact area capacitance and non-contact area capacitance:

(3.29)

ε ε ε (3.30) ε ε ω

where the integral is from the contact edge radius b to the outer radius a, and g-ω(r) gives the gap value at a specific radius position r. Figures 3.11 to 3.15 plot the

(contact, non-contact and total) capacitance versus pressure for decreasing

48 diaphragm radii (and increasing pressure range) in the linear range of the contact mode. The plots predict device performance parameters including sensitivity, nonlinearity. Note that the gap and SiC thickness are kept constant at 0.5 μm and 3

μm respectively. Keeping the above parameters constant enables us to fabricate devices with different pressure ranges at the same time by implementing them on the same mask set.

Capacitance contributed by the contact part is at first not linearly proportional to pressure, but progressively becomes so. In contrast, the capacitance of the non-contact part initially increases non-linearly but then progressively flattens. Together, these two parts complement each other and overall curve exhibits good linearity than either individually.

r-70μm 1.7-3.5MPa 140 120 C total 100 80 C non-contact 60 40

Capacitance (pF) Capacitance 20 C contact 0 1.3 1.8 2.3 2.8 3.3 3.8 Pressure (MPa)

Figure 3.11 Plot of capacitance versus pressure for r=70 μm.

r-58μm 3.4-7.0MPa 120 C total 100

80 C non-contact 60

Capacitance (pF) Capacitance 20 C contact 0 2.7 3.7 4.7 5.7 6.7 7.7 Pressure (MPa)

Figure 3.12 Plot of capacitance versus pressure for r=58 μm.

r-47μm 6.4-17MPa 120 C total 100

80 C non-contact

Capacitance (pF) Capacitance 20 C contact 0 6 8 10 12 14 16 18 Pressure (MPa)

Figure 3.13 Plot of capacitance versus pressure for r=47 μm.

r-38μm 18-34MPa 120

100 C total 80 C non-contact 60

Capacitance (pF) Capacitance 20 C contact 0 15 20 25 30 35 Pressure (MPa)

Figure 3.14 Plot of capacitance versus pressure for r=38 μm.

r-31μm 34-72MPa 90 80 C total 70 60 C non-contact 50 40 30 20

Capacitance (pF) Capacitance C contact 10 0 30 40 50 60 70 Pressure (MPa)

Figure 3.15 Plot of capacitance versus pressure for r=31 μm.

Table 3.4 lists the calculated performance of the touch mode pressure sensors and the corresponding sensors parameters. The calculations are based on arrayed devices.

In comparing Table 3.3 and Table 3.4, we observe that the contact mode devices exhibit higher sensitivity and higher non-linearity than the small-deflection mode devices.

Table 3.4 Performance comparisons between pressure sensor arrays for different

range and process parameters (contact mode).

Number Total Sensitivity(f Gap (um) P(MPa) R (μm) H(μm) D Wmax(μm) NL (% ) of sensitivity F/Pa) elements (fF/Pa) 1.7-3.4 70 3 9.28E-07 0.5 9.9E-05 3.69% 176 1.7E-02 3.4-6.9 58 3 9.28E-07 0.5 3.5E-05 3.53% 228 7.9E-03 0.5 6.9-17 47 3 9.28E-07 0.5 9.2E-06 3.86% 336 3.1E-03 14-34 38 3 9.28E-07 0.5 2.8E-06 3.18% 480 1.3E-03 34-69 31 3 9.28E-07 0.5 8.6E-07 2.82% 630 5.4E-04

1.4-2.1 97 3 9.28E-07 1.5 1.6E-04 3.65% 130 2.1E-02 1.5 2.1-3.4 86 3 9.28E-07 1.5 7.5E-05 4.93% 150 1.1E-02 4.1-6.9 71 3 9.28E-07 1.5 2.5E-05 3.85% 176 4.4E-03

3.2.3 Analytical design of 50 mmHg pressure sensor

Pressure sensors for medical applications usually need to measure the pressure range from 0 to 50 mmHg relative to an atmosphere (i.e., 0.101-0.108 MPa range). An example of a medical application is an implantable blood pressure monitoring system.

In such implantable applications, power consumption is a critical engineering constraint. Capacitive devices offer a clear advantage over their piezoresistive counterparts in the area of power consumption. In addition, at low pressure ranges, capacitive pressure sensors have higher sensitivity than piezoresistive devices. SiC capacitive pressure sensors possess advantages over silicon capacitive sensors due to their superior chemical inertness within the human fluid environment [56]. This section describes the design of a low pressure SiC capacitive pressure sensor for medical applications. Two approaches may be used to realize the sensors in this case:

A sensor with a sealed cavity close to vacuum (absolute pressure sensor) or a sensor with a cavity at atmospheric pressure (gage pressure sensor). 52

Absolute pressure sensor

In this version of the sensor, the pressure inside the cavity is ~ 47 Pa (in comparison to atmospheric pressure of 101,325Pa). The intrinsic stress in the diaphragm is 0-200 MPa tensile (29,000 psi). For calculation purposes, a plane stress of 100 MPa (14,500 psi) is considered.

In this work, both small-deflection mode and contact mode structures were designed with Mathematica to do the complex integration of capacitance.

Table 3.5 Analytical design of 0.108 MPa (15.7 psi) small deflection mode

absolute pressure sensor.

SiC diaphragm (μm) gap (μm) Radius (μm) Sensitivity (fF/Pa) NL(%) 0.5 49 2.4E-02 0.16 1 1 49 5.1E-03 0.06 1.5 49 2.1E-03 0.04 0.5 108 1.5E-01 0.21 3 1 145 2.4E-01 0.32 1.5 145 7.7E-02 0.17

To simplify fabrication, only two SiC film thicknesses were chosen for all the designs in this work. For the small-deflection mode, the maximum center deflection must be limited to less than 20% of the diaphragm thickness. Taking this into consideration, as observed in Table 3.5 for 1 μm diaphragm thickness, the same dimension (49 μm radius) may be shared for sensors with different gaps. However, as the gap increases, the sensitivity decreases, although nonlinearity remains well within

1%. Similarly, for 3 μm diaphragm thickness, the maximum possible dimension is

53 limited to 145 μm radius. However, the maximum deflection of 0.6 μm cannot be achieved for the 0.5 μm gap. Thus, a much smaller diaphragm dimension of 108 μm radius is chosen. From the results in Table 3.5, we see that the structure with 1 μm gap and 3 μm diaphragm thickness has the highest sensitivity but the worst nonlinearity. Considering process limitations, a 0.5 μm gap and 3 μm-thick diaphragm is chosen for these sensors, trading off sensitivity for diaphragm size.

Table 3.6 Analytical design of 0.108 MPa (15.7 psi) contact mode absolute

pressure sensor.

SiC diaphragm (μm) gap (μm) Radius (μm) Sensitivity (fF/Pa) NL(%) 0.5 95 7.5E-01 0.30 1 1 95 5.8E-01 0.094 1.5 N/A N/A N/A 0.5 180 2.3E-01 0.42 3 1 233 4.4E-01 0.23 1.5 270 6.2E-01 0.23

Compared with the small-deflection mode, the contact mode allows a much larger diaphragm dimension, leading to higher sensitivity. However, the dimension is limited by burst pressure concerns (2× maximum operating pressure). With a

1μm-thick SiC diaphragm, the maximum possible radius is 95 μm. For the 1.5 μm gap, even the maximum pressure loading does not result in contact. The 0.5 μm gap provides the highest sensitivity.

For the same values of burst pressure, the maximum radius of a 3 μm-thick diaphragm is 270 μm. The optimal radius can be found based on the fact that the

linear range of the contact mode occurs between 1.2PT and 2.5PT (PT is the touch

54 pressure, 0.04 MPa (6.3 psi) in this case). From Table 3.6 the highest sensitivity and lowest non-linearity is exhibited by sensors with the largest diaphragms. However, fabrication parameters, in particular, the diaphragm release time places design constraints. In addition, large diaphragms are very fragile. Thus, from prior experience, the ideal dimension size is limited to less than 100 μm radius. The only acceptable choice from Table 3.6 is then 0.5 μm gap with 1 μm-thick diaphragm.

Gage pressure sensor

In this case, pressure inside the cavity is at 1 atm (14.7 psi). Therefore, a relative pressure of 6895 Pa (1 psi) affects diaphragm deflection. The relative low pressure requires the design of a sensor with a large radius to make it sufficiently sensitive.

However, at the same time, the dimensions are limited when considering the burst pressure, as well as process complexity. In small deflection mode, for a 1 μm-thick diaphragm, the maximum center deflection has to be less than 0.2 μm. Thus, the radius of the diaphragm must be less than 126 μm, irrespective of gap spacing. This dimension meets the burst pressure specification as well. In addition, because the 0.2

μm deflection is acceptable for 0.5 μm gap structures, these three structures can share the same radius. For 3 μm-thick diaphragm with a radius of less than 100 μm, it is impossible to produce a higher sensitivity than a 1 μm-thick structure. The final design chosen for fabrication was a 1 μm-thick diaphragm, with 0.5 μm gap and 95

μm radius. The capacitance versus pressure behavior is shown in Fig. 3.16.

r-95μm, 6895 Pa small deflection mode 53

50 Capacitance (pF) Capacitance 50

49 0 2000 4000 6000 8000 Pressure (Pa)

Figure 3.16 Performance of a 0.5 μm-gap, 90 μm-radius, 1 μm-thick diaphragm pressure sensor with 0.46fF/Pa (3.2 pF /psi) sensitivity and 0.94% nonlinearity.

For the contact mode, a much larger diaphragm radius (280 μm) is necessary to ensure contact. An important observation is that, a single set of dimensions can be used for the absolute pressure sensor when operated in contact mode and gage pressure sensor when operated in small-deflection mode. The former shows slightly better performance characteristics than the latter, the sensitivity and nonlinearity being

0.75 fF/Pa (5.17 pF/psi) and 0.30% versus (0.46 fF/Pa) 3.2 pF/psi and 0.94%, respectively.

Chapter 4

FINITE ELEMENT ANALYSES

4.1 Introduction

Finite element techniques were used to verify the analytical models of Chapter 3.

The commercial software package COMSOL was used to perform the analyses. Figure

4.1 shows the quarter symmetry model of the pressure sensor used in COMSOL. The quarter symmetry model substantially reduced the computational resources required to analyze the sensor. The model here varies slightly from the actual structure fabricated:

(i) the diaphragm is rigidly fixed over the entire circumference and not at discrete intervals; (ii) there is no sealing ring; and (iii) the step-up geometry of the anchored edges is ignored. However, the combination of the sealing ring and the anchoring geometry is expected to provide a high degree of rigidity, closely approximating the fixed edge assumed in the model here.

3 μm SiC diaphragm

0.5 μm 2 μm air Si3N4 layer gap

SiC or Si substrate

Figure 4.1 A schematic of the 3D COMSOL model.

Although the deformation of the sensor is primarily in response to applied pressure, there exist stresses in the material that result in an initial offset and also affect the deformation. Therefore, the fabrication process and the selected materials directly influence sensor operation. In this case, the diaphragm is formed from poly-SiC and is anchored around its edge on a LSN insulating layer. The bulk substrate may be either Si or SiC. The mismatch in the coefficient of thermal expansion (CTE) between the films and/or between the film(s) and substrate produces stresses in the diaphragm that can affect device performance with temperature. In this chapter, pressure versus capacitance effects are modeled for both small-deflection and contact mode behavior.

The sensors are modeled with and without the diaphragm residual film stress. Sensor behavior as a function of temperature is modeled, including CTE effects.

4.2 COMSOL simulation for diaphragm deflection

4.2.1 Small-deflection mode simulation

Figure 4.2 Deflection of a r=48 μm diaphragm under 3.4 MPa (500 psi) pressure from FEA. r=0 always at the diaphragm center.

0.00 0 10 20 30 40 50 60 -0.05

-0.10 COMSOL with initial stress -0.15 COMSOL without initial stress -0.20 calculation with

initial stress Deflection (μm) -0.25 calculation without initial stress -0.30

-0.35 Along diaphragm radius r (μm)

Figure 4.3 FEA compared with analytical model for deflection of a diaphragm under pressure (r=48 μm and gap=2 μm)

Figure 4.2 shows diaphragm deflection for a pressure sensor with a diaphragm radius of 48 μm undergoing small deflection due to a 3.4 MPa (500 psi) pressure load.

(r=0 always at the diaphragm center.) The warm colors indicate areas of greater deflection; the cool colors indicate areas of little or no deflection. Figure 4.3 plots the deflection as a function of diaphragm radius for the FEA and analytical models. When the poly-SiC diaphragm residual stress is included, 100 MPa is assumed. In both cases, the maximum deflection is at the center, in agreement with the analytical calculation.

4.2.2 Contact mode simulation

It is not strictly possible to model the contact occurrence using COMSOL. The reason is that, at the point of contact, there is a topology change, i.e., a domain is split into two, which is beyond the capability of the moving mesh mode to handle. One way to approach contact mode modeling is to build a contact force which is large enough to keep the system in convergent state at all times. This contact force is an exponential function of the gap. In addition, in order to utilize the moving mesh mode,

the gap in the model G0 cannot be the actual gap and instead includes an offset. Thus,

the actual gap g0=G0-offset, and the resulting gap after deformation is g=g0 + w

(where w is the z-displacement). The contact force can be defined as

(4.1) where Tn is the contact pressure at initiation of the contact. ―Scale‖ defines how rapidly the contact force increases. 60

0.00 0 10 20 30 40 50 60 70 -0.05

-0.10

) -0.15 0.7MPa m

μ 1.4MPa -0.20 2.1MPa -0.25 2.8MPa 3.4MPa

Deflection ( -0.30 4.1MPa -0.35

-0.40

-0.45 Along diaphragm radius r (μm)

Figure 4.4 Deflection of a diaphragm with r=58 μm under different pressures from FEA (0.4 μm gap).

Figure 4.4 is a plot of displacement along the radius of a pressure sensor with r=58 μm. The contact does not occur until the pressure is over 2.2 MPa (320 psi), in agreement with the analytical model. As the pressure increases further, the contact area, i.e., area near r=0, increases proportionally.

58 μm contact mode under 2.8MPa 0.00 0 10 20 30 40 50 60 70 -0.05

-0.10

) m

μ -0.15 COMSOL 2.8MPa -0.20 calculation 2.8MPa

-0.25 Deflection ( Deflection -0.30

-0.35

-0.40

-0.45 Along diaphragm radius r (μm) Figure 4.5 Comparison between FEA and analytical models at 2.8 MPa (400 psi) pressure.

58 μm contact mode under 3.4MPa 0.00 0.00E+00 1.00E+01 2.00E+01 3.00E+01 4.00E+01 5.00E+01 6.00E+01 7.00E+01 -0.05

-0.10 )

-0.15 m

μ COMSOL 3.4MPai -0.20 calculation 3.4MPa -0.25

-0.30 Deflection ( Deflection

-0.35

-0.40

-0.45 Along diaphragm radius r (μm)

Figure 4.6 Comparison between FEA and analytical models at 3.4 MPa (500 psi) pressure.

58 μm contact mode under 4.1MPa 0.00E+00 0.00E+00 1.00E+01 2.00E+01 3.00E+01 4.00E+01 5.00E+01 6.00E+01 7.00E+01 -5.00E-02

-1.00E-01

) -1.50E-01 m

μ COMSOL 4.1MPa -2.00E-01 calculation 4.1MPa -2.50E-01

Deflection Deflection ( -3.00E-01

-3.50E-01

-4.00E-01

-4.50E-01 Along diaphragm radius r (μm)

Figure 4.7 Comparison between FEA and analytical models at 4.1 MPa (600 psi) pressure.

Figures 4.5-4.7 compare FEA and analytical results for increasing pressure from

2.8 to 4.1 MPa (400 to 600 psi). The results match closely with respect to the contact areas area prediction but show different slopes with respect to diaphragm curvature.

The reason may be that in the analytical calculations, a simple function was applied to approximate the large deflection of the diaphragm in Eq. (3.28). Comparatively, the finite element method gives a more accurate description of the mode shape. It should be noted that the capacitance change caused by the contact area change has a dominant effect on the total capacitance change. Thus, the analytical method still provides a valuable estimate of capacitance versus pressure.

4.3 Thermal mismatch stress effect

4.3.1 Background

Chemical reactions, including doping (by diffusion or ion implantation), lattice mismatch and/or rapid deposition (evaporation or sputtering) can all lead to very highly stressed films. We can think of residual stress in thin films as having two components, namely thermal-mismatch stress and intrinsic stress. The latter is due to all effects other than thermal mismatch. Intrinsic stress can sometimes be annealed out completely, while some amount of thermal mismatch stress is unavoidable when working with materials having different thermal expansion coefficients.

It is preferable for a sensor, particularly one that is designed to operate at elevated temperatures, to be made entirely from a single material to avoid thermal mismatch stress effects. An all-SiC (i.e., diaphragm and substrate) capacitive pressure sensor has been reported by our group [6]. However, with respect to applications where cost may be a concern a Si substrate is preferable if the thermal mismatch effects can be accommodated for acceptable performance. SiC substrates are typically much more expensive than their Si counterparts and supplier choices are limited.

To the best of our knowledge, there does not appear to be any study relating performance of capacitive pressure sensors to CTE mismatch effects when diaphragms of one material are used on substrates of another. A comparison of the performance of sensors with SiC substrates against those with Si substrates is detailed below as a function of temperature. The diaphragm is made of poly-SiC always. 64

4.3.2 Analytical model

The coefficient of thermal expansion describes how the size of an object changes with a change in temperature. Specifically, it measures the fractional change in volume per degree change in temperature at a constant pressure.

Stress in thin film

Figure 4.8 A simple structure for film stress calculation.

1) Linear thermal expansion coefficient relates the change in a material's

linear dimensions to a change in temperature (ΔT). It is the fractional change

in length per degree of temperature change.

(4.2)

(4.3)

where T is temperature, T0 is the reference temperature and is the strain in x-axis.

2) The volume thermal expansion coefficient relates the change in a

material’s volumes to a change in temperature.

(4.4)

where V is volume, and and are strains along the y and z axes, respectively.

If the material is an exact isotropic material, then

(4.5)

In a simple model, let us assume a thin film is deposited on a substrate in a

stress-free state at temperature Td, as shown in Fig. 4.8. When the structure is cooled

to a lower temperature Tr, strain is caused in the film because of its different thermal expansion with respect to the substrate which is undergoing a strain . Assuming that the coefficient of thermal expansion of the substrate remains constant for a moderate temperature excursion, the change in the substrate strain for a finite temperature change can be written as

(4.6)

Where (4.7)

Since the film is much thinner than the substrate, its strain is dominated by that of the substrate; we can assume that the film strain can be calculated by

(4.8)

Compared with a film not attached on substrates (in stress-free state), the strain can be calculated as

(4.9) where is the thermal expansion coefficient of the film.

The strain difference between the attached and the free film is called the thermal mismatch strain

(4.10)

In a plane stress model

(4.11)

(4.12)

(4.13)

(4.14)

where is Poisson’s ratio. Then, a biaxial strain develops an in-plane biaxial stress given by

(4.15)

The ratio is called the biaxial modulus

(4.16)

4.5

) 4

/C 6 - 3.5

poly-sic

1E (

3 si Linear thermalLinear

2.5 expansion coefficient 2 0 200 400 600 800 1000

Temperature (ºC ) Figure 4.9 Temperature dependent linear expansion coefficient of poly-SiC and Si.

The linear thermal expansion coefficient as a function of temperature Si and poly-SiC are shown in Fig. 4.9 [57, 58]. Assuming the poly-SiC film is deposited without thermal stress at 900oC, we can calculate for the thermal expansion stress in

67 the film as it cools using the above equations (see Fig. 4.10). To do so, an elastic modulus of 401 GPa is used for our poly-SiC film.

ζ (4.17) ζ

For a thermal stress value ζ into the above adjusted equation, we can calculate the diaphragm deflection under external pressure and due to the thermal stress can be calculated. To examine the impact of thermal expansion mismatch on diaphragms of different sizes, analytical two pressure sensors with poly-SiC diaphragms on Si substrates were analyzed. These sensors were designed for pressure ranges of 5.2 and

1.7 MPa (750 psi and 250 psi), having diaphragm radii of 50 μm and 67 μm, respectively. The results are shown in Figs. 4.11 and 4.12. With increasing temperature, the sensor sensitivity increases in both cases. However, this trend is much more obvious for the larger diaphragm sensor.

250

200

150

100

50 stress (Mpa)stress 0 Thermalexpansion 0 200 400 600 800 1000 Temperature (ºC )

Figure 4.10 Thermal expansion stress for a poly-SiC film on Si wafer as a function of temperature by analytical calculation.

11.2

10.8 SiC on SiC 0ºC 10.6 SiC on Si 0ºC 10.4 SiC on Si 100ºC

10.2 SiC on Si 200ºC

10 SiC on Si 400ºC

Capacitance(pF) 9.8 SiC on Si 800ºC

9.6 0 2 4 6 Pressure (MPa)

Figure 4.11 Thermal mismatch stress impact on a small-deflection mode sensor designed for a pressure range of 5.2 MPa (750 psi), wherein the substrate is Si (50 μm radius and 1.5 μm gap).

18.5

18 SiC on SiC 0 ºC 17.5 SiC on Si 0 ºC

17 SiC on Si 100ºC SiC on Si 200ºC 16.5 SiC on Si 400ºC Capacitance(pF) 16 SiC on Si 800ºC

15.5 0 0.5 1 1.5 2 Pressure (MPa)

Figure 4.12 Thermal mismatch stress impact on a small-deflection mode sensor designed for a pressure range of 1.7 MPa (250 psi), wherein the substrate is Si (67 μm radius and 1.5 μm gap).

The above analytical calculations are based on the diaphragm being anchored

69 around its entire circumference, air as the only dielectric and the initial capacitances

(at 0 Pa external load) being the same in all cases. For comparison, the calculations were also performed for poly-SiC diaphragms on SiC substrates.

In practice however, the diaphragm is anchored on a LSN insulator layer around its circumference, rather than directly on the Si or SiC substrates. To further study how the thermal mismatch stresses affect the behavior this more complex structure, the sensors were modeled using COMSOL.

4.3.3 COMSOL simulation

The sensor in this example measures static pressures from 0 to 3.4 MPa (500 psi).

The model first computes the initial stresses from the manufacturing process, and then accounts for the structure’s mechanical deformation resulting from an applied pressure.

Finally, it calculates the sensor’s capacitance for the deformed shape. The pressure sensor consists of a 3 μm-thick poly-SiC diaphragm on a base material on SiC or Si substrates, as shown in Fig. 4.1.

We solve the 3D problem by using four application modes in COMSOL: two Solid, stress-strain application modes; one Moving Mesh (ALE) application mode; and one

Electrostatic application mode. The latter two are defined in a frame to allow the mesh to move. The solution process takes place in four steps as follows. In the first step, the solid stress-strain application mode computes the initial stress that results from the thermal expansion mismatch during sensor’s fabrication. This step is solved with the 70 static solver. In the second step, the second solid stress-strain application mode computes the deformation and stresses that result when the sensor is subject to the ambient pressure and temperature. This step uses the initial stresses and deformation from the first solid stress-strain application mode. A parametric solver is used for different values of ambient pressure.

The third and fourth steps are both solved with a parametric solver for different values of ambient pressure. The third step is to solve the ALE mesh for each ambient pressure. The fourth step solves for the electric field, resulting in an integration of capacitance for each ambient pressure.

Simulation result discussion

1. Assuming no insulating layer on top of the base electrode

First, a simple model is built (diaphragm anchored all around the circumference) without a silicon nitride insulating layer. The initial gap between the diaphragm and substrate is 2 μm.

2.10

) ) m

μ 2.00

1.90

1.80 SiC on Si 1.70 SiC on SiC 1.60

1.50

Initialgapdistance ( 0 100 200 300 400 500 Ambient temperature (ºC)

Figure 4.13 The initial gap size change caused by thermal expansion mismatch stress based on COMSOL simulation (58 μm radius and without the LSN layer).

Figure 4.13 shows no change in gap size for the poly-SiC diaphragm on a SiC substrate after fabrication, since there is no thermal mismatch. For the poly-SiC diaphragm on a Si substrate, the initial gap size decreases at lower temperatures, since the thermal mismatch stress increases with cooling to a lower ambient temperature.

160 140 120 100 80 60 SiC on Si 40 SiC on SiC

Thermal stress Thermalstress in diaphragm(MPa) 0 0 100 200 300 400 500 Ambient temperature (ºC)

Figure 4.14 Thermal stress in the poly-SiC diaphragm based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer).

Figure 4.14 shows the in-plane thermal mismatch stress at room temperature and at 400ºC. For SiC substrates, there is no stress; for Si substrates, the mismatch stress is 140 MPa at room temperature (~40 MPa at 400ºC). It does not agree with analytical calculation (200 MPa). The analytical model assumes that the mechanical stress is dominated by the substrate, which may be an oversimplification.

5.6E-02 5.5E-02 5.4E-02 5.3E-02 5.2E-02 5.1E-02 20ºC 5.0E-02 4.9E-02 400ºC

4.8E-02 Capacitance(pF) 4.7E-02 4.6E-02 0 1 2 3 4 Pressure (MPa)

Figure 4.15 The performance of a SiC substrate sensor accounting for the thermal mismatch stress based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer).

5.7E-02 5.6E-02 5.5E-02 5.4E-02 5.3E-02 5.2E-02 5.1E-02 20ºC 5.0E-02 4.9E-02 400ºC

4.8E-02 Capacitance(pF) 4.7E-02 4.6E-02 0 1 2 3 4 Pressure (MPa)

Figure 4.16 The performance of a Si substrate sensor accounting for the thermal mismatch stress based on COMSOL simulation (58 μm radius and 2 μm gap and without the LSN layer).

Figures 4.15 and 4.16 show the simulated sensor behavior (capacitance versus pressure) at room temperature and 400ºC for SiC and Si substrates, respectively. The thermal mismatch stress takes effect at lower temperatures when on a Si substrate.

2. Assuming a LSN insulator exists on the top of base electrode

We assume a 0.5 μm-thick LSN layer is deposited on the SiC or Si substrate, and the 58 μm-radius diaphragm is patterned on the top of the LSN layer with a 2 μm gap

(Fig. 4.1). This is a slight simplification of the actual sensor in order to simplify the computational complexity. When setting up the substrate bottom boundary conditions, two extreme situations are considered. First, the substrates are assumed totally fixed in three dimensions. Second, the substrates are fixed in z-direction, freely expanding in plane.

2.1 m)

μ 2.0

1.9

1.8 SiC on Si

1.7 SiC on SiC

1.6

Initial gapInitialdistance ( 1.5 0 200 400 600 800 1000 Ambient temperature (ºC)

Figure 4.17 The initial gap size change caused by thermal mismatch stress based on COMSOL simulation, with the substrate bottom fixed in x, y and z directions (58 μm radius and 2 μm gap and the LSN layer).

Figure 4.17 plots the effect of thermal stress on gap size as a function of temperature for a sensor on a SiC or Si substrate.

1600

1400

1200

1000

800

600 SiC on Si

(MPa) SiC on SiC 400

200

0 200 400 600 800 1000 Thermal stress Thermalstress indiaphragm Ambient temperautre (C)

Figure 4.18 The thermal mismatch stress in the diaphragm poly-SiC film based on COMSOL simulation, with substrate bottom fixed in x, y, and z directions (58 μm radius and 2 μm gap and with the LSN layer).

Figure 4.18 plots the thermal stress in the diaphragm as a function of temperature for a sensor on a SiC or Si substrate. In this case, the substrate is fixed in all directions.

The stress caused by thermal expansion is concentrated at the top of the diaphragm film, with tensile stress as high as 1,000 MPa (ultimate strength of SiC is 3,440 MPa).

The initial gap sizes decrease due to the high in-plane stress, causing the initial capacitance to shift to higher values at lower temperatures. The presence of the LSN insulating layer between the top diaphragm and bottom substrate results in thermal mismatch stress effects in the sensor regardless of whether the substrate is SiC or Si.

2.10

2.00

1.90

m) 1.80

μ SiC on Si ( 1.70 SiC on SiC

1.60 Initial gapInitialdistance 1.50 0 200 400 600 800 1000 Ambient temperature (ºC)

Figure 4.19 The initial gap size change caused by thermal mismatch stress based on COMSOL simulation, with substrate bottom fixed in z-direction (58 μm radius and 2 μm gap and with the LSN layer).

30 SiC on Si

20 SiC on SiC Thermal stress Thermalstress in

diaphragm(MPa) 10

0 0 200 400 600 800 1000 Ambient temperature (ºC)

Figure 4.20 Thermal expansion mismatch stress in the diaphragm poly-SiC film based on COMSOL simulation, with bottom fixed in z-direction (58 μm radius and 2 μm gap and with the LSN layer).

Figure 4.19 plots the effect of thermal stress on gap size as a function of temperature for a sensor on a SiC or Si substrate. Figure 4.20 plots the thermal stress in the diaphragm as a function of temperature for a sensor on a SiC or Si substrate. In this case, the substrate is fixed only in the z-direction. Compared to the previous case, the thermal stress produced is much smaller. There is almost no effect on sensor behavior since the initial gap size change caused by the thermal mismatch stress is negligible.

0.625 0.620 0.615 0.610 20ºC 0.605 200ºC 0.600 400ºC 0.595 600ºC

Capacitance(pF) 0.590 800ºC 0.585 0 1 2 3 4 Pressure (MPa)

Figure 4.21 COMSOL simulation of a 3.4 MPa (500 psi) small-deflection mode sensor on a Si substrate under thermal mismatch stress (58 μm radius and 2 μm gap and with the LSN layer)

0.625

0.620

0.615 20ºC 0.610 200ºC 0.605 400ºC 0.600 600ºC 0.595 Capacitance(pF) 800ºC 0.590 0 1 2 3 4 Pressure (MPa)

Figure 4.22 COMSOL simulation of a 3.4 MPa (500 psi) small-deflection mode senor on a SiC substrate under thermal mismatch stress (58 μm radius and 2 μm gap and with the LSN layer)

Figures 4.21 and 4.22 plot the simulated capacitance versus pressure as a function of temperature for sensors on Si or SiC substrates, respectively. The temperature-dependent responses in each plot are almost parallel to one other. The

78 change in capacitance at different temperatures is caused by the increase of the dielectric constant of the LSN layer. The total capacitance of the sensor is composed of two parallel connected parts: the capacitance between the top diaphragm and bottom electrode, and the capacitance formed between the poly-SiC diaphragm anchor and bottom electrode. Because the latter has a much narrower gap between the two electrodes (hence, leading to a comparatively much larger capacitance contribution), the dielectric constant change of LSN dominates the sensor behavior.

Figure 4.23 shows the temperature-dependent dielectric constant change of LSN.

8.05 8.00 y = 3E-07x2 + 4E-05x + 7.5579 7.95 7.90 7.85 7.80 7.75

dielectric constant dielectric 7.70 4

N 7.65 3

Si 7.60 7.55 0 500 1000 1500 Temperature (k)

Figure 4.23 The temperature-dependent LSN dielectric constant. [59]

Conclusion

Thermal stresses exist in the pressure sensor diaphragm after fabrication because of the existence of the thermal expansion mismatches between the different materials.

But, compared with external forces, this thermal stress has a limited effect on the sensor’s behavior. We have simulated two extreme situations (with the substrate fixed in all directions or only in one direction), but in practice the situation will be somewhere in between. The positive temperature dependent shift of capacitance could be attributed to the increase of the dielectric constant of LSN and the leakage current, rather than to thermal stress, which would work in the opposite direction. The thermal mismatch stress increases the diaphragm’s rigidity, similar to the intrinsic stress.

The higher the temperature, the lower the thermal mismatch stress (―zero thermal stress‖ is supposed to occur at SiC’s deposition temperature of 900ºC). Since the in-plane stresses in the diaphragm decrease as temperature increases, a more sensitive behavior is expected at higher temperature. A fabricated sensor on a Si substrate is characterized and the data shown in Fig. 4.24, demonstrating this behavior.

430 425 420 415 20ºC 50ºC 410 100ºC 405 150ºC 400 200ºC Capacitance(pF) 395 250ºC 390 0 1 2 3 4 5 6 Pressure (MPa)

Figure 4.24 Experimental data from a 5.2 MPa (750 psi) small-deflection mode sensor on a Si substrate under thermal mismatch stress (50 μm radius and 1.5 μm gap).

Chapter 5

FABRICATION OF SIC CAPACITIVE PRESSURE SENSORS

5.1 Introduction

This chapter describes the fabrication process for the SiC capacitive pressure sensors. A total of six photolithography masks are used to realize the sensor. The complete process flow is briefly described first, followed by the practical details of each important step. Design parameters that directly factored into the fabrication process included sensing capacitance gap size and diaphragm thickness. After fabrication, an electron microscope was used to inspect the sensor structure and identify fabrication issues, if any.

5.2 Fabrication Process

5.2.1 Process Flow Overview

1: Deposition of 200 nm-thick LSN by LPCVD for substrate isolation. The substrate may be SiC or Si.

2: (Mask1 SiC0) Deposition of 300 nm-thick low-stress n-type heavily-doped poly-SiC by LPCVD, followed by bottom-electrode photolithography and RIE etch.

3: Deposition of 400 nm-thick LSN by LPCVD to isolate the patterned poly-SiC electrode.

4: (Mask2 LSN window) Contact window photolithography and RIE etch.

5: Deposition of LTO sacrificial layer (0.5 μm or 1.5 μm-thick ) by LPCVD to define the eventual sensing capacitance gap size..

6: (Mask3 Oxide moduling) Diaphragm anchor photolithography and wet etch in buffered HF.

7: Deposition of 2.5-2.8 μm-thick low-stress n-type heavily-doped poly-SiC by LPCVD.

8: (Mask4 SiC1) Chemo-mechanical polishing of the poly-SiC film, followed by diaphragm photolithography and RIE etch.

9: Wafer-level release in buffered HF solution.

10: Deposition of 2.7 μm-thick LTO by LPCVD deposition over released diaphragm to seal the cavity in vacuum.

11: (Mask5) LTO photolithography and wet etch in buffered HF.

12: (Mask6) Ti (100 nm)/TaSi2 (400 nm)/Pt (200 nm) metallization by lift-off, followed by rapid thermal annealing.

Figure 5.1 Cross-sectional schematic view of the sensor fabrication process.

Figure 5.1 describes the sensor fabrication process, which is similar to the process by Chen [6].

SiC wafers

Two kinds of substrates, SiC and Si, are used here. The 500-700 μm-thick, 100 mm-diameter CVD SiC wafers were purchased from Morgan Advanced Ceramics.

After lapping and polishing services from Valley Design Corp, 470 μm-thick SiC substrates with a surface roughness of 16 Å resulted. For Si, p-type boron-doped 100 mm-diameter (100) wafers with a thickness of 500 μm and a resistivity of 1-10 Ω-cm were used.

LPCVD LSN

Low-stress, LPCVD LSN film deposition is used twice, once as substrate and another time for the bottom electrode isolations. The MRL Cyclone furnace at the

Cornell Nanofabrication Facility was used. The deposition reaction is at 800ºC using

dichlorosilane (SiH2Cl2) and ammonia (NH3) reaction

(5.1)

Stoichiometric Si3N4 film is known to have high residual tensile stress, while

Si-rich Si3N4 films exhibits low residual stress. A low-stress Si-rich Si3N4 film was

obtained at 800°C and 200 mTorr using NH3 and SiH2Cl2 flow rates of 95 sccm and

16 sccm, respectively. The deposition rate was approximately 24 Å/min, and the measured stress was under 180 MPa tensile.

LPCVD SiC

Low-stress, high-electrical-conductivity, poly-SiC films were used to form the base electrode and the top diaphragm. The thin films were deposited in a LPCVD

furnace designed by MRL industries, using dichlorosilane (SiH2Cl2) and acetylene

(C2H2) as precursors and ammonia (NH3) as a dopant gas. The chemical reaction is given by

(5.2) where the carbon source is C2H2 and the silicon source is SiH2Cl2. The deposition temperature and pressure were set at 900°C and 4.00 Torr, respectively. The flow

rates of DCS, C2H2 gas and NH3 (5%in H2) were 35 sccm, 180 sccm and 64 sccm, respectively. With thickness measured by a spectrophotometer (Nanospec AFT4000),

85 the deposition rate was calculated to be ~70 Å/min. The residual stress in the film was tensile, varying from 160 MPa to 50 MPa as measured with the TOHO film stress measurement tool. Film resistivity was 0.02 Ω-cm (using the OmniMAP RS35C

4-point probe thin film sheet resistance measurement system) [6]. X-ray diffraction

(XRD) data showed that all the stoichiometric films were highly textured (111) oriented, polycrystalline 3C-SiC. The surface morphology and roughness, as determined by atomic force microscopy (AFM) and scanning electron microscopy

(SEM), indicated that the surface roughness increased with increasing film thickness.

PhotoLithography

Pattern transfer was accomplished through photolithography. Positive photoresist

AZ®9245 was chosen for two reasons. Firstly, the feature resolution that can be obtained is good (< 1 μm lines and spaces at a film thickness of 5 μm). Secondly, the

5 μm (at 3500 rpm) thickness is suitable for the lift-off process and as an etch mask.

The detailed process is given below:

Table 5.1 Process parameters of 9245 Photoresist. Coat Spin: 3500rpm,60sec Soft bake 110°C,120sec Edge Bead Removal Rinse: 500 rpm, 10sec Dry: 1000 rpm, 10sec Exposure 20 sec Post Exposure Bake Not needed Development AZ 400K Developer 1:4, 120 sec spray

Exposure was done in a contact aligner (MA6/BA6 from Karl Suss) with the maximum obtainable resolution of 0.4 μm and intensity uniformity of ±5%. Mask 1 with small lateral gaps (1-2μm) used the vacuum contact mode to obtain the best resolution. To pattern the LTO ring sealing the sensing cavities, the soft contact mode was used to avoid damaging the released diaphragms. All other mask steps used the hard contact mode.

Poly-SiC Etching

The Technics 800 was used to pattern the poly-SiC films. Technics 800 is a low frequency (30 kHz) RIE capable of etching films anisotropically. For the bottom electrode etching, a 5 μm positive photoresist AZ®9245 was pattered to form an etch mask, as described above. A recipe with low etching rate to photoresist was chosen;

the parameters were RF power 350 W, pressure 300 mTorr and flow rates of CHF3,

SF6 and He, 10 sccm, 10 sccm and10 sccm, respectively.

The following chemical reactions associated with the removal of Si and C atoms in mixtures of fluorinated gases and oxygen are given in Eq. (5.3) – (5.4), [22]

(m=1 to 4) (5.3)

(5.4)

The resulting etch rate was 200 Å/min.

For the thick poly-SiC diaphragm film, another recipe was chosen, using a Ni layer as a hard mask process described below. The etching rate of Ni is much lower than that of SiC. After the etch, the Ni mask is removed in a wet chemical etchant at

87 room temperature. The parameters for SiC etching were: RF power 350 W, pressure

300 mttor and flow rates of CHF3, O2 and He 25 sccm, 10 sccm and10 sccm, respectively. The resulting etch rate was 150 Å /min for the poly-SiC film. In addition to the Eq. (5.3)-(5.4), two more chemical reactions relating to oxygen occurs during etching:

(n=1 to 2) (5.5)

(5.6)

Figure 5.2 The SiC bottom electrode patterned by Technics 800 after the photoresist mask is removed (on Si substrate).

Figure 5.3 The SiC bottom electrode patterned by Technics 800 after the photoresist mask is removed (on SiC substrate).

LSN etching

The LSN was etched in a LAM 490 RIE system with AZ®9245 as a mask.

Sulphur hexafluride (SF6) was used as the etch gas and helium (He) as the carrier gas.

The flow rates were 150 sccm for both. The chamber pressure was 300 mTorr, and the

RF power was set to 200 W during the etching process. The etch rates were about

2400 Å/min and 3000 Å/min for silicon nitride and photoresist, respectively. Because of the issues related to etch non-uniformity, over etch time was incorporated to ensure good metal contact with the underlying poly-SiC.

The endpoint was determined by measuring the step height of the pattern using a

DEKTAK stylus profilometer before and during the etch process. A monitoring structure for multimeter probing was designed into the masks to help confirm the endpoint measurements.

LTO deposition

LTO was deposited in a LPCVD furnace designed by MRL industries. Silane

(SiH4) and oxygen (O2) were used as the source gases. The reaction is given by:

(5.7)

Deposition took place at 350 mTorr and 450°C , with an O2 flow rate of 61 sccm and

SiH4 flow rate of 51 sccm. The film deposition rate was measured at 150 Å/min. After the deposition of the LTO film to seal the cavity, a thermal anneal at 1000°C for 30 min was performed to densify the film.

BOE wet etching of LTO

Buffered oxide etch or BOE (40%wt. NH4F) was used to pattern the LTO layers.

The etch rate was about 700 Å /min for both the cavity sacrificial layer and the sealing layer. This etch rate was lower than the typical etch rate of 1000 Å /min since both layers were densified as a result of subsequent thermal steps, prior to the wet etch.

Chemical mechanical polishing (CMP)

unit:nm Z range 299.87 Mean 0.204 Raw mean 72.636 Rms (Rq) 35.985 Mean roughness (Ra) 27.03 Max height (Rmax) 297

Figure 5.4 Tapping mode AFM image of a 3 μm-thick poly-SiC film surface before polishing.

The surface roughness of the poly-SiC film is related to its deposition thickness.

If the film thickness is less than 0.5 μm, a smooth surface with a roughness average Ra of less than 2 nm can be achieved. However, if the film thickness is over 1 μm, the Ra increases rapidly. Here, a thin poly-SiC layer was used for the bottom electrode and therefore polishing was not needed. The ~3 μm-thick poly-SiC diaphragm film however required polishing. In this case, a chemo-mechanical polishing process was used to reduce the surface roughness for better pattern definition and delineation.

Otherwise, the subsequent RIE of this film to delineate features produced rough and jagged sidewalls. Figure 5.4 is an AFM image of the 3 μm-thick poly-SiC surface after deposition. Ra of the unpolished (as deposited) film is 27 nm.

A polishing suspension, SF-1, produced by Logitech, Ltd.[60] was used. This suspension is primarily alkaline colloidal silica. The process was performed on a

Logitech PM5 polishing tool. Measured with the AFM tapping mode, the average roughness following polishing was greatly improved to 4 nm (see Fig. 5.5).

unit:nm Z range 32.411 Mean 0.092 Raw mean 418.1 Rms (Rq) 5.326 Mean roughness (Ra) 4.052 Max height (Rmax) 33.1 Figure 5.5 Tapping mode AFM image of a 3 μm-thick poly-SiC film surface after polishing.

Ni mask process for thick poly-SiC RIE

Poor etch selectivity was noticed when photoresist was used as an etch mask for thick poly-SiC (more than 1 μm) RIE. A Ni mask in a thickness of 200 nm was deposited by DC magnetron sputtering. To pattern the metal film with lift off process,

AZ®9245 (photoresist) was spun cast at 3500 rpm for 60 seconds to achieve a thickness of 5 μm, followed by soft bake on a hot plate at 95°C for two minutes. The coated wafer was then exposed in the SUSS® MA6 Aligner in hard contact mode. The resist was exposed to UV light for twenty seconds with an energy density of 15

92 mW/cm2. The exposed wafer was developed immediately in an AZ®400K developer solution for two minutes, followed by a DI water rinse and spin drying.

After RIE etching of poly-SiC, a commercial Ni wet etching was used to remove the film at room temperature, followed by a DI water rinse. The Ni’s removal coincided with a noticeable change in color of SiC.

Wafer-level releasing

The LTO sacrificial layer was etched in BOE to release the diaphragms. To ensure that the LTO layers under the largest diaphragms were completely etched away,

C-V testing of the diaphragms was used to monitor the etch progress. A circular poly-SiC plate 140 μm in radius was patterned on the LTO without any anchors (Fig.

5.6). When the LTO was etched away, the plate separated from the substrate. The time taken to release the 100 μm-radius diaphragms (the maximum dimension) was

22 hours for the 1.5 μm gap sensors and 31 hours for the 0.5 μm gap sensors.

Figure 5.6 The C-V features used for BOE release monitoring.

Metallization

Based on prior work [61], a multi-layer stack of Ti (100 nm)/TaSi2 (400 nm)/Pt

(200 nm) was chosen for high temperature metallization. The TaSi2 film serves as a diffusion barrier layer between the Ti and Pt films. The lift-off process was chosen to pattern the three layers together. The lift-off process began with a 5 μm-thick photoresist (AZ®9245) being spun on and developed to expose the regions where the metal was to be in direct contact. BOE was used to remove any native oxide layer on the surface. A Discovery® 24 from Denton Vacuum, LLC. [62]was used to sputter 100

nm Ti and 400 nm TaSi2 in sequence without breaking vacuum.

In order to obtain a high quality mechanical and electrical contact, the sputter chamber pressure was pumped down to 2× 10-6 Torr before deposition. The process

condition for the Ti sputtering was 5 mTorr at 250 W. For the brittle TaSi2 target, a low RF power of 100 W (at 5 mTorr) along with a slow ramp rate was used to avoid

cracking of the target. The deposition rate of Ti and TaSi2 were 3 Å/s and 1.8 Å/s, respectively.

After deposition of the two layers, the wafer was transferred to a Discovery® 18 sputtering system, also from Denton Vacuum, LLC. for a 200 nm- thick Pt over-layer coating for passivation and gold wire bonding. Lift off was performed by submerging the wafer in an acetone solution, assisted by ultrasonic agitation for 3 minutes.

Damage to the diaphragm was detected if the duration of agitation was increased to 10 min. The desired metallic features appeared after the metal in the areas with photoresist was washed away.

5.3 Fabrication challenges

5.3.1 Mask 1 Photolithography

With respect to the photolithography process of Mask 1, of particular importance challenge is the 1.5 μm narrow gap between the bottom electrode and contact pad for upper electrode. With the negative photoresist and normal hard contact exposure, the gap was not properly defined. Because of diffraction of UV light in the gap area from the surrounding region (the contact pads and bottom electrode), photoresist was not washed away easily during the development. This problem was solved by using a mask of opposite polarity (clear field) and a vacuum contact mode for exposure, (the best resolution mode). A micrograph of the properly developed features is shown in Fig. 5.7.

Figure 5.7 Optical micrograph showing proper pattern definition from Mask 1.

5.3.2 Etch control of RIE to precisely stop on underlying film

Precise control of the etching process is essential to ensure high yield.

Underetching will cause problems such as electrode shorts and contact windows which are not open. Overetching will cause problems such as damaged electrodes, missing insulating layers, rough edges and large step heights. A test die was designed as shown in Fig. 5.8 to examine the status of the etch process by electrical probing of the test features. probing the conductivity between adjacent contact pads. Table 5.2 outlines the related tests for the various etch steps in the process, as well as the established criteria. However, the test die is only effective in determining if the film is underetched, and not overetched. Therefore, periodic monitoring is necessary as the endpoint gets closer.

1 2

3 4

Figure 5.8 Test die for process monitoring. Table 5.2 Test process and the corresponding criteria.

Process Probing Status

SiC0 etch 1-3, 4-2, 1-2 open circuit

LSN windows etch 3-4 conductive,

Oxide etch 3-4; conductive,

SiC1 etch 3-5; 3-1,2-4,1-2 3-5 conductive, others open circuit

LTO sealing ring BOE etch 3-5 conductive

5.3.3 Non-uniformity of BOE etch

The BOE etch was used to pattern the anchor features in the sacrificial LTO film that established the cavity. As shown in Fig. 5.9, it was found that etching was non-uniform in these small anchor features. The reason for this non-uniformity of BOE etch may be related to surface tension preventing proper wetting of the oxide surface. The Figure 5.10 demonstrates this behavior; the color variation seen in the figure is a result of incomplete etching of the square cavities. The problem was solved by making the surface more hydrophilic. A 5-minute oxygen plasma (at 100W) was used to activate the surface and remove any residual photoresist in the cavities. Results showing the subsequent uniformity of the etching are seen in Figs. 5.11 and 5.12.

Figure 5.9 Non-uniformity of the BOE etch for the anchor features.

Figure 5.10 Non-uniformity of BOE etch of square cavities.

Figure 5.11 Uniformity of BOE etch after ashing in an Oxygen Plasma the test features.

Figure 5.12 Uniformity of BOE etch after ashing in an Oxygen Plasma the anchor features.

5.3.4 RIE of SiC films

Another issue encountered during processing was stringers left from the RIE of poly-SiC. Figure 5.13 shows how these stringers were formed. When the poly SiC is deposited on the LTO sacrificial layer, the thickness at the edge of the step is equal to the poly-SiC thickness plus the LTO thickness. When the SiC is patterned by RIE, to remove the 3 μm-thick poly-SiC film, a 0.5 μm-thick, 2-3 μm-wide poly-SiC stringer is left. After release, this stringer is suspended around the intended feature (Fig. 5.14).

Subsequently, when the LTO layer to seal the cavity is deposited, a narrow gap results underneath the stringer, inhibiting the formation of a sealed cavity. The problem is more prominent for the 0.5 μm-thick sacrificial layer used to obtain a small sensing

100 capacitance gap; there is much less room for overetching in this case versus the 1.5

μm-thick sacrificial layer. A deep reactive ion etch (DIRE) process at NASA Glenn

Research Center was employed to solve this problem described. The overetch in this

DRIE process removed the poly-SiC film at the edges without damaging the surrounding sacrificial layer. Clear features etched in the DRIE process are shown in

Fig. 5.15.

101

(a) LTO sacrificial layer deposition

(b) Conformal poly-SiC deposition

(d) After overetch

(e) Resulting suspended stringers after BOE release

Figure 5.13 The formation of a suspended stringer.

102

Figure 5.14 Optical micrograph of a broken stringer.

Figure 5.15 Features without stringers after poly-SiC etch by deep RIE.

103

5.4 Fabrication verification

Figure 5.16 Optical micrograph of pressure sensors in an array on a Si substrate.

Figure 5.17 Optical micrograph of pressure sensors in an array on a SiC substrate.

104

Figures 5.16 and 5.17 show optical micrographs of pressure sensors in an array on a Si or a SiC substrate, respectively. The contact metallization adheres strongly to the underlying layer, with no evidence of peeling that plagued many of the devices in our previous work. The concentric featurs of the different layers show good alignment.

The LTO ring closely seals the cavity (Fig. 5.22) and does not cover the diaphragm edge excessively. The exposed poly-SiC diaphragm looks smooth, uniform and is not transparent since the thickness is close to 3μm.

Figure 5.18 SEM image of pressure sensors in an array on a Si substrate.

A series of diagnostic SEM images are taken to evaluate the fabrication process quality. Figure 5.18 shows a scanning electron micrograph (SEM) of a vacuum–sealed capacitive pressure sensor with a 95 μm-radius poly-SiC diaphragm. There are twelve equally-spaced anchors anchoring the diaphragm along its periphery. The spaces

105 between adjacent two anchors form twelve release channels to allow the BOE solution to access the sacrificial LTO layer. A 30 μm-wide, 2.7 μm-thick LTO ring seals the edge of the SiC diaphragm cavity and also anchors the diaphragm further. The two sense capacitance electrodes are connected to nearby metal pads using buried poly-SiC traces which are covered by LSN.

Figure 5.19 Cross-sectional SEM of a pressure sensor on a SiC substrate.

Figure 5.19 shows a cross-sectional view of a sensor with a 68 μm-radius diaphragm. The LTO ring seals the cavity intimately. The cavity underneath the diaphragm is completely released. The poly-SiC diaphragm is flat and uniform.

Figures 5.20 and 5.21 show magnified cross-sectional views of a pressure sensor with

106 a 95 μm-radius diaphragm. The large diaphragm is flat, and the gap is uniform from center to periphery.

Figure 5.20 Cross-sectional SEM of a pressure sensor on a SiC substrate.

107

Figure 5.21 Magnified view of Fig. 5.20.

Figure 5.22 Cross-sectional SEM showing the anchor region of a pressure sensor diaphragm.

108

Figure 5.22 shows the anchor region of a sealed diaphragm. A small cavity sealed underneath the edge is formed, which connects to the cavity under the diaphragm.

This occurrence does not impact the operation of the sensor and is normal, because the LTO deposition does not fill the gap around the edge of the diaphragm.

Figure 5.23 Cross-sectional SEM of a sensor with a 0.5 μm gap on a SiC substrate.

Figure 5.23 presents a cross-sectional view of a pressure sensor with a 0.5 μm gap and 95 μm radius on a SiC substrate. The gap under the diaphragm appears straight, smooth and uniform, which is very important to obtain a linear and accurate relationship between capacitance change and pressure load. This view proves that the narrow gap fabrication is accomplished in current process.

109

71.10 71.09 71.08 71.07 71.06 71.05 71.04 71.03 71.02

Capacitance change (pf)changeCapacitance 71.01 71.00 1 2

Figure 5.24 10 minute leakage test at 6.9 MPa (1,000 psi) for a sensor on a SiC substrate with a70 μm-radius diaphragm operating in contact mode, where (1) is the initial measurement and (2) measurement after 10 minutes.

A ten-minute 6.9 MPa (1,000 psi) leakage test was performed on a 70 μm-radius contact mode pressure sensor (Fig. 5.24). The capacitance change was 0.029 pF, 0.04% of the 71.067 pF full range. Considering that this change was within the margin of accuracy of our pressure regulation, we concluded that there was no leakage in this test. In conclusion, working poly-SiC pressure sensors were successfully fabricated.

The diaphragms exhibited low film stress, as demonstrated by their flatness. Sensor with sensing capacitance gap as small as 0.5 μm were realized.

110

Chapter 6

METALLIZATION DEVELOPMENT

6.1 Introduction

High temperature contact and interconnect metallization is a key requirement for the development of the sensors described here, and in general, for SiC devices intended for high temperature applications. Ohmic contacts are electrical connections between a metal and a semiconductor which have linear current-voltage

(I-V) characteristics. Metal-semiconductor contacts are generally not Ohmic, but instead rectifying. These rectifying contacts are often referred to as Schottky contacts due to the Schottky barrier at the metal-semiconductor interface responsible for rectification.

Vacuum level Vacuum level ) s χ s Φ q - Φ m q m m s Φ Φ Φ χ ( Φ q q q q q ) = i χ Ec - b m V B q Φ

Ec Φ ( EF q q

EF Ev Ev Semiconductor Metal Metal Semiconductor Schottky contact

Figure 6.1 Energy levels and band structure of semiconductor-metal Schottky contacts.

111

Figure 6.2 Energy levels and band structure of semiconductor-metal Ohmic contacts.

The Schottky barrier height determines the electrical behavior of an Ohmic or

Schottky contact (see Figs. 6.1 and 6.2). The most important parameter of Ohmic

contacts is the specific contact resistance ρc, an intrinsic interfacial property independent of the contact geometry. In order to form a good Ohmic contact to a semiconductor, a metal with a low Schottky barrier with the semiconductor material must be selected. Contacts with low specific contact resistance, good mechanical adhesion and thermal stability are required to form a good Ohmic contact to SiC.

However, because of the wide band gap of SiC, which is about three times higher than that of silicon, almost all metals have a Schottky barrier larger than 1 eV with SiC. In order to overcome the high Schottky barriers at the interface, the most common method is to deposit transition metals on heavily-doped SiC, followed by a high temperature annealing process. A large number of Ohmic contact materials have been investigated in the last decade, in terms of structure characterization and electrical performance. Among them, nickel is the most widely used for Ohmic

112 contacts with n-type SiC. It is found that three silicides (NiSi2, NiSi, and Ni2Si) rather than nickel are in equilibrium with SiC, as seen in Ni-Si-C ternary phase diagram in Fig.6.3.

Figure 6.3 Ternary phase diaphragm of Ni-Si-C at 900ºC [63].

It has been demonstrated that Ni films annealed at temperatures in the range

900 ºC to 1000ºC can form good Ohmic contacts on heavily-doped (>1×1020) n-type

-6 2 SiC with specific contact resistance ρc as low as 1×10 Ω-cm [64]. Crofton, et al.

[65] found that the ρc decreases with increasing temperature. Auger electron spectroscopy (AES) study showed that Ni reacted with silicon to form nickel silicide

(Ni2Si) during the annealing process. However, Ni2Si is not sufficient to explain the 113

Ohmic contact behavior. Silicide formation begins at temperatures as low as 600ºC, whereas Ohmic behavior is not observed at temperatures below ~900ºC for short anneal times (~5 minute). Nikitina, et al. [3] attributed this Schottky-to-Ohmic transformation to a solid-state reaction between nickel and SiC, taking place during

Ni–SiC contact annealing at a temperature of 1040°C. This process may result in the creation of sufficient carbon vacancies in the near-interface region of the SiC to allow increased electron transport through the Schottky barrier.

The thermal stability of Ni and Ni2Si contact to 6H-SiC has been compared by

Marinova, et al. [66]. He concluded that the presence of carbon in the contact layer and at the interface is a potential source of contact degradation at high temperature.

With a Ni/Si multilayer evaporated on SiC instead of pure Ni, the contact stability

was shown to improve in a 100 hour aging test in a N2 atmosphere at 500ºC.

Han, et al. [67] has studied the formation mechanism of Ni on SiC, and concluded that a number of carbon vacancies were produced below the contact, thus playing a key role in the formation of an Ohmic contact through the reduction of effective Schottky barrier height for the transport of electrons. High temperature annealing provides enough carbon vacancies, which act as donors, thereby contributing to the formation of the Ohmic contact. However, they also cause an undesirable feature, i.e., a rough interface morphology, which inhibits the contact’s long term reliability and results in contact degradation.

To avoid the high thermal budget (950ºC for annealing) during device

114 fabrication, Deeb and Heuer [68] developed a nickel monosilicide Ohmic contact by annealing an amorphous Si film with a Ni overlayer at 300ºC. For a doping

19 3 -4 2, concentration of 1.5×10 /cm , these contacts showed a ρc of 6.9×10 Ω-cm which decreased to 10-5 Ω-cm2 upon annealing in air at 600ºC, remaining unchanged following 300 hours of annealing.

Ti based contacts to SiC also cover a wide portion of literature data, because Ti

forms very stable compounds with both silicon and carbon (mainly TiC, Ti5Si3,

Ti3SiC2) [69][70]. It has been reported that an appropriate surface preparation method may result in a Ti/SiC Ohmic contact without post-deposition annealing being necessary, due to the formation of band gap defect states near the interface.

However, Goesmann [69] investigated the reactions at Ti/SiC contacts at different annealing temperatures and discovered the following (see Fig. 6.4). Below 700ºC ,

the contacts are of Schottky type with SiC/TiC1-y/two-phase (Ti5Si3+TiC1-y)/Ti3Si/Ti as diffusion path. Between 800ºC to 1200ºC, the contacts are Ohmic contacts, with

SiC/Ti3SiC2/Ti5Si3/two-phase (Ti5Si3+TiC1-y)/Ti3Si/Ti as diffusion path. Above

1200ºC, the contacts are also Ohmic, with SiC/Ti3SiC2/Ti5Si3/two-phase

(Ti5Si3+TiC1-y)/Ti5Si3/Ti as diffusion path. Other reports state that annealing processes below 900ºC lead to Schottky contacts, while above this temperature

-5 2 Ohmic contacts are formed. ρc reaches its lowest value (3.6×10 Ω-cm ) after a

950ºC temperature anneal, when the ternary phase Ti3SiC2 starts to appear [71].

115

Figure 6.4 Ternary phase diaphragm of Ti-Si-C at 700ºC [69].

Because of the high thermal budget required to form Ohmic contacts and the ease of Ti oxidation, several studies have been carried out to investigate Ti-based

compounds, such as TiSi2, TiC, Ti/Sb, Ti/Au, Ti/Al, Ti/Ni. Schmid, et al. [72] have

studied TiSi2/6H-SiC contacts by sputtering a TiSi2 compound target on nitrogen

18 -3 implanted (ND=5×10 cm ) 6H-SiC. The formation of Ti3SiC2 at the interface accompanied by the reduction of the specific resistance to 7×10-6 Ω-cm2 was indicated after annealing at 1150ºC .

Epitaxially-grown TiC contacts by CVD or co-evaporation method have also been studied [73][73][73][72][71][69][71]. As reported, TiC contacts annealed at

-5 2 1300ºC form a good Ohmic contact with ρc of 1.3×10 Ω-cm on 6H-SiC, whereas

116

-5 2 an Ohmic contact with ρc of 1×10 Ω-cm is obtained on 4H-SiC [73]. Recently, several publications describing the combination of Ni and Ti, Ti/Al and Ti/Al/Ni to n-type and p-type SiC have been published [74-79].

To overcome the contact degradation caused by oxidation at high temperature, cap layers of noble metals such as, Au or Pt, as well as diffusion barriers for the metal are used to protect the transition metal. Okojie, et al. [4] reported thermally-stable Ti-based Ohmic contacts on both n-type 6H- and 4H-SiC, with

-4 2 stacking sequence Pt/TaSi2/Ti/SiC, and ρc as low as 1-5×10 Ω-cm . A thirty minute anneal at 600ºC was necessary to complete the transformation to Ohmic contacts. A

1000 hours aging test at 600ºC was demonstrated in air.

The above work primarily focused on α-SiC. Additional work for Ohmic contact to β-SiC is described below. It should be noted here that most of the research on Ohmic contacts focuses on α-SiC substrates, because use of β-SiC substrates has been limited by the large concentration of stacking faults in the material.

Steckl and Su [80] employed as-deposited and annealed (900ºC for 3-5 min) Ni for rectifying and Ohmic contacts, respectively, in one device. However, Cho, et al. reported that Ni could form Ohmic contact on β-SiC in the as-deposited case [81], which was attributed to the high concentration of defects in the β-SiC films.

Jacob, et al. [82] investigated Al, Ni and W contacts on APCVD 3C-SiC (1017 cm-3 nitrogen doping) and found that as-deposited samples formed Ohmic contacts

-4 2 -4 2 -3 2 with ρc of 2×10 Ω-cm , 5×10 Ω-cm and 2×10 Ω-cm , respectively. With a

117

500ºC anneal, there were no changes in the Al and W contact samples, but ρc of

Ni/SiC decreased to 5×10-5 Ω-cm2 because of the formation of additional reaction products like nickel silicide.

Chen, et al. [83] investigated both as-deposited and annealed Pt, Re and Ta films on n-type, single-crystalline β-SiC (001). The as-deposited Ta, Pt and Re

-7 contacts were all Ohmic on a nitrogen-implanted β-SiC substrate, with ρc of 1×10

Ω-cm2, 1×10-4 Ω-cm2 and 6×10-6 Ω-cm2, respectively. After a post annealing, Ta/SiC

-6 2 -5 contact resistance degraded to 4.3×10 Ω-cm , and Re/SiC ρc improved to 1×10

Ω-cm2, while Pt/SiC contact eventually lost Ohmic behavior. However, long-term high-temperature studies are missing from above work.

As we know, high temperature annealing restricts device fabrication and makes the contact surface morphology rough. The goal is to achieve Ohmic contact with

low ρc, modest thermal budget and good stability. In this work, we focus on studying

the Ohmic contact performance of Ti/TaSi2/Pt to LPCVD n-type heavily-doped

poly-SiC films used in our sensor fabrication. We compare ρc under different annealing conditions, evaluate thermal stability and analyze the diffusion status at the interface with XPS and AES.

118

6.2 Experimental

6.2.1 Selection of measurement techniques

Table 6.1 Experimental methods for specific contact resistance ρc measurement [84]. Method Test Structure Advantages Disadvantages Ref Cox and Varying diameter dots Easy to fabricate; Difficult to measure [85] Strack on top surface with gives vertical small values of large contact on back measurement of contact resistance of substrate contact resistance Kuphal 4 co-linear dots of the Easy to fabricate Inaccurate - does not [86] same diameter account for current crowing at contact edge Kelvin Diffused path and Capable of measuring Test structure [87] metal layer in a very small contact requires diffused four-point structure resistance layer Linear Equal area rectangular Easy to extract Test structure [88] TLM contacts moderate to small requires two masking values of lateral levels contact resistance Circular Varying radii Capable of extracting Requires extremely [89] TLM concentric circles on moderate to small low metal sheet epitaxial or implanted values of lateral resistance and the material contact resistance with analysis of modified only one masking level Bessel functions

Many experimental methods have been developed to measure specific contact

resistance ρc (see Table 6.1). The oldest is the Cox and Strack method [85], which was first proposed in 1967. Varying diameter dots patterned on the top surface of the semiconducting layer with a large broad area Ohmic contact on the semiconductor's back surface are used for measuring contact resistance. This structure allows for a

119 vertical measurement of the ρc through substrates, which is more suitable for vertical devices.

Two other well-known methods, for measuring contact resistances, are the

Kuphal [86] and the Kelvin techniques [87]. The Kuphal method uses four co-linear dots to measure contact resistance. It is not very accurate since it does not eliminate the error induced by current crowding at the contact edges, and the spreading resistance in the semiconductor. Although the Kelvin technique is very accurate and

useful for measuring small values of ρc, it has not been used often on SiC, because it requires a diffused or implanted layer. Linear Transmission Line Methods (L-TLM), which was proposed in 1964 and refined by Berger in 1972 [88], became a method of

determining information on semiconductor sheet resistance, as well as ρc. It is the

most widely used method to determine ρc on SiC.

Another form of the TLM method known as the Circular Transmission Line

Method was proposed by Reeves in 1980 [89] , which determines the same information as the linear TLM but is easier to fabricate. However, it requires very low metal sheet resistances in order to ensure accuracy, which is not easy to achieve because the metal layers are usually thin. In addition, the modified Bessel function equations which must be analyzed using this method are very complex. Thus, the most widely used method for measuring contact resistance on SiC, as well as the method used in this thesis, is the Linear TLM method.

120

6.2.2 Experiment

P-type boron-doped (100) Si wafers were used as substrates in this experiment.

The thickness varied from 475 μm to 500 μm, with resistivity ranging from 20 to 60

Ω -cm. The Si wafer surfaces were cleaned by successive immersion, with intermediate aqueous rinses, a standard twenty minute Piranha cleaning with a 4:1

ratio of H2SO4:H2O2, followed by rinsing and spin-drying under nitrogen. A standard

RCA clean was applied to remove metallic and organic impurities, which consisted of

a fifteen minute bath in 1:1:5 NH4OH:H2O2:H2O, a thirty second immerse in HF:H2O

1:6 solution and another 15-minute bath of 1:1:5 HCl:H2O2:H2O at 60ºC . To electrically insulate the substrates, a 2 μm-thick LTO layer was deposited by LPCVD

with silane (SiH4) and oxygen as source gases (at 450ºC and 350 mTorr). After that, another RCA clean was performed before the LPCVD SiC film deposition. A 1

μm-thick poly-SiC film was then deposited by LPCVD at 900ºC and 4 Torr, using a reaction of dichlorosilane (35 sccm) and acetylene (180 sccm), with ammonia (64 sccm) as the doping gas [17]. To enable good contact to the surface, a CMP process was applied to reduce the roughness to 4 nm Ra. DI water rinse and another piranha clean were used to clean the surface. The sheet contact resistance of the heavily-doped poly-SiC film (>11019 /cm3) was measured to be 110-150 Ω/□ with the residual stress in the film less than 200 MPa. To use L-TLM to measure the resistance of the metal-semiconductor contact, the poly-SiC layer needed to be patterned into mesas

121 before metal contact deposition. A 5 μm-thick photoresist was patterned on the poly-SiC film to prepare for the Ni lift off process. A Ni film100 nm thick was sputtered at a pressure of 310-6 Torr and power of 250 W, followed by lift off in acetone solution. Next, poly-SiC RIE was performed in the Technics 800 with a Ni

layer as mask and CF4, SF6 and O2 as reaction gases similar to the processes described in Chapter 5. The RIE etch rate was 160 Å/min. After mesa patterning, the Ni mask was removed using Ni etchant, followed by surface cleaning with piranha, DI water rinse and spin-drying. A 5-μm thick photoresist was patterned on the surface, in preparation for the metal contact lift off process. Prior to metal sputtering, the native oxide on poly-SiC was removed with a 1-min dip in a buffered oxide etch solution.

The sequence of Ti (100 nm), followed by TaSi2 (400 nm) and then Pt (200 nm) was sputtered in a Denton Discovery 24 system with a base pressure of around 10-6 Torr.

The L-TLM structure, sketched in Fig. 6.5, consists of a 105 μm-wide poly-SiC mesa and six identical metal pads, 100 μm in width and 60 μm in length. The metal pads separations increased from 10 μm to 30 μm in 5 μm intervals.

122

d L

Figure 6.5 L-TLM structure for Ohmic contact measurement.

Current-voltage (I-V) testing was carried out on a probe station using a Keithley

236 source-measure unit. A -5V to +5V DC voltage (Maximum current 100 mA) was swept across two metal pads immediately next to each other, using probes to contact the pads, and the resultant current was recorded. The total resistance was then extracted from the I-V curve. To eliminate the additional resistance caused by the probes and wires, a calibration step was performed during each measurement; the

probe tip-to-tip resistance was measured and deducted from the total resistance. ρc was next calculated from the total resistance versus contact pad separation data.

Grazing incidence X-ray diffraction analysis was carried out in the Scintag X-1 advanced X-ray diffractometer to study the reaction mechanism for various temperature annealing processes. X-ray photoelectron spectroscopy (XPS) depth

123 profile studies were carried out in a PHI VersaProbe XPS scanning Microprobe at a base pressure of 1.2×10-7 Pa. The photoelectrons were excited with a monochromated

Al Kα (24.7w) x-ray source and analyzer pass energy of 93.9 eV. The depth profile was carried out by 3 keV Ar+ beam incident at 38º, with an estimated sputtering rate

5.2 nm/min for Ta2O5. Auger electron spectroscopy (AES) was also used for chemical depth profiling using a Perkin-Elmer PHI 680 Scanning Auger Microprobe system, which consisted of a field-emission scanning electron microscope and an axial cylindrical mirror analyzer with a multi-channel detector.

The contact temperature annealing process and high-temperature long-term aging tests were performed in an OTF-1200X high-temperature vacuum tube furnace. At intervals of 100 hours during the aging test, the sample was cooled down to room

temperature to measure the ρc. The sample was cooled to room temperature to

measure ρc at intervals of 100 hours during the aging test.

124

6.3 Result and discussion

ρc calculation

0.1

0.08

0.06

0.04

0.02 IV(1,2) IV(2,3) 0 IV(3,4) -1.5 -0.5 0.5 1.5 -0.02 Current ACurrent IV(4,5) IV(5,6) -0.04

-0.06

-0.08

-0.1 Voltage V

Figure 6.6 I-V data between two nearby contact pads for a typical as-deposited contact (i.e., no thermal anneal). I-V(1,2) means I-V curve between Pad 1 and Pad 2.

Figure 6.6 shows the measured room-temperature I-V characteristic of contacts without post-metallization annealing (i.e., as-deposited), indicating Ohmic behavior.

For the TLM test structure, the total resistance of the contact is [88]:

(6.1)

where Rs is the poly-SiC sheet resistance under the contact, L and W are the length

and the width of the contact pads, respectively. The transfer length, Lt, is:

(6.2)

125

The transfer length Lt is defined as the distance from the edge of the contact at which the current density drops to 1/e of its original value. In the case of , the contact resistance equation can be simplified to

(6.3)

A measurement of the total resistance, RT, between pairs of adjacent contact pads with a variable separation d can therefore be fitted into a straight line:

(6.4)

Rs can then be obtained from the slope of this line, while the contact resistance (and ρc) can be obtained from the intersection with the y-axis; the transfer length can be

obtained from the intersection with the x-axis. In this experiment, Lt is usually less than 10 μm, while L is set to 100 μm; henceforth, is satisfied.

126

Figure 6.7 is an example of the total resistance versus contact pad spacing data for an as-deposited sample. Data from all test samples in this study show excellent linearity, i.e., R2 ≥0.99 .

Resistance vs spacing 12 11 y = 0.2856x + 2.9502 R² = 0.9972 10

9 test1 8 test2 7 test3

6 test4 Resistance Resistance (ohm) 5 test5 4 0 10 20 30 40 Spacing (μm)

Figure 6.7 Total resistance versus contact pad separation for a typical as-deposited contact.

127

Effect of annealing on ρc

ρc was measured and calculated under different post-deposition annealing

temperatures. As shown in Fig. 6.8, we measured ρc of as-deposited metallization as

5.710-6 Ω-cm2, lower than the value of similar contacts on 6H-SiC (110-5 Ω-cm2)

[4].

)

cm 

1E-5

1E-6

0 100 200 300 400 500 600 700 800 900 Specific contact resistance ( o Anneal temperature ( C)

Figure 6.8 ρc as a function of post-deposition anneal temperature in a nitrogen ambient. All anneals are for 30 minutes.

-6 2 19 -3 Our value is close to the ρc of 510 Ω-cm for Ti on highly-doped (610 cm )

3C-SiC surface [90].*To study the anneal effect on ρc for different temperatures, 14 samples were divided into 7 groups and annealed up to 800ºC . Thus, 12 sets of test

features were measured for ρc at each anneal temperature (six sets on each sample).

-6 Annealing at 600ºC after metallization further reduced the average ρc to 4.810

2 Ω-cm . ρc increased to a much higher level after annealing at 700ºC for half an hour, accompanied by surface morphology changes. The reason for the decrease in SCR at

128

600ºC is that a new phase of Ti5Si3 begins to form at the Ti/SiC interface. This could be detected from the glancing XRD analysis on samples subjected to different anneal

temperatures. Figure 6.9 shows the effect of anneal time at 600ºC; the lowest ρc is obtained for the 45 minute anneal. Six sets of test features were used for each anneal

time. ) 2 1E-5

cm 9E-6

 8E-6 7E-6 6E-6

5E-6

4E-6

3E-6

2E-6 Specific contact resistance ( 15 30 45 60 Anneal time (min)

Figure 6.9 ρc as a function of post-deposition anneal time at 600ºC in a nitrogen ambient.

Samples were then prepared for a 1000-hour aging test at 550ºC in air. Based on the previous studies (Fig. 6.9), the samples were annealed at 600ºC for 45 mins in

-5 2 nitrogen. After 100 hours at 550ºC, ρc increased to 2.410 Ω-cm . The contact maintained its Ohmic behavior throughout the 1000-hour test.

129

Aging test study on Ohmic contact after 120 minute anneal at 600ºC

-5 2 Figure 6.10 shows that ρc measured is lower than 510 Ω-cm up to the 800

hours marks. Beyond 800 hours, ρc trends to a much higher value, which is likely due

to oxidation of the metal surface.

) 2

cm 1E-4 

sample 1

1E-5 sample 2 Specific contact resistance ( 1E-6 0 200 400 600 800 1000 Aging test time (hour)

Figure 6.10 Aging time test of ρc at 550ºC in air, following a 45-min anneal at 600ºC in nitrogen ambient.

It is believed that a silicon dioxide layer forms on the metal pad surface, making electrical probing of the underlying platinum silicide layer difficult, but also limiting a further migration of oxygen to the metal-SiC interface, thereby extending the life of the contact. However, lateral oxidation of the contact pads causes delamination and damage at the pads’ edges, thereby decreasing the effective contact area. The latter effect was also reported by Okojie, et al [4]. Unfortunately, our current experiments do not allow separating these effects from those associated directly with the metal-semiconductor contact.

130

Effects of annealing at different temperature

XRD analysis was employed to study the phases formed in the annealed contacts.

Six samples from the same Si wafer with metal already deposited on the SiC layer, were annealed for 30 minutes from 300ºC to 800ºC. Figure 6.11 shows the results of the glancing incidence x-ray diffraction analysis (incidence angle 1º) for each of the samples. An as-deposited sample was also analyzed for comparison.

Figure 6.11 Glancing incidence x-ray diffraction analyses of the samples annealed for 30 minutes at different temperatures.

For the as-deposited sample and the samples up to 500ºC, only the reflection peaks corresponding to Pt, 3C-SiC, are observed. XRD spectra of samples annealed

131 beyond 500ºC show new diffraction peaks corresponding to platinum silicide Pt2Si

and Pt3Si. The peaks corresponding to tantalum silicide phases Ta5Si3 and TaSi2

appear only at anneal temperature beyond 600ºC . It seems that the amorphous TaSi2 starts to crystallize from 600ºC . Along with the crystallization and phase conversion

(such as from TaSi2 to Ta5Si3), a lower ρc was observed at 600ºC .

We noticed the shift of Pt2Si and Pt3Si peak to a lower 2θ, which indicates the lattice plane distance d increased (2.79 to 2.88 Å, and 1.89 to 1.93 Å). There are reasons due to which this may happen, such as residual stress, composition variation, stacking fault and surface geometry (including surface curvature, surface inclination effect, surface roughness). Usually the sin2Ψ method is applied to measure the stress, based on the measurement of the shift of a diffraction peak position recorded for different Ψ angles—the angle between the diffracting plane normal and the specimen surface normal. A high-2θ diffraction peak is chosen to ensure higher sensitivity to strain. However, for thin films, high-2θ diffraction peaks might be too weak to be conveniently measured. In the GIXRD, the residual stress can be derived from a plot of the lattice parameters calculated from different peaks vs. sin2Ψ (Ψ corresponds to the Bragg angle θ minus the grazing angle α). However, due to the preferred

orientation of the highly textured thin film, only one peak of Pt2Si is present in the diffraction spectra. Furthermore, because of small incidence angles, the effect of refraction has to be considered, which leads to an increase of the measured diffraction angle 2θ of a hkl reflection and thus to an error of the resulting lattice spacing, d.[91]

132

Based on above reasons, the exact evaluation on stress in the films was not obtained in this work. A rough estimation of the stress (for a Young’s modulus of 100 GPa

[92]) is calculated to be larger than 5 GPa, a platinum silicide film stress stated in the literature [93]. Then the lattice parameters change may caused by another factor—composition change. The ratio of Pt to Si varies with temperatures when atoms get different diffusion energy. And, because the ratio of Pt to Si is not exactly

2:1 or 3:1 in the Pt2Si and Pt3Si compounds, interstitial or substitutional defects exist in some density. These defects cause the lattice parameters deviate from the standard compound, thus cause the diffraction peaks shift.

Figure 6.12 is an SEM showing the surface morphology after annealing at 500ºC temperature.

Figure 6.12 Surface morphology of Ohmic contact after 30 min anneal at 500ºC.

133

For the sample subjected to 600ºC (Fig.6.13), some particles were observed on the surface of contacts. An Auger analysis (Fig 6.14) of the areas shown in Fig.6.13 indicates that the concave area has the lowest Pt concentration, while the convex area has the highest Pt concentration.

Figure 6.13 Surface morphology of Ohmic contact after 30 min anneal at 600ºC.

The 40%-50% carbon most probably comes from the contamination in the air. Si and O exists with the atomic concentration ratio is close to 1:1 (Fig.6.14), indicating an incomplete oxidation of platinum silicide on top surface.

134

Figure 6.14 The Auger analysis on the surface after 600ºC anneal in N2. When the temperature reaches 700ºC , these bright clusters increase in number and spread over the surface (Fig 6.15).

Figure 6.15 Surface morphology of Ohmic contact after 30 min anneal at 700ºC

The Pt atomic ratio is comparably much higher than the value detected on the surface after 600ºC anneal (Fig 6.16).

135

Figure 6.16 The Auger analysis on the surface after 700ºC anneal in N2.

Fig 6.17 clearly demonstrates that the Pt-rich clusters increase in size at 800ºC .

Figure 6.17 Surface morphology of Ohmic contact after 30 min anneal at 800ºC.

The remaining areas have a lower atomic concentration of Pt with Si:O ratio still close to 1:1 (Fig 6.18). However, since single phase silicon monoxide can only be

136 formed from condensing SiO gas at 1300ºC [94]. SiOx is most probably formed as a mixture of finely divided silicon dioxide and silicon. The clustered surfaces lead to a high surface roughness, decreasing the effective contact area between probes and the

metal surface. Furthermore, the resistivity also increases due to the thin SiOx layer

presence. These factors lead to the obvious raise of ρc at 700 ºC and higher temperatures.

Figure 6.18 The Auger analysis on the surface after 800ºC anneal in N2.

An auger depth profile study with 10.2 nm/min sputtering rate (Fig 6.19 ) was

performed on the top surface of the sample after an 800ºC anneal in N2. The study

indicates that the SiOx layer is about 10 nm in thickness. This SiOx co-exists with the

Pt rich clusters on top surface. The oxygen content decreases to less than 5% at

100-nm depth. The atomic ratio of Pt to Si keeps is constant at 2:1 across the depth up

to100 nm, indicating the Pt2Si formed due to silicon’s out-diffusion. A similar surface 137 morphology change was reported by Okojie.[95] It was attributed to the non-uniform surface oxidation of the platinum silicide, with the Si source resulting from the

decomposition of TaSi2 during the 30 minutes anneal in nitrogen.

Figure 6.19 AES depth profile of the metal surface after 800ºC anneal in N2.

138

AES depth profile study of Ohmic contacts

100 Pt4

80 C1 N1 60 Ta2 O1 Si2 40 Ti2 C1 Ti2 Si2 20 Ta2 O1 Pt4 N1 Atomicconcentration (%) 0 0 20 40 60 80 100 120

Sputter time (min) Figure 6.20 AES depth profile for a typical as-deposited contact.

In order to have further insight into the reaction mechanism, the cross-sectional

distribution of the elements inside the as-deposited Pt/TaSi2/Ti contacts was examined by the Auger depth profile measurement. Figure 6.20 indicates that after metal sputtering, the platinum, titanium and tantalum atoms show some diffusivity into the nearby metal layers. However, there is no indication that new phases are formed in the interface. A significant amount of carbon is present in the tantalum silicide zone; the carbon comes either from the ambient or the ion gun during the sputtering. The silicon concentration is surprisingly lower than expected, due to differential sputtering efficiency for Ta and Si in the AES depth profile analysis. AES analysis was conducted directly on the tantalum silicide target. The target was found to have a

Ta:Si atomic concentration ratio of 1:2 on the fresh fracture surface; on the other hand,

139

AES depth profiling with sputtering indicated that tantalum was at a higher atomic concentration than silicon.

The as-deposited metallization formed Ohmic contacts with SiC without any thermal treatment, which was also observed by Chen for Re, Ta and Pt contacts on

3C-SiC [83]. Since no interface reaction occurred, it is believed that the formation of

Ohmic contact on β-SiC is possibly more linked to the polycrystalline nature of the

SiC film, having defects such as grain boundaries and high roughness.

Figure 6.21 shows the AES depth profile of a typical contact after a two hour anneal at 600ºC in nitrogen. At this temperature, silicon diffuses into the platinum and

titanium layers, forming Pt2Si and Ti5Si3; STEM analysis, shown later, was done to confirm the nature of the resulting compounds. Platinum has diffused into the tantalum silicide layer, while tantulum silicide and carbon do not show an obvious decrease over the same depth.

140

100

C1 Pt4 Ta2 60 N1 Ti2 O1 Si2 40 Si2 C1 Ti2 20 Ta2 Pt4 O1 N1

Atomicconcentration (%) 0 0 20 40 60 80 100 120 Sputter time (min)

Figure 6.21 AES depth profile of a typical contact following a 120-min anneal at 600ºC in a nitrogen ambient.

Compared with the contact depth profile data for a short anneal (Fig. 6.21), long-term aging data (Fig. 6.22) shows a smoother depth profile for platinum. During the aging test, the platinum reaches the titanium silicide layer and forms platinum silicide.

Oxygen of the order of 20% atomic concentration was detected on the outermost surface of the sample after the 2 hour anneal (Fig.6.21), which increased to 50% following 100 hours of the aging test (Fig. 6.22). The platinum silicide, present at the surface after the anneal process, likely reacts with residual oxygen from the ambient to form a silicon dioxide layer.

141

100

80 C1 Pt4 Ta2 60 N1 O1 Ti2 40 Si2 Si2 Ti2 C1 Ta2 20 Pt4 O1 N1

0 Atomicconcentration (%) 0 20 40 60 80 100 120 Sputter time (min)

Figure 6.22 AES depth profile of a typical contact following a 100-hours aging test at 600ºC in air.

142

XPS study on Ohmic contact after a 120 minute 600ºC anneal

To study the reaction mechanism at the interface after anneal, x-ray photoelectron spectroscopy (XPS) studies were carried out on a typical contact following a 120 min anneal at 600ºC in nitrogen ambient. The shift of the Ta4f (Fig. 6.23) photoelectron lines of the thin film confirms the existence of two Tantalum phases. Over 80% of the area of the upper layer peaks is occupied by the peak with a binding energy of 22.3

eV and 24.5 eV, corresponding to Ta4f7/2 and Ta4f5/2 in TaSi2. The lower layer appearing close to the Ti layer is composed of two pairs of peaks, 50% of the area is occupied by peaks with binding energies of 21.6 eV and 23.5 eV, corresponding to metallic Ta. Another 50% is occupied by peaks with binding energies of 22.3 eV and

24.5 eV, which are the Ta4f peaks in TaSi2.

Figure 6.23 Binding energy shift of the Ta4f photoelectron peak along depth profile.

143

Figure 6.24 illustrates the binding energy shift of the Pt4f photoelectron peak.

The upper layer contains Pt4f peaks (over 94% of the area) with a binding energy of

71.9 eV and 75.1 eV corresponding to Pt2Si 4f7/2 and 4f5/2, respectively [96], the other 6% corresponds to the 4f7/2 and 4f5/2 of Pt. When the Pt diffuses into the Ti layer, a new phase is formed, and the binding energy of 71.3 eV and 74.6 eV

corresponds to the 4f7/2 and 4f5/2 peaks of the Pt3Ti peaks. However, since there is just a small amount of Pt in the Ti layer, it was not detected by further STEM profile scans.

Figure 6.24 Binding energy shift of the Pt4f photoelectron peak.

144

The Si2s binding energy peak of the topmost layer is not shown in Fig. 6.25,

which has a binding energy of 153.6 eV, corresponding to SiOx on the top surface of the sample. The photoelectron lines of Si2s underlying the surface consist of two peaks with binding energies of 151.3eV (69% of area) and 153.2eV(22% of area). the

former peak corresponding to Si2s peak in TaSi2. In the Ti layer, the binding energy of

150eV correponds to the peak of Si2s in titanium silicides [97].

Figure 6.25 Binding energy shift of the Si2s photoelectron peak.

145

As shown in figure 6.26, the binding energy of O1s at the surface presents a

single peak at 532.4ev, which corresponds to the bonding energy of O1s in SiO2. It approves again that the silicon oxide phase form on the top surface of the sample following anneal at 600ºC for 2 hours in nitrogen. The source of the oxygen may be the residule gas in the chamber due to samples loading. The formation of thin Oxide layer on a Pt layer deposited on Si annealed at 500ºC or higher temperature in oxygen or inert gas enviornment has been reported, attributing to the Platinum silicide formation and silicon out diffusion.[98][99] The thin film limits the further diffusion of oxygen to the metal underneath, leading to the parabolic growth rate of oxidation.

Figure 6.26 Binding energy peak of the O1s at surface.

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STEM line scan study on Ti/SiC interface

To further study the contact interface compounds formed after 2 hours annealing in nitrogen, we applied a FEI Nova 200 NanoLab DualBeam™ system at the

Swagelok Center to prepare a TEM cross sectional sample (Fig. 6.26). The TEM investigations were performed on a LIBRA 200FE made by Zeiss, operating with an accelerating voltage of 200 kV, combining the versatility of a new, aberration-corrected in-column OMEGA energy filter with the advantages of a field-emission gun and Köhler illumination energy.

Figure 6.26 TEM sample prepared by FIB.

147

The multilayer structure of Ti/TaSi2/Pt was clearly observed in the STEM image in Fig. 6.27.

Figure 6.27 STEM cross-sectional image of the multilayer metallization.

The Ti/SiC interface is enlarged by performing a line scan (Fig. 6.28).

Figure 6.28 STEM line scan profile.

148

From the STEM line scan (Table 6.2), we observe that in both interface layers

close to Ti, the atomic ratio of Ti to Si is close to 5:3, which corresponds to the Ti5Si3 compounds we found in XRD analysis after a 600ºC anneal. A TiC layer is most likely formed in the center of Ti layer, where most of the silicon is consumed in the reaction with Ti at the interfaces.

Table 6.2 Atomic concentration of elements at line scan points.

Element Point 1 Point2 Point3 Point4 C(K) 48.63 34.45 53.19 34.71 O(K) 0.07 0.83 1.25 1.39 Si(K) 51.28 25.94 6.50 26.41 Ti(K) 0.00 38.77 39.05 37.47 Ta(L) 0.00 0.00 0.00 0.00

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CONCLUSION

Multilayer Ohmic contacts of Ti/TaSi2/Pt to heavily-nitrogen-doped, n-type poly-SiC were studied in this work. The contacts show good Ohmic behavior both in the as-deposited state, as well as with post-deposition annealing up to 800ºC. Effects

of different annealing temperatures and times on the ρc were also examined. The

-6 2 lowest ρc measured was approximately 410 Ω-cm on the samples that underwent

600ºC annealing for 45 minutes in a nitrogen ambient. AES depth profile analysis provided information on contact material composition. The polycrystalline nature of the SiC film defects were thought to be possibly responsible for the Ohmic contact

behavior with the as-dposited Ti/TaSi2/Pt stack. Titanium silicide, platinum silicide,

and tantalum silicide appeared to be the three main formations influencing ρc after the annealing process. The 1000 hours aging test in air proves the high temperature reliability of this metallization. While the oxidation of platinum silicide forms a protective layer on the metal pad surface, lateral oxidization of the contact pads causes delamination and damage at the pad’s edges. Incorporating a passivation layer on top of the metallization (and around the pad’s edges) may therefore improve the thermal and electrical stability of this Ohmic contact.

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Chapter 7

PRESSURE SENSOR CHARACTERIZATION

7.1 Introduction

The performance of the pressure sensors was studied by measuring the capacitance change with pressure. Properties including nonlinearity, sensitivity, resolution and hysteresis were investigated in order to understand the effects of the substrate choice (Si or SiC), sensing capacitance gap size and the operational mode

(small deflection or contact mode). These measurements were conducted from room temperature to 550ºC . For safety, pressure testing was limited to 8.3 MPa (1,200 psi).

Figure 7.1 describes the nomenclature used for the sensors in this chapter. The nomenclature to identify the sensors is as follows:

AAA-B-CC-DD-EEE

A: Substrate choice (Si or SiC)

B: Operational mode (small deflection or contact mode)

C: Sensing capacitance gap size (15 for 1.5 μm and 05 for 0.5μm)

D: Diaphragm radius (in microns)

E: Pressure range per design (in psi)

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SiC substrate Si substrate

Small deflection 1.5um gap SiC-S-15-54-500 SiC-S-15-47-700 Si-S-15-47-700 mode

Small deflection 0.5um gap SiC-S-05-37-500 mode

Contact 1.5um gap mode SiC-T-15-70-1000 SiC-T-15-95-300 Si-T-15-68-1200

Contact 0.5um gap mode SiC-T-05-70-500

Figure 7.1 Sensor types used for characterization along with their nomenclature.

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7.2 Test setup

7.2.1 Basic theory

The equivalent circuit of a device can be modeled as a simple circuit comprising lumped elements representing the real and imaginary (resistive and reactive) parts of the total equivalent circuit impedance. Figure 7.2 shows the equivalent circuit of a capacitor. Capacitors have small amounts of parasitic elements that can be modeled as series resistance (Rs), series inductance (Ls) and parallel resistance (Rp).

The relative magnitude of the reactance (1/(ωC)), series resistance (Rs) and parallel resistance (Rp) determines the optimal mode of measurement. When the capacitor exhibits a high (1/(ωC)), Rp is the primary determinant relative to (Rs), for the real part of the capacitor’s impedance. Accordingly, a parallel equivalent circuit consisting of C and Rp is a reasonable approximation to the complex circuit model.

When the reactance of a capacitor is low, Rs is a more significant determinant than Rp.

Thus, a series equivalent circuit becomes the approximate model. In our measurement, for the most part, the reactance is higher than the parallel resistance. Thus, the parallel equivalent circuit mode is chosen for measurement.

153

Figure 7.2 Model for a capacitor with parasitic elements.

7.2.2 Measurement setup

The high temperature pressure test was performed in an in-house designed stainless steel (SS) chamber shown in Fig. 7.3. A regulator was used to control the pressure going to the chamber, and a digital pressure gauge (OMEGA DPG1202) was used to monitor the pressure. The SS chamber had ports for electrical interconnects.

Temperature LCR meter controller

Digital pressure gage Nitrogen gas tank

Regulator

Stainless steel chamber

Figure 7.3 Schematic of the test measurement setup.

A high efficiency heating system (Fig. 7.4) capable of heating a packaged sensor

154 to 550ºC was setup inside the SS chamber. The heating system consisted of two brass bars with through-holes for cartridge heaters (120 W and 0.25 inch diameter). An appropriately packaged sensor could then be clamped between the bars with adjustable end caps. This setup provided maximum contact area for quick heating. A thermocouple tip was buried directly in the shallow surface of the fixture, on the side in direct contact with the metal lid of the package as shown in Fig. 7.5. A thermal controller was set outside the chamber to obtain the thermocouple feedback and control the heater power (Fig. 7.3). The setup proved to be stable during the high temperature experiment.

The room for Adjustable cartridge heater bolt

Room for fixing the package

Cartridge heater

Figure 7.4 Rendering of heating fixture

155

Groove to insert K type thermal couple

Figure 7.5 Individual brass bar showing thermocouple placement.

It should be recalled here that each pressure sensor die tested was an array of several sensors to ensure a large enough capacitance change for read out. Thus, an

LCR meter (Agilent-E4980A) was used to directly measure the capacitance. The sensor die was attached onto the Dual In Line-package (DIP) (Spectrum

Semiconductor Materials, Inc. [100]) with a high temperature metallic adhesive

(Cotronics Corporation [101]). Gold rather than aluminum bond wires were used.

Measurements were made using the four-wire technique. To ensure a high degree of accuracy, the LCR meter was calibrated each time when it was powered on or when any connections were changed.

7.2.3 Packages

Two kinds of packages were used (see Fig. 7.6): a ceramic dip package from 156

Spectrum Semiconductor Materials, Inc.; and a flatpack metal package from AEGIS,

Inc. [102]. The former was composed of an alumina (Al2O3) body, tungsten metallization and gold over nickel metal plating. The latter was made from one piece of metal Kovar, a nickel-cobalt ferrous alloy.

Flatpack metal package Ceramic DIP package

Figure 7.6 Packages used for pressure sensor packaging and testing.

To test the thermal reliability, a 24 hour test at 550ºC was performed on both package types. An alumina board with thick film gold printed traces were epoxied in the cavity of the packages. Gold wires were used to bond the traces to the bond pads in the packages. Mica-glass insulated nickel coated copper conductor wires (designed for stable operation up to 450ºC by OMEGA Engineering, Inc. [103]) were used to connect to the package pins. The setup was heated and the change in resistance to three arbitrary terminals was monitored. Any change in resistance would be a function of several factors including wire bonding, thick film metal degradation and package component deterioration. Figure 7.7 shows the resistance curves for the metal flatpack recorded over 25 hrs. T1, T2 and T3 are the three terminals used. Figure 7.8 shows the

157 resistance curves for the ceramic DIP package; the large peak is a glitch caused by manual handling. The small resistance deviation proved that both of these packages, as well as the associated wire bonding and connections operate, well through the test, thereby providing us confidence for the high temperature measurements.

9 600 8

6 T1-T2 5 T2-T3 300 T3-T1

Temperature (ºC) Temperature Resistance (Ω) Resistance 3

2 0 1

0 0 5 10 15 20 25 30 Time (hours)

Figure 7.7 Thermal reliability tests at 550ºC in air for the metal flatpack package.

158

15 14

13 600

12 11 10 9 400 8 7 T1-T2

Resistance (Ω) Resistance 6 T2-T3 5 T3-T1 (ºC) Temperature 4 200 3 2 1 0 0 0 5 10 15 20 25 30 35 Time (hours)

Figure 7.8 Thermal reliability tests at 550ºC in air for the ceramic DIP package.

159

7.3 Dielectric property study of SiNx

In the sensor construction, low-stress SiNx deposited by LPCVD is used as an

insulating layer. Stoichiometric silicon nitride (Si3N4) has an intrinsic tensile stress of

~910 MPa at room temperature. The intrinsic tensile stress can be decreased to 125

MPa by increasing the silicon content to form a SiNx composition [104]. LPCVD SiNx has a significant advantage for the fabrication process here because of nitride’s

inertness to HF etching. However, compared with SiO2, it also has a few points of concern such as higher electrical conductivity and more fixed charge storage. The thermal stability of this insulating layer is very important for the performance of the sensor; therefore, it is necessary to study its temperature dependent behavior.

Figure 7.9 shows the structure used to measure the dielectric constant of the SiNx

layer. A 200 nm-thick SiNx layer was deposited on a Si substrate. A 300 nm-thick heavily-doped poly-SiC electrode was deposited and patterned into a circular pad of

400 μm radius. A 400 nm-thick SiNx layer was deposited to cover the bottom

electrode. Following etching of the SiNx layer, a contact belt area of poly-SiC was

exposed. A Ti/TaSi2/Pt metal layer was then deposited by sputtering. The metal, which also served as the top electrode, was then patterned by lift-off. Thus, the contact belt area was brought in contact with the bottom electrode and extended to the contact pad.

The screen belt was used to eliminate parasitic noise from the area around the top electrode. The capacitance measurement was obtained by probing the top and bottom electrodes on a probe station. An LCR meter was used to directly read the output

160 capacitance.

Metal

SiNx on SiC

SiNx

Figure 7.9 The C-V structure used for dielectric constant study of SiNx.

As shown in Fig. 7.10, the red points indicate the measured values from the LCR meter, while the blue points indicate the estimated capacitance based on the reference

data of the dielectric constant of Si3N4. The difference between calculation and measurement is most likely due to parasitic capacitance and fringing fields. Figure

7.10 shows that as temperature increases, capacitance increases faster than predicted.

The leakage current through the SiNx layer may contribute to such behavior.

161

13.0

12.5

12.0

11.5 calculation

11.0 experiment

10.5 Capacitance(pF) 10.0 0 100 200 300 400 Temperature (ºC)

Figure 7.10 Measured result of C-V structure compared with the calculation.

Leakage current measurement was then performed on sensor arrays with SiC

substrate and Si substrate incorporating the SiNx insulator layer using Source

Measurement Unit (SMU) with 1V DC or 5V DC input (as Fig. 7.11).

0.6

) 2 0.5

Si substrate 1V DC 0.4

Si substrate 5V DC 0.3

0.2 SiC substrate 1V DC

0.1 SiC substrate 5V DC

Leackage current (A/cm 0 0 100 200 300 400 500 600 Temperature (ºC )

Figure 7.11 Leakage current measurements on sensor arrays

162

The resulting leakage currents plot shows that the leakage currents are dependent on temperature, and also related to the DC bias voltages. At temperatures over 300ºC , the leakage current increases 1000 times compared with the room temperature value

and is no longer negligible. The capacitor becomes leaky when the equivalent Rp in parallel with C is too low. This results in resistive impedance overwhelming the capacitive impedance, and the C value is lost in the noise [105]. Figure 7.12 plots D

(measured simultaneously with the capacitance readings by the LCR meter) as a function of temperatures for the SiC-T-05-70-500 sensor array from room temperature to 550ºC with 10 kHz 1V AC signal. D is defined as the ratio of the power loss in a dielectric material to the total power transmitted through the dielectric, the imperfection of the dielectric. It is equal to the tangent of the loss angle

(dimensionless):

( 7.1)

where is the applied frequency; Cp is the equivalent parallel capacitor; is the equivalent parallel resistance and is loss angle. As the dissipation factor D increases, the accuracy of the capacitance measurement degrades.

163

9 8 7 6 5

D 4 3 2 1 0 0 100 200 300 400 500 600

Temperature (ºC)

Figure 7.12 D measurements of a SiC sensor array at different temperatures.

At higher temperatures, the measurement is more sensitive to the parallel impedance change. Thus, the noise produced by temperature fluctuation influences the capacitance signal, worsening linearity as well as resolution. However, higher measurement frequencies can be applied to solve the problem. At higher frequencies, the capacitive impedance is lower, resulting in a C current that is higher and more easily measured. Since the best working condition of the SiC impedance amplifier is

10 kHz, we used 10 kHz as the default condition for sensor array characterization.

164

7.4 Sensor array testing

Several tests including stand-alone and comparison at room and elevated temperatures were conducted. Sensor testing followed the outline given below:

1. Comparison between sensors with different sensing gaps

a. SiC-S-15-54-500 versus SiC-S- 05-37-500

2. Comparison between sensors fabricated on SiC and Si substrates

a. SiC-S-15-47-700 versus Si-S-15-47-700 at room temperature and 500oC

b. Testing of Si substrate contact mode sensor Si-T-15-68-1200 at high

temperature

3. Comparison between small deflection mode and contact mode sensors

a. Testing of SiC-S-05-37-500 as a function of temperature

b. Testing of SiC-T-05-70-500 as a function of temperature

c. Comparison between SiC-S-05-37-500 and SiC-T-05-70-500

4. Testing of contact mode SiC substrate sensors for different pressure ranges

a. Testing of SiC-T-15-70-1000 as a function of temperature

b. Testing of SiC-T-15-95-300 as a function of temperature

The comparison between sensors with different pressure ranges is not meaningful, because typically sensors spanning smaller pressure range possess higher sensitivity.

Thus, all the comparisons are performed between sensors with the same pressure range. We first compare the sensors with different sensing gaps (SiC-S-15-54-500 versus SiC-S-05-37-500) for same pressure range at room temperature. We investigate if the increase in sensitivity due to a smaller sensing gap is offset by the decrease in radius. To study the performance of lower cost Si substrate sensors, two dimensionally identical sensors fabricated on SiC and Si substrates operating in small

165 deflection mode (SiC-S-15-47-700 versus Si-S-15-47-700) are compared at room temperature and 500°C. A Si substrate sensor operating in contact mode is also characterized as a function of temperature. Next we compare sensors with different operating modes at different operating temperatures, for the same pressure range.

Finally, to complete the study over an expansive pressure range, two designs with small sensing gaps operating in contact mode and fabricated on SiC substrate were characterized at different temperatures.

High temperature testing was limited to 550°C, the maximum sustained operating temperature of the heater.

7.4.1 Analytical calculation versus experimental data

Figures 7.13 to 7.15 compare the calculation/experimental data for small deflection mode sensors. The measured sensitivity is less than that calculated and linearity worse than that calculated. The lower measured sensitivity may be a result of the base electrode radius being smaller than the diaphragm radius, as compared to the equal radius used for calculation. The linearity measurement is partially related to the hysteresis error as will be observed in the later sections.

166

5.0 4.5 4.0 3.5 3.0 2.5 Calculation 2.0 Experiment 1.5 1.0 0.5 0.0

Capacitancechange (pf) 0 1 2 3 4 Pressure (MPa)

Figure 7.13 Measured response versus analytical calculations for SiC-S-15-54-500.

5.0 4.5 4.0 3.5 3.0 2.5 2.0 Calculation 1.5 Experiment 1.0 0.5

Capacitance change (pF) changeCapacitance 0.0 0 1 2 3 4 Pressure (MPa)

Figure 7.14 Measured response versus analytical calculation for SiC-S-05-37-500.

167

4.5 4.0 3.5 3.0 2.5 Calculation 2.0 1.5 Experiment 1.0 0.5

0.0 Capacitance change (pF) changeCapacitance 0 2 4 6 Pressure (MPa)

Figure 7.15 Measured response versus analytical calculation for SiC-S-15-47-700.

Figures 7.16 to 7.19 compare the calculation/experimental data for contact mode sensors. The experimental curves of capacitance versus pressure of these sensors follow the trend of the analytical calculations. The linear behavior extends over a wider pressure range than that calculated. This may be attributed to the simplified equations in the analytical calculations. The sensitivity is not lower than the calculation as in the case of the small deflection mode, because the contact area dominates the capacitance change. Compared with small deflection mode sensors, the contact mode pressure sensors exhibit higher sensitivity. Characteristics such as hysteresis, resolution and nonlinearity are discussed briefly in the following paragraphs.

168

90 80 70 60 Calculation 50 40 Experiment 30 20 10

0 Capacitancechange (pF) -10 0 2 4 6 8 Pressure (MPa)

Figure 7.16 Measured response versus analytical calculation for SiC-T-15-70-1000.

30 Calculation Experiment 20

Capacitancechange (pF) 0 0 0.5 1 1.5 2 2.5 Pressure (MPa)

Figure 7.17 Measured response versus analytical calculation of device SiC-T-15-95-300.

169

100 90 80 70 60 Calculation 50

40 Experiment 30 20 10

Capacitancechange (pF) 0 0 1 2 3 4

Pressure (MPa) Figure 7.18 Measured response versus analytical calculation for SiC-T-05-70-500.

50 45 40 35 30 25 20 Calculation 15 Experiment 10 5 0

Capacitancechange (pF) -5 0 2 4 6 8 10

Pressure (MPa)

Figure 7.19 Measured response versus analytical calculation for Si-T-15-68-1200.

7.4.2 Comparison between sensors with different sensing gaps

Sensors designed for the same pressure range but with different sensing capacitance gaps were compared at room temperature. Device SiC-S-15-54-500 has a

SiC diaphragm 54 μm in radius and sensing capacitance gap of 1.5 μm. Device 170

SiC-S-05-37-500 has a diaphragm 37 μm in radius and sensing capacitance gap of 0.5

μm. Both are operated in small deflection mode.

Comparing the data in Figs. 7.13-7.14 and Figs. 7.20-7.21, both sensors demonstrated good repeatability and a linear capacitance change with pressure.

However, linearity is not as good as that expected based on the analytical calculations.

4.5 4 3.5 3 2.5 1 2 2 1.5 3 1 4 0.5

Capacitancechange (pF) 0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 Pressure load (MPa)

Figure 7.20 Capacitance versus pressure (C vs. P) plot for SiC-S-15-54-500 at room temperature (decreasing load).

171

4.5 4.0 3.5 3.0 1 2.5 2.0 2 1.5 3 1.0 4 0.5

Capacitancechange (pF) 0.0 0 0.5 1 1.5 2 2.5 3 3.5 4 Pressure (MPa) Figure 7.21 C vs. P plot for SiC-S-05-37-500 at room temperature (decreasing load).

Table 7.1 outlines the results from the testing. The smaller gap sensor possesses a higher sensitivity than the larger gap sensor, even though its diaphragm dimension is much smaller. It is also superior to the larger gap sensor in both linearity and resolution. Decreasing sensing gap improves sensor sensitivity for a given pressure range.

172

Table 7.1 Performance comparison between SiC-S-15-54-500 and

SiC-S-05-37-500. SiC-S-15-54-500 SiC-S-05-37-500 Gap (μm) 1.5 0.5 Sensitivity (fF/Pa) 1.1E-03 1.2E-03 Nonlinearity 4.1% 2.0% Resolution 2.1% 1.2%

7.4.3 Comparison between sensors fabricated on SiC and Si substrates

7.4.3.1 SiC-S-15-47-700 versus Si-S-15-47-700

One focus of this work was comparing the difference in performance between pressure sensors fabricated on SiC substrates and those on Si substrates. Two sensors with identical dimensions and fabrication processes, but different substrates, were compared at room temperature and 500ºC . Each sensor has a 47 μm-radius diaphragm with 1.5 μm sensing gap. Both were operated in the small deflection mode.

From Figures 7.22-7.23, we observe that both sensors demonstrate similar performance at room temperature. They have similar relative capacitance change at full pressure loading, with good repeatability.

173

4.0

3.5

3.0

2.5

2.0 1 2 1.5 3 1.0 4 0.5

0.0 Capacitancechange (pF) 0 1 2 3 4 5 6 Pressure (MPa)

Figure 7.22 C vs. P plot for SiC-S-15-47-700 at room temperature (decreasing load).

4.0

3.5

3.0

2.5

2.0 1 1.5 2

1.0 3

0.5 Capacitancechange (pF) 0.0 0 1 2 3 4 5 6 Pressure (MPa)

Figure 7.23 C vs. P plot for Si-S-15-47-700 at room temperature (decreasing load).

From Table 7.2, we observe the Si substrate sensor is slightly superior to SiC substrate sensor in linearity at room temperature. The performances of these two sensors are in agreement with results from COMSOL simulation—the effect from thermal expansion mismatch stresses is almost negligible.

174

Table 7.2 Performance comparison between SiC-S-15-47-700 and Si-S-15-47-700

at room temperature. SiC-S-15-47-700 Si-S-15-47-700 Substrate SiC Si Sensitivity (fF/Pa) 6.5E-04 6.1E-04 Nonlinearity 5.0% 3.9% Resolution 0.2% 0.3%

Figures 7.24-7.25 show the sensor array (with SiC substrate and Si substrate) performance as a function of pressure at 500ºC . Both sensors demonstrate good linearity, repeatability and similar sensitivity. This result agrees with our prediction about the negligible thermal mismatch influence based on COMSOL simulation.

1 30 2

20 3 4 10

Capacitancechange (pF) 0 1 2 3 4 5 6 Pressure (MPa)

Figure 7.24 C vs. P plot for SiC-S-15-47-700 at 500 ºC (decreasing load).

175

30 1 2 20 3

10 4

0 Capacitancechange (pF) 0 1 2 3 4 5 6 Pressure (MPa)

Figure 7.25 C vs. P plot for Si-S-15-47-700 at 500ºC (decreasing load).

Table 7.3 indicates that the SiC substrate sensor shows similar sensitivity with better linearity and resolution compared with Si substrate sensor. The difference in nonlinearity may relate to the higher thermal stability of the electrical properties of the SiC substrate.

Table 7.3 Performance comparison between SiC-S-15-47-700 and Si-S-15-47-700

at 500ºC .

SiC-S-15-47-700 Si-S-15-47-700 Substrate SiC Si Sensitivity (fF/Pa) 1.2E-02 1.1E-02 Nonlinearity 2.6% 3.8% Resolution 0.5% 1.8%

7.4.3.2 Testing of Si substrate contact mode sensor Si-T-15-68-1200 at high temperature

The Si substrate contact mode pressure sensor Si-T-15-68-1200 was

176 characterized at different temperatures. The room temperature C vs P plot (Fig. 7.26) shows typical touch mode behavior. Touch mode operation was also verified at 300oC

(Fig. 7.27) and 400oC (Fig. 7.28). Repeatability at all three test temperatures was very good. However, at 400oC, the linearity deteriorated. Tests using an LCZ were not possible beyond this temperature.

45 40 35 30 25 20 1 15 2 3 10 5

0 Capacitancechange (pF) -5 0 2 4 6 8 10 Pressure (MPa)

Figure 7.26 C vs. P plot for Si-T-15-68-1200 at room temperature (increasing load).

30 1

20 2 3 10

Capacitancechange (pF) 2 3 4 5 6 7 8 9 -10 Pressure (MPa)

Figure 7.27 C vs. P plot for Si-T-15-68-1200 at 300ºC (increasing load).

177

120

100

60 1 40 2

Capacitancechange (pF) 0 2 3 4 5 6 7 8 Pressure (MPa)

Figure 7.28 C vs. P plot for Si-T-15-68-1200 at 400ºC (increasing load).

Figure 7.29 shows the repeatability tests of the same Si substrate sensor array at 0

Pa load at 400ºC . At temperatures over 400ºC , the readout is extremely noisy. This is likely caused by packaging issues such as shorts between bonding wires and metal traces. A Si-substrate sensor of a different design was successfully tested up to 500ºC

(section 7.4.3.1).

178

1.E+50

8.E+49

6.E+49

4.E+49

2.E+49 Capacitance(pF) 0.E+00 0 10 20 30 40 50 Measurements

Figure 7.29 Capacitance measurements repeated 40 times at 400ºC.

The sensor array performance is listed in Table 7.4. The 1.E50 has no sense of capacitance value, it is an over range readout recorded by instrument, while the normal values is at 1E3 level. Thus packaging issues rather than thermal expansion mismatch issues limit high temperature tests of this Si substrate sensor array.

Table 7.4 Performance of Si-T-15-68-1200 at different temperatures. Room temp 300ºC 400ºC Sensitivity 3.6E-03 8.4E-03 2.0E-02 (fF/Pa) Nonlinearity 3.9% 2.8% 5.6% Resolution 0.6% 1.6% 2.2%

179

7.4.4 Comparison between small deflection mode and contact mode sensors

In this section, the test results of a small deflection mode sensor SiC-S-05-37-500 and a contact mode sensor SiC-T-05-70-500 as a function of temperature are presented individually and then compared.

7.4.4.1 Testing of SiC-S-05-37-500 as a function of temperature

Since the deflection must to be limited to less than 40% of the gap to achieve acceptable linearity, the diaphragm radius of SiC-S-05-37-500 was limited to 37 μm.

Sensor sensitivity, nonlinearity and resolution at room temperature were previously discussed in Section 7.4.2.

Figure 7.30 plots sensor hysteresis over four cycles. The hysteresis corresponds to 0.88%FS. Figures 7.31-7.33 show the sensitivity is increasing with temperature.

The reason for this behavior may be attributable to the high leakage current.

180

4.0

3.5

3.0

2.5

2.0 1 1.5 2

1.0 3 4 0.5

0.0 0 0.5 1 1.5 2 2.5 3 3.5 4 Capacitancechange (pF) -0.5

-1.0 Pressure (MPa)

Figure 7.30 Hysteresis plot for SiC-S-05-37-500 at room temperature over four cycles.

4.0

3.5

3.0

2.5

2.0 1 1.5 2 1.0 3

0.5

0.0 Capacitancechange (pF) -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 Pressure (MPa)

Figure 7.31 C vs. P plot for SiC-S-05-37-500 at 100ºC (increasing load).

181

8 1 6 2 3 4 4 2

0 Capacitancechange (pF) 0 1 2 3 4 -2 Pressure (MPa)

Figure 7.32 C vs. P plot for SiC-S-05-37-500 at 200ºC (increasing load).

182

1 5 2

0 1 2 3 4 Capacitancechange (pF) -5

Pressure (MPa) Figure 7.33 C vs. P plot for SiC-S-05-37-500 at 400ºC (increasing load).

The 400ºC test was performed with 0.1V, 100 kHz excitation signal rather than at

1 V and 10 kHz used in the other measurements, due to high noise levels during measurement. However, this high noise problem was not observed during high temperature tests with other SiC substrate sensors. Packaging issues such as shorting wire bonds may be the most likely cause. The increased sensitivity and degraded resolution at elevated temperature are clearly observed in Table 7.5.

Table 7.5 Performance of SiC-S-05-37-500 at different temperatures. Room temp 100ºC 200ºC 400ºC Sensitivity (fF/Pa) 1.1E-03 1.0E-03 3.2E-03 5.4E-03 Nonlinearity 2.2% 2.8% 2.3% 3.0% Resolution 1.3% 2.0% 1.4% 3.0%

183

7.4.4.2 Testing of SiC-T-05-70-500 as a function of temperature

Here, we characterize a pressure sensor fabricated on a SiC substrate, with a 0.5

μm gap and operating in contact mode. Sensor repeatability tests were conducted over a period of five days. Figure 7.34 shows the excellent convergence of the five trials.

100 90 80 70 60 day1 50 day2 40 day3 30 day4 20 day5 10

Capacitancechange (pF) 0 0 1 2 3 4

Pressure (MPa) Figure 7.34 Repeatability test for SiC-T-05-70-500 at room temperature over 5 days (increasing load)

184

Figures 7.35-7.40 demonstrate the excellent sensitivity, wide linear range and high operating temperature of this sensor. The repeatability is very good at temperatures less than 300ºC, but degrades at higher temperatures. The resolution and nonlinearity also degrade beyond 300ºC .

100 90 80 70 60 50 1 40 2 30 3 20 4 10

0 Capacitancechange (pF) -10 0 1 2 3 4 Pressure (MPa)

Figure 7.35 C vs. P plot for SiC-T-05-70-500 at 100ºC (increasing load).

100 90 80 70 60 1 50 40 2 30 3 20 4 10

0 Capacitancechange (pF) -10 0 1 2 3 4 Pressure (MPa)

Figure 7.36 C vs. P plot for SiC-T-05-70-500 at 200ºC (increasing load).

185

100 90 80 70 60 50 1 40 2 30 3 20 4 10 0 Capacitancechange (pF) -10 0 1 2 3 4 Pressure (MPa)

Figure 7.37 C vs. P plot for SiC-T-05-70-500 at 300ºC (increasing load).

140

120

100

80 1 60 2 3 40 4 20

Capacitancechange (pF) 0 0 0.5 1 1.5 2 2.5 3 3.5 4 -20

Pressure (MPa) Figure 7.38 C vs. P plot for SiC-T-05-70-500 at 400ºC (increasing load).

186

160

140

120

100

80 1 2 60 3 40 4 20

0 Capacitancechange (pF) 0 1 2 3 4 -20

Pressure (MPa) Figure 7.39 C vs. P plot for SiC-T-05-70-500 at 500ºC (increasing load).

180 160 140 120

100 1 80 2 60 3 40 4 20

0 Capacitancechange (pF) -20 0 1 2 3 4 Pressure (MPa)

Figure 7.40 C vs. P plot for SiC-T-05-70-500 at 550ºC (increasing load).

187

2500 2250 2000 1750 20ºC 1500 100ºC 1250 200ºC 1000 300ºC 750 400ºC 500 500ºC

Capacitance(pF) 250 550ºC 0 0 1 2 3 4

Pressure (MPa) Figure 7.41 C vs. P plot for SiC-T-05-70-500 for temperatures up to 550ºC (increasing load)

It is also observed that the resolution degrades beyond 200ºC (Table 7.6). A temperature gradient between the sample and ambient environment results in increased heat loss. To keep the temperature constant, a series of impulse heating signals are sent from the controller to the heaters to compensate. The heater is unable to respond fast enough to the controller input resulting in temperature fluctuations.

These fluctuations affected nonlinearity and resolution of measurements.

Table 7.6 Performance of SiC-T-05-70-500 at different temperatures. Room 100ºC 200ºC 300ºC 400ºC 500ºC 550ºC temp Sensitivity 2.2E-02 2.3E-02 2.3E-02 2.3E-02 4.1E-02 5.1E-02 5.7E-02 (fF/Pa) Nonlinearity 0.9% 1.3% 1.7% 1.4% 4.1% 3.3% 2.0% Resolution 0.3% 0.1% 1.0% 0.9% 1.0% 1.0% 0.8%

188

7.4.4.3 Comparison between SiC-S-05-37-500 and SiC-T-05-70-500

Previously, we concluded that the SiC substrate is superior to Si substrate at high operating temperatures. In addition, the 0.5 μm gap is superior to 1.5 μm gap in sensitivity. Here, the contact mode sensor SiC-T-05-70-500 is compared with the small deflection mode sensor SiC-S-05-37-500 with respect to sensitivity, nonlinearity and resolution. From Table 7.7, for a given pressure range, it is clearly seen that contact mode sensor is superior in all three parameters. The small deflection sensor however, has a wider span of operation (from 0 Pa).

Table 7.7 Performance comparison between SiC-S-05-37-500 and

SiC-T-05-70-500. SiC-S-05-37-500 SiC-T-05-70-500 Operation mode Small deflection Contact Sensitivity (fF/Pa) 1.1E-03 2.2E-02 Nonlinearity 2.2% 0.9% Resolution 1.3% 0.3%

7.4.5 Testing of contact mode SiC substrate sensors for different pressure ranges

7.4.5.1 Testing of SiC-T-15-70-1000 as a function of temperature

The contact mode SiC substrate pressure sensor demonstrated excellent capacitance versus pressure characteristics at room temperature. The linear range extended to 1.7 - 6.9 MPa (250 psi to 1000 psi). Good repeatability with low hysteresis (<1%) between loading and unloading data was observed. The loading and

189 unloading data at room temperature are separately plotted in Figs. 7.42 and 7.43.

40 1 2 30 3 20 4 10

0 Capacitancechange (pF) 0 1 2 3 4 5 6 7 8 -10 Pressure (MPa)

Figure 7.42 C vs. P plot for SiC-T-15-70-1000 at room temperature (increasing load).

190

40 1 30 2 3 20

Capacitancechange (pF) 0 0 1 2 3 4 5 6 7 8 -10 Pressure (MPa)

Figure 7.43 C vs. P plot for SiC-T-15-70-1000 at room temperature (decreasing load).

Figure 7.44 shows that at 100ºC, the hysteresis error of SiC-T-15-70-1000 remains at the same low level as at room temperature. The total capacitance change is

70 pF, much higher than the performance of small deflection mode sensors for the same pressure range. Generally, the contact mode pressure sensor shows good

linearity for the 1.2 PT to 2.5 PT range. In this measurement, the linearity starts at 1.7

MPa (250 psi).

191

40 Increase 30 Decrease 20

Capacitancechange (pF) 0 0 2 4 6 8 Pressure (MPa)

Figure 7.44 Hysteresis plot for SiC-T-15-70-1000 at 100ºC.

Figure 7.45 shows that when the temperature is lower than 200ºC, there is almost no change in sensitivity. Similar to the small deflection mode sensors, a base capacitance shift with increasing temperature is observed.

820

800 20ºC-1 780 20ºC-2 760 20ºC-3 740 100ºC-1

720 100ºC-2 100ºC-3 700

Capacitance(pF) 200ºC-1 680 200ºC-2 660 200ºC-3 0 2 4 6 8 Pressure (MPa)

Figure 7.45 C vs. P plot for SiC-T-15-70-1000 for temperatures up to 200ºC (increasing load).

Figure 7.46 shows that the linear range of the sensor is reduced to 3.4 - 6.9 MPa

192

(500 - 1000 psi) at 500ºC. The linearity is still acceptable in this range, while the decrease in resolution is caused mainly by the effect of temperature on the base capacitance.

120

100

60 1

40 2 3 20

Capacitancechange (pF) 2 3 4 5 6 7 8 -20 Pressure (MPa)

Figure 7.46 C vs. P plot for SiC-T-15-70-1000 at 500ºC (increasing load).

193

Figure 7.47 plots the capacitance versus pressure for different temperatures. The temperature dependent base capacitance shift is caused by the increase in leakage current. The sensitivity increases at a higher temperature.

2000

1800

1600 20ºC 1400 100ºC 1200 200ºC 1000 300ºC

800 400ºC Capacitance(pF) 500ºC 600 0 2 4 6 8

Pressure (MPa)

Figure 7.47 C vs. P plot for SiC-T-15-70-1000 for temperatures up to 500ºC (increasing load)

From Table 7.8, the sensor sensitivity trends upward till 500oC, this is consistent with the observations in other sensors. The nonlinearity and resolution degrade beyond 400oC, as the leakage current increased.

Table 7.8 Sensor array performance of SiC-T-15-70-1000 at different

temperatures. Room 100 ºC 200 ºC 300 ºC 400ºC 500ºC temp Sensitivity 9.7E-03 9.6E-03 1.0E-02 1.4E-02 3.0E-02 3.2E-02 (fF/Pa) Nonlinearity* 2.6% 2.2% 2.8% 2.9% 4.4% 4.0% Resolution 0.3% 0.3% 0.5% 0.6% 0.7% 0.4% *linear range 2.8 MPa-6.9 MPa (400-1000psi); 3.4 - 6.9 MPa (500-1000psi) for over 400ºC

194

7.4.5.2 Testing of SiC-T-15-95-300 as a function of temperature

At temperatures up to 200oC, the linear range of the sensor spans 0.6 - 2.1 MPa

(90 - 300 psi) (Figs 7.48-7.50). The sensor behavior shows good repeatability and the sensitivity remains fairly constant.

40 1 30 2

20 3

0 Capacitancechange (pF) 0 0.5 1 1.5 2 2.5 -10 Pressure (MPa)

Figure 7.48 C vs. P plot for SiC-T-15-95-300 at room temperature (increasing load).

40 1 30 2 20 3

0 Capacitancechange (pF) -10 0 0.5 1 1.5 2 2.5

Pressure (MPa) Figure 7.49 C vs. P plot for SiC-T-15-95-300 at 100ºC (increasing load)

195

40 1 30 2 20 3

0 Capacitancechange (pF) 0 0.5 1 1.5 2 2.5 -10

Pressure (MPa) Figure 7.50 C vs. P plot for SiC-T-15-95-300 at 200ºC (increasing load).

From Fig. 7.51, we can see that at 500ºC , the linear range is from 0.8 - 2.1 MPa

(120 - 300 psi). Sensor repeatability at 500ºC degrades in comparison to performance at lower temperatures.

90 80 70 60 50 40 1 30 2 20 3 10 0 Capacitancechange (pF) -10 0.5 1 1.5 2 2.5 Pressure (MPa)

Figure 7.51 C vs. P plot for SiC-T-15-95-300 at 500ºC (increasing load).

At 550ºC , the sensor performance degrades further in both repeatability and linearity (Fig. 7.52).

196

120

100

60 1

40 2 3 20

Capacitancechange (pF) 0.5 1 1.5 2 2.5 -20 Pressure (MPa)

Figure 7.52 C vs. P plot for SiC-T-15-95-300 at 550ºC (increasing load).

Figure 7.53 plots the capacitance versus pressure for different temperatures. The temperature dependent base capacitance shift is caused by the increase in leakage current. The sensitivity also increases at a higher temperature.

3000

2500

2000 20ºC 1500 100ºC 200ºC 1000 500ºC

Capacitance(pF) 500 550ºC

0 0.5 1 1.5 2 2.5

Pressure (MPa) Figure 7.53 C vs. P plot for SiC-T-15-95-300 for temperatures up to 550ºC (increasing load).

197

Table 7.9 shows the sensitivity of this sensor at room temperature is 2.8E-2 fF/Pa

(0.19 pF/psi), which is almost three times that of the sensor SiC-T-15-70-1000. The larger radius (95 μm) directly contributes to improved sensitivity. It is also observed that the resolution is < 1% up to 200ºC , and < 2.5% at 500ºC and 550ºC .

Table 7.9 Performance of SiC-T-15-95-300 at different temperatures. Room 100ºC 200ºC 500ºC 550ºC temp Sensitivity 2.8E-02 2.9E-02 2.9E-02 6.4E-02 7.3E-02 (fF/Pa) Nonlinearity 3.5% 2.7% 2.6% 2.7% 4.6% Resolution 0.07% 0.1% 0.5% 2.5% 2.0%

198

7.5 Conclusion

A series of sensor arrays with different substrate materials, structure, and operating modes are characterized and compared in this chapter. The sensors exhibit high sensitivity, good repeatability and good linearity. It is shown that sensitivity and resolution changes when testing as a function of temperature are attributable to the leakage current increase at elevated temperature. For sensors with different sensing gaps, those with 0.5 μm gap were superior to those with 1.5 μm gap in both linearity and resolution. With respect to sensors fabricated on different substrate materials, comparable performance was observed at room temperature. This corresponded well with simulation results. Sensors with both SiC and Si substrates have been tested up to 500ºC with comparable results. Thus, SiC sensors on Si substrates may be a promising approach to realize relatively low cost sensors capable of operating at high temperatures. With respect to operating modes, contact mode sensors exhibited superior performance to small deflection mode sensors in terms of sensitivity, nonlinearity and resolution. The best sensing performance was obtained from

SiC-T-05-70-500, a sensor with a SiC substrate, contact mode operation and a 0.5 μm gap. The sensitivity, nonlinearity and resolution for this sensor were 2.2E-2 fF/Pa,

0.9%, 0.3%, respectively, at room temperature and 5.7E-2 fF/Pa, 2.0%, 0.8%, respectively, at 550ºC . The high temperature performance of the sensor may be further improved by improving the quality of the insulating layer to decrease the leakage current.

199

Chapter 8

CONCLUSION This thesis has advanced the state-of-the-art in silicon carbide capacitive pressure sensors, addressing issues related to the design, fabrication process, and metallization.

The generally excellent performance of these sensors demonstrates the potential of poly-SiC for high temperature applications.

FEA was employed to model the sensor and study the thermal mismatch stress effect on sensor behavior for Si substrates. The analysis showed that the effect of thermal expansion mismatch stress is small when Si substrates are used. Instead, the change in dielectric constant and leakage current as a function of temperature is the predominant cause of the change in base capacitance, a phenomenon independent of the substrate type. This temperature dependent capacitance shift was corroborated in measurements on sensors fabricated on both SiC and Si substrates.

High-temperature-capable Ohmic contacts of Ti/TaSi2/Pt to heavily-nitrogen- doped, n-type poly-SiC were studied in this work. The contacts show good behavior, both in the initial as-deposited state and following post-deposition annealing. The polycrystalline nature of the poly-SiC film, incorporating defects such a grain boundaries and surface roughness, is thought to be responsible for the as-deposited

Ohmic contact behavior.

Effects of different anneal temperatures and anneal times on the specific contact

200 resistance were also examined. In comparing a series of 30-minute anneals as a function of temperature, it was observed that the specific contact resistance decreased up to 600ºC anneal, but increased beyond 700ºC. Samples annealed at 600oC were then studied as a function of anneal times. The lowest specific contact resistance measured was approximately 410-6 Ω-cm2 on the samples that underwent 600ºC annealing for 45 minutes in nitrogen ambient. Glancing incidence x-ray diffraction analysis (incidence angle 1º) of the samples subjected to 30-minute anneals at temperatures up to 800ºC were performed. XRD spectra of samples annealed at 600ºC

and above showed diffraction peaks corresponding to the tantalum silicide (Ta5Si3) phase. According to AES depth profile study, the new phases formed at the interface of the three layers together with the grain growth of tantalum silicide may contribute to the specific contact resistance drop at 600ºC anneal. SEM analyses on samples detected obvious changes in surface morphology at anneal temperatures over 700ºC, which is believed to cause the specific contact resistance to increase at these temperatures.

Tantalum silicide, platinum silicide and titanium silicide appear to be the main compounds influencing the specific contact resistance following the anneal process.

The oxidation of platinum silicide forms a silicon dioxide passivation layer on the metal pad surface, which protects the layer underneath from further oxidation. Finally, the Ohmic contact successfully withstood 1000 hours at 550ºC in air, with specific contact resistance remaining stable in the range of 510-5 Ω-cm2. Capacitive sensors

201 incorporating the foregoing metallization scheme were tested up to 550 ºC. No evidence of delamination or metal degradation was observed.

Sensors with sensing capacitance gaps of 0.5 μm and 1.5 μm were designed with maximum pressure ranging from 2.1 MPa to 8.3 MPa (300 to 1200 psi) and then fabricated and subsequently tested to 550oC. The sensors demonstrated good repeatability, small hysteresis, low nonlinearity and high sensitivity. For example, a sensor designed for a 3.4 MPa (500 psi) range with 54 μm diaphragm radius and 1.5

μm gap showed 1.10×10-3 fF/Pa (7.6 fF/psi) sensitivity, 4.1% nonlinearity and 2.1% resolution. In comparison, a sensor for 3.4 Mpa (500 psi) range with 37 μm radius and

0.5 μm gap showed 1.15×10-3 fF/Pa (7.9 fF/psi) sensitivity, 2.2% nonlinearity and 1.3% resolution.

The contact mode pressure sensors demonstrated better sensitivity than their small displacement counterparts. The sensors on SiC substrates performed similar to those on Si substrates at both room temperature and 500ºC. The best performance from the fabricated designs was obtained from a SiC substrate contact mode sensor with 0.5 μm sensing gap. Thus, for SiC-T-05-70-500, a sensitivity of 5.7×10-2 fF/Pa

(390 fF/psi), nonlinearity of 2.0% and resolution 0.8% for 3.4 MPa (500 psi) range at

550 oC were achieved. This shows improved performances compared with 1.04×10-3 fF/Pa (7.2 fF/psi), 2.4% and 7%, respectively, at 574oC for a small deflection mode,

1.5 μm-gap sensor of previous work [6].

202

In summation, the above studies provide insightful information towards aiding the development of harsh environment-capable capacitive pressure sensors with good performance at low cost.

203

Appendix A

Definition of sensor parameters:

Sensitivity: It is the slope of the C vs P plot in linear range, with units of fF/Pa.

Nonlinearity: E Nonlinearity: Nonlinearity is calculated from

where ΔC+ and ΔC- are the maximum and minimum deviation from a linear fit

of the capacitance versus pressure plot. Cmax and Cmin are the maximum and

minimum capacitance over the operational range.

Hysteresis: It is the maximum difference in sensor output at a pressure when that

pressure is first approached with pressure increasing and then approached with

pressure decreasing during a full span pressure cycle. It is stated as less than x%

FS. It is caused by the natural reluctance of a pressure sensing material such as a

diaphragm to return to its original position, shape or form after being stressed.

Resolution: The minimum input pressure change that causes the output to change.

It can be derived from the minimum output change that can be distinguished by

the measurement electronics divided by the sensitivity of sensor array. The

measurement electronics by itself typically is capable of very high resolution (as

high as 1 ppm in the case of the Agilent E4980A LCZ meter used in these

experiments). However, the measurement setup itself always produces output

204 fluctuations due to factors such as temperature variation that degrade the obtainable resolution. The fluctuation in the output capacitance at full scale loading for a given test temperature was used to specify sensor resolution.

205

BIBLIOGRAPHY

[1] M. Mehregany, et al, "Silicon carbide MEMS for harsh environments," Proceedings of the IEEE, vol. 86, no.8, pp. 1594-1609, 1998.

[2] A. C. Patil, et al, "6H-SiC JFETs for 450C Differential Sensing Applications," Journal of Microelectromechanical Systems, vol. 18, no.4, pp. 950-961, 2009.

[3] I. P. Nikitina, et al, "Formation and role of graphite and nickel silicide in nickel based ohmic contacts to n-type silicon carbide," J. Appl. Phys., vol. 97, no.8, pp. 083709, 2005.

[4] R. S. Okojie, et al, "Reliability assessment of Ti/TaSi[sub 2]/Pt ohmic contacts on SiC after 1000 h at 600 [degree]C," J. Appl. Phys., vol. 91, no.10, pp. 6553-6559, 2002.

[5] P. G. Neudeck, et al, "Stable Electrical Operation of 6H–SiC JFETs and ICs for Thousands of Hours at 500 " Electron Device Letters, IEEE, vol. 29, no.5, pp. 456-459, 2008.

[6] L. Chen and M. Mehregany, "A silicon carbide capacitive pressure sensor for in-cylinder pressure measurement," Sensors and Actuators A: Physical, vol. 145-146, pp. 2-8, 2008.

[7] Mikhail E.fimovich Levinshtein, et al, "SiC," in Properties of Advanced Semiconductor Materials: GaN,AlN,InN,BN,SiC,SiGe ,1st ed.New York: Wiley-IEEE, 2001, pp. 93-110.

[8] M. Mehregany, et al, "Internal stress and elastic modulus measurements on micromachined 3C-SiC thin films," Electron Devices, IEEE Transactions on, vol. 44, no.1, pp. 74-79, 1997.

[9] N. S. Savkina, et al, "New results in sublimation growth of the SiC epilayers," Materials Science and Engineering B, vol. 61-62, pp. 165-167, 1999.

[10] A. A. Lebedev and V. E. Chelnokov, "Measurement of electrophysical properties of silicon carbide epitaxial films," Diamond and Related Materials, vol. 3, no.11-12, pp. 1393-1397, 1994.

[11] C. Hung Wu, et al, "Growth of polycrystalline SiC films on SiO2 and Si3N4 by APCVD," Thin Solid Films, vol. 355-356, pp. 179-183, 1999.

[12] Haixia Zhang, et al, "In-situ doped and laser annealing of PECVD SiC thin filnm," Proceedings of the 2nd IEEE International Conference on Nano/Micro Engineered and Molecular Systems, pp. 33-36, 2007.

206

[13] Hui Dong Tang, et al, "SiC Coatings Deposited by RF Magnetron Sputtering," Key Engineering Materials, vol. 280-283, no.High-Performance Ceramics III, pp. 1309-1312, 2005.

[14] M. Dubey and G. Singh, "Recrystallization of SiC thin films," J. Phys. D, vol. 7, no.11, pp. 1482, 1974.

[15] K. Wasa, et al, "Structure and mechanical properties of r.f. sputtered SiC films," Thin Solid Films, vol. 31, no.3, pp. 235-241, 1976.

[16] C. A. Zorman, et al, "Deposition of Polycrystalline 3C-SiC Films on 100 mm Diameter Si(100) Wafers in a Large-Volume LPCVD Furnace," Electrochemical and Solid-State Letters, vol. 5, no.10, pp. G99-G101, 2002.

[17] X. Fu, et al, "Polycrystalline 3C-SiC thin films deposited by dual precursor LPCVD for MEMS applications," Sensors and Actuators A: Physical, vol. 119, no.1, pp. 169-176, 2005.

[18] E. Hurtós and J. Rodríguez-Viejo, "Residual stress and texture in poly-SiC films grown by low-pressure organometallic chemical-vapor deposition," J. Appl. Phys., vol. 87, pp. 1748-1758, 2000.

[19] M. T. Clavaguera-Mora, et al, "Growth of SiC films obtained by LPCVD," Diamond and Related Materials, vol. 6, no.10, pp. 1306-1310, 1997.

[20] C. S. Roper, et al, "Stress control of polycrystalline 3C-SiC films in a large-scale LPCVD reactor using 1,3-disilabutane and dichlorosilane as precursors," J Micromech Microengineering, vol. 16, no.12, pp. 2736, 2006.

[21] N. Behnel, et al, "A new highly selective sacrificial layer technology for SiC MEMS," Transducers, vol. T1E, no.002, pp. 740-742, 2009.

[22] H.YIH P., et al, "A review of SiC reactive ion etching in fluorinated plasmas," no.1, pp. 605; 642-642,

[23] J. R. Flemish, et al, "Smooth etching of single crystal 6H-SiC in an electron cyclotron resonance plasma reactor," Appl. Phys. Lett., vol. 64, no.17, pp. 2315-2317, 1994.

[24] K. Xie, et al, "Low damage and residue-free dry etching of 6H--SiC using electron cyclotron resonance plasma," Appl. Phys. Lett., vol. 67, no.3, pp. 368-370, 1995.

[25] J. J. Wang, et al, "High rate etching of SiC and SiCN in NF3 inductively coupled plasmas," Solid-State Electronics, vol. 42, no.5, pp. 743-747, 1998.

207

[26] J. J. Wang, et al, "ICP etching of SiC," Solid-State Electronics, vol. 42, no.12, pp. 2283-2288, 1998.

[27] Laura J. Evans, et al, "New deep reactive ion etching process developed for the microfabrication of silicon carbide," Http://www. Grc. Nasa. Gov/ WWW/RT/ 2004/RI/ RIS-Evans. Html, vol. 2004, pp. 1,

[28] Zhigang Lin and Rick J. Yoon, "An AlN-based high temperature package for SiC devices: Materials and processing," in Proceedings of International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces, 2005, pp. 156-159.

[29] Philip G.Neudeck, et al, "High-temperature Electronics—A role for wide bandgap semiconductors?" in Proceedings of IEEE, 2002, pp. 1065-1076.

[30] F. Miyashiro, et al, "High thermal conductivity aluminum nitride ceramic substrates and packages," in IEEE Trans. Compon., Hybrids, Manuf. Technol., 1990, pp. 313-319.

[31] D. J. Young, et al, "High-temperature single-crystal 3C-SiC capacitive pressure sensor," Sensors Journal, IEEE, vol. 4, no.4, pp. 464-470, 2004.

[32] B. Diem, et al, "SOI 'SIMOX'; from bulk to surface micromachining, a new age for silicon sensors and actuators," Sensors and Actuators A: Physical, vol. 46, no.1-3, pp. 8-16, 1995.

[33] K. Petersen, et al, "Ultra-stable, high-temperature pressure sensors using silicon fusion bonding," Sensors and Actuators A: Physical, vol. 21, no.1-3, pp. 96-101, 1990.

[34] V. M. Stuchebnikov, "SOS strain gauge sensors for force and pressure transducers," Sensors and Actuators A: Physical, vol. 28, no.3, pp. 207-213, 1991.

[35] K. Kasten, et al, "CMOS-compatible capacitive high temperature pressure sensors," Sensors and Actuators A: Physical, vol. 85, no.1-3, pp. 147-152, 2000.

[36] Z. Yulong, et al, "A novel high temperature pressure sensor on the basis of SOI layers," Sensors and Actuators A: Physical, vol. 108, no.1-3, pp. 108-111, 2003.

[37] Shuwen Quo, et al, "High temperature high accuracy piezoresistive pressure sensor based on smart-cut soi," Micro Electro Mechanical Systems, 2008. MEMS 2008. IEEE 21st International Conference on, pp. 892-895,

[38] I. Ayerdi, et al, "High-temperature ceramic pressure sensor," Sensors and Actuators A: Physical, vol. 60, no.1-3, pp. 72-75, 1997.

208

[39] A. Dehe, et al, "A piezoresistive GaAs pressure sensor with GaAs/AlGaAs membrane technology," J Micromech Microengineering, vol. 5, no.2, pp. 139, 1995.

[40] K. Mutamba, et al, "A GaAs pressure sensor with frequency output based on resonant tunneling diodes," in IEEE Trans. Instrum. Meas., 1999, pp. 6-7.

[41] R. Gaska, et al, "Piezoresistive effect in metal--semiconductor--metal structures on p-type GaN," Appl. Phys. Lett., vol. 76, no.26, pp. 3956-3958, 2000.

[42] B. S. Kang, et al, "Capacitance pressure sensor based on GaN high-electron-mobility transistor-on-Si membrane," Appl. Phys. Lett., vol. 86, no.25, pp. 253502, 2005.

[43] Darrel R. Wur, et al, "Polycrystalline Diamond Pressure Sensor," Journal of Microelectromechanical Systems, vol. 4, no.1, pp. 34-41, 1995.

[44] J.L.Davidson, et al, "On the Fabrication and Behavior of Diamond Microelectromechanical Sensors," Diamond Materials V, vol. 97, no.32, pp. 635-651, 1998.

[45] K. C. Holmes, et al, "Diamond microelectromechanical sensors for pressure and acceleration sensing," Microelectromechanical Systems Conference, 2001, pp. 45-49, 2001.

[46] A. A. Ned, et al, "6H-SiC pressure sensor operation at 600C," High Temperature Electronics Conference, 1998. HITEC. 1998 Fourth International, pp. 257-260,

[47] e. a. Frederik Ceyssens, "An optical absolute pressure sensor for high-temperature applications, fabricated directly on a fiber," J Micromech Microengineering, vol. 19, no.11, pp. 115017, 2009.

[48] Michael A. Fonseca, et al, "Wireless Micromachined Ceramic Pressure Sensor for High-Temperature Applications," Journal of Microelectromechanical Systems, vol. 11, no.4, pp. 337-343, 2002.

[49] Li Chen. "Silicon carbide pressure sensors and infra-red emitters,"Ph.D dissertation,Case western reserve univ.,.,Cleveland,OH,2008

[50] Stephen P. Timoshenko, et al, "Large deflection of pates," in Theory of Plates and Shells ,1st ed., vol. 9, New york: McGraw-Hill book company, 1940, pp. 329-350.

[51] X. Fu, et al, "Measurement of residual stress and elastic modulus of polycrystalline 3C-SiC films deposited by low-pressure chemical vapor deposition," Thin Solid Films, vol. 492, no.1-2, pp. 195-202, 2005.

209

[52] S. Roy, et al, "The mechanical properties of polycrystalline 3C-SiC films grown on polysilicon substrates by atmospheric pressure chemical-vapor deposition," J. Appl. Phys., vol. 99, no.4, pp. 044108, 2006.

[53] S. P. Timoshenko, et al, "Theory of Plates and Shells (2nd Edition),"

[54] William P.Eaton, et al, "A new analytical solution for diaphragm deflection and its application to surface-micromachined pressure sensor," in International Conference on Modeling and Simulation of Microsystems, 1999, pp. 1-4.

[55] R. Schellin, et al, "Measurements of the Mechanical Behavior of Micromachined Silicon and Silicon-nitride Membranes for Microphones, Pressure Sensors, and Gas Flow Meters," Sensors and Actuators. A, vol. 41, no.1-3, pp. 287-292, 1994.

[56] Armin Bolz, et al, "Coating Cardiovascular Stents with a Semiconductor," Texas Heat Institute Journal, vol. 23, no.2, pp. 162-166, 1996.

[57] Z. Li and R. C. Bradt, "Thermal expansion of the cubic (3C) polytype of SiC," J. Mater. Sci., vol. 21, no.12, pp. 4366-4368, 1986.

[58] H. Watanabe, et al, "Linear Thermal Expansion Coefficient of Silicon from 293 to 1000 K," Int. J. Thermophys., vol. 25, no.1, pp. 221-236, 2004.

[59] Ting Zhang, et al, "Studies on Dielectric Properties of Silicon Nitride at High Temperature," Journal of Electronic Science and Technology of China, vol. 5, no.4, pp. 316-318, 2007.

[60] Logitech Ltd,"http://www.logitech.uk.com/index.asp"

[61] S. Jin, et al, "Ohmic contacts on n-type polycrystalline silicon carbide with Ti/TaSi2/Pt," in Transducer 2009 Denver, 2009, pp. 1083-1086.

[62] Denton Vacuum, LLC."http://www.dentonvacuum.com/"

[63] Basin Y.M., et al, "Phase equilibria in the Ni-Si-C system," Russ. Metall, vol. 4, pp. 197-200, 1988.

[64] T. Uemoto, "Reduction of Ohmic Contact Resistance on n-Type 6H-SiC by Heavy Doping," Japanese Journal of Applied Physics, vol. 34, no.2, pp. 7-9, 1995.

[65] J. Crofton, et al, "High‐temperature ohmic contact to n‐type 6H‐SiC using nickel," Journal of Applied Physics, vol. 77; 77, no.3, pp. 1317-1319, 1995.

210

[66] T. Marinova, et al, "Nickel based ohmic contacts on SiC," Materials Science and Engineering B, vol. 46, no.1-3, pp. 223-226, 1997.

[67] S. Y. Han, et al, "Ohmic contact formation mechanism of Ni on n-type 4H--SiC," Appl. Phys. Lett., vol. 79, no.12, pp. 1816-1818, 2001.

[68] C. Deeb and A. H. Heuer, "A low-temperature route to thermodynamically stable ohmic contacts to n-type 6H-SiC," Appl. Phys. Lett., vol. 84, no.7, pp. 1117-1119, 2004.

[69] F. Goesmann and R. Schmid-Fetzer, "Temperature-dependent interface reactions and electrical contact properties of titanium on 6H-SiC," Semiconductor Science and Technology, vol. 10, no.12, pp. 1652-1658, 1995.

[70] S. Gorsse and Y. Le Petitcorps, "A new approach in the understanding of the SiC/Ti reaction zone composition and morphology," Composites Part A: Applied Science and Manufacturing, vol. 29, no.9-10, pp. 1221-1227, 1998.

[71] F. La Via, et al, "Structural and electrical characterisation of titanium and nickel silicide contacts on silicon carbide," Microelectronic Engineering, vol. 60, no.1-2, pp. 269-282, 2002.

[72] U. Schmid, et al, "Temperature behavior of specific contact resistance and resistivity on nitrogen implanted 6H-SiC with titanium silicide ohmic contacts," J. Appl. Phys., vol. 85, no.5, pp. 2681-2686, 1999.

[73] A. K. Chaddha, et al, "Thermally stable, low specific resistance (1.3010-5 Ohmcm2) TiC Ohmic contacts to n-type 6Ha-SiC," Applied Physics Letters, vol. 66, no.6, pp. 760-762, 1995.

[74] P. Machac, et al, "Sputtering of Ni/Ti/SiC ohmic contacts," Microelectronic Engineering, vol. 85, no.10, pp. 2016-2018, 2008.

[75] Bohumil Barda, et al, "Comparison of Ni/Ti and Ni ohmic contacts on n -type 6H–SiC," J. Mater. Sci., vol. 19, no.11, pp. 1039-1044, 2008.

[76] S. Chang, et al, "Investigation of Au/Ti/Al ohmic contact to N-type 4H–SiC," Solid-State Electronics, vol. 49, no.12, pp. 1937-1941, 2005.

[77] J. Crofton, et al, "Contact resistance measurements on p-type 6H-SiC," Appl. Phys. Lett., vol. 62, no.4, pp. 384-386, 1993.

[78] R. Konishi, et al, "Development of Ni/Al and Ni/Ti/Al ohmic contact materials for p-type 4H-SiC," Materials Science and Engineering B, vol. 98, no.3, pp. 286-293, 2003.

[79] B. Pécz, et al, "Ti3SiC2 formed in annealed Al/Ti contacts to p-type SiC," Appl. Surf. Sci., vol. 206, no.1-4, pp. 8-11, 2003.

211

[80] A. J. Steckl, et al, "Ohmic and rectifying contacts to 3C–SiC using all-Ni technology," Silicon Carbide and Related Materials V-Inst. Phys. Conf. Ser. , vol. 137, pp. 653-656, 1994.

[81] H.J.Cho, et al, "Effect of reation products in monocrystalline beta-SiC/metal contact on contact resistivity," Silicon Carbide and Related Materials Conference-Institute of Physics Conference Series, vol. 137, pp. 663-665, 1993.

[82] C. Jacob, et al, "High temperature ohmic contacts to 3C–silicon carbide films," Solid-State Electronics, vol. 42, no.12, pp. 2329-2334, 1998.

[83] J. S. Chen, et al, "Contact resistivity of Re, Pt and Ta films on n-type β-SiC: Preliminary results," Materials Science and Engineering B, vol. 29, no.1-3, pp. 185-189, 1995.

[84] J. Crofton, et al, "The Physics of Ohmic Contacts to SiC," Physica Status Solidi (b), vol. 202, no.1, pp. 581-603, 1997.

[85] R. H. Cox and H. Strack, "Ohmic contacts for GaAs devices," Solid-State Electronics, vol. 10, no.12, pp. 1213-1214, IN7-IN8, 1215-1218, 1967.

[86] E. Kuphal, "Low resistance ohmic contacts to n- and p-InP," Solid-State Electronics, vol. 24, no.1, pp. 69-78, 1981.

[87] S. J. Proctor and L. W. Linholm, "A direct measurement of interfacial contact resistance," Electron Device Letters, IEEE, vol. 3, no.10, pp. 294-296, 1982.

[88] H. H. Berger, "Models for contacts to planar devices," Solid-State Electronics, vol. 15, no.2, pp. 145-158, 1972.

[89] G. K. Reeves, "Specific contact resistance using a circular transmission line model," Solid-State Electronics, vol. 23, no.5, pp. 487-490, 1980.

[90] Yu Suzuki, et al, "Evaluation of Specific Contact Resistance of Al, Ti, and Ni Contacts to N ion implanted 3C-SiC (100)," Materials Science and Forum, vol. 556-557, pp. 705-708, 2007.

[91] C. -. Ma, et al, "Residual stress measurement in textured thin film by grazing-incidence X-ray diffraction," Thin Solid Films, vol. 418, no.2, pp. 73-78, 2002.

[92] P. G. Datskos, et al, "Detection of infrared photons using the electronic stress in metal–semiconductor cantilever interfaces," Ultramicroscopy, vol. 82, no.1-4, pp. 49-56, 2000.

[93] J. Angilello, et al, "Observations of stresses in thin films of palladium and platinum silicides on silicon," J. Vac. Sci. Technol., vol. 17, no.1, pp. 471-475, 1980.

212

[94] K. K. Kolobova, "Some properties of silicon monoxide," Refractories and Industrial Ceramics, vol. 8, no.11, pp. 764-765, 1967.

[95] Robert S. Okojie, et al, "Stable Ti/TaSi2/Pt Ohmic Contacts on N-Type 6H-SiC Epilayer at 600C in Air," Materials Research Society Symposium Proceedings, vol. 622, pp. 1-7, 2000.

[96] L. Shuang, et al, "Formation of ultra-thin PtSi film by vacuum annealing," Vacuum, vol. 65, no.2, pp. 133-136, 2002.

[97] O. A. Fouad, et al, "Titanium disilicide formation by rf plasma enhanced chemical vapor deposition and film properties," Appl. Surf. Sci., vol. 206, no.1-4, pp. 159-166, 2003.

[98] G. Larrieu, et al, "Formation of platinum-based silicide contacts: Kinetics, stoichiometry, and current drive capabilities," J. Appl. Phys., vol. 94, no.12, pp. 7801-7810, 2003.

[99] P. I. Gaiduk and A. Nylandsted Larsen, "Platinum-silicide formation during rapid thermal annealing: Dependence on substrate orientation and pre-implanted impurities," Appl. Phys. A, vol. 53, no.2, pp. 168-171, 1991.

[100] Spectrum Semiconductor Materials, Inc."http://www.spectrum-semi.com/index.html"

[101] Cotronics Corporation,"http://www.cotronics.com/vo/cotr/"

[102] Aegis, Inc."http://aegis-inc.net/"

[103] Omega engineering, Inc."http://www.omega.com/"

[104] H. W. van Zeijl and L.K. Nanver, "Lpcvd silicon nitride-on-silicon spacer," in Microelectronics Techonology and Devices, 2005, pp. 153-162.

[105] Lee Stauffer, "Fundamentals of Semiconductor C-V Measurements," vol. 2008, pp. 2,2008.

213