DOCSLIB.ORG

Marcelo S. Cintra Phd Thesis

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Marcelo S. Cintra Phd Thesis UNIVERSITY OF CALIFORNIA, IRVINE Just-in-Time Compilation Techniques for Hardware/Software Co-Designed Processors DISSERTATION submitted in partial satisfaction of the requirements for the degree of DOCTOR OF PHILOSOPHY in Information and Computer Science by Marcelo Cintra Dissertation Committee: Professor Dr.Sc. Michael Franz, Chair Professor PhD. Harry Xu Professor PhD. Ian Harris 2015 © 2015 Marcelo Cintra DEDICATION To my beloved wife, Monique, and my beloved children, Sofia, Lucas Anthony and Benjamin. “Love, just like knowledge, is a treasure that the more we spread, the more we have.” Joanna de Ângelis ii TABLE OF CONTENTS Page LIST OF FIGURES vi LIST OF TABLES viii LIST OF LISTINGS ix ACKNOWLEDGMENTSx CURRICULUM VITAE xii ABSTRACT OF THE DISSERTATION xiv 1 Introduction1 1.1 Managed Programming Languages.......................3 1.2 Hardware/Software Co-Designed CPUs....................5 1.3 Problem Statement................................6 1.4 Thesis statement.................................7 1.5 Our Approach...................................8 1.6 Contributions...................................9 1.7 Thesis Organization............................... 11 2 Related Work 13 2.1 Virtual Machines................................. 14 2.2 Virtual Machine Services............................. 15 2.2.1 Mobile Code Security........................... 15 2.2.2 Garbage Collection............................ 16 2.2.3 Bytecode Emulation........................... 16 2.3 HW/SW Codesign Methodology......................... 19 2.3.1 HW/SW Co-design Advantages..................... 20 2.3.2 ISA Emulation.............................. 23 2.3.3 Dynamic Binary Translation....................... 24 2.4 HW/SW Co-Designed Processors........................ 25 2.4.1 Hardware Support in Co-Designed Processors............. 27 iii 3 Bytecode Acceleration Techniques 29 3.1 Bytecode Acceleration with AccelDroid..................... 29 3.2 AccelDroid Infrastructure............................ 32 3.2.1 OS Acceleration Driver.......................... 32 3.2.2 Modifications to the Android DVM................... 35 3.2.3 Bytecode Acceleration in the DBT.................... 37 3.3 Bytecode Optimizations............................. 39 3.3.1 Bytecode Interpretation with LINKPIPE................. 39 3.3.2 Bytecode Check with SPECULATION.................. 40 3.3.3 Bytecode Call and Return with FLOOK................. 42 3.3.4 Bytecode Register Promotion...................... 46 3.3.5 Optimizing 64-Bit Loads and Stores................... 48 3.4 Experiments.................................... 48 3.4.1 Programmability............................. 49 3.4.2 Porting the Dalvik Runtime into the Efficeon DBT........... 50 3.4.3 ISA Compatibility and Transparency.................. 50 3.4.4 CaffeineMark 3.0 Benchmark...................... 51 3.4.5 Overall Performance Benefits...................... 52 3.4.6 Bytecode-Specific Optimization Benefits................ 55 3.4.7 Direct Interpretation and LINKPIPE Benefits.............. 56 3.4.8 Energy Benefits.............................. 58 3.5 Conclusions.................................... 60 4 Evaluating Bytecode Performance and Energy Efficiency on Processor Simulators 62 4.1 Difficulties for Bytecode Energy/Performance Evaluation on Processor Sim- ulators....................................... 63 4.2 Motivation for a Virtualized Interface for Simulation Control......... 67 4.2.1 Cross-platform Benchmarking...................... 67 4.2.2 Controlling the Simulation on a Co-designed Processor........ 68 4.3 Benchmarking Using Special Markers..................... 69 4.3.1 API for Bytecode Instrumentation.................... 70 4.3.2 OS Simulation Control Driver...................... 70 4.3.3 Virtual Machine Modification...................... 72 4.3.4 Modifications to the Architecture Simulator.............. 75 4.3.5 Application Instrumentation....................... 76 4.4 Evaluation..................................... 78 4.4.1 Experiment Setup............................ 78 4.4.2 Workloads................................. 80 4.5 Related Work................................... 82 4.6 Conclusion and Future Work........................... 83 iv 5 Bytecode Acceleration in a Out-of-Order Co-Designed Processor 85 5.1 Motivation..................................... 86 5.2 Acceleration Interface Design.......................... 88 5.2.1 ISA-Compatibility............................. 88 5.2.2 Virtual Machine Simplicity and Flexibility............... 89 5.2.3 OS Transparency............................. 90 5.3 Programming for Acceleration.......................... 91 5.3.1 Virtual Machine.............................. 91 5.4 Internal Implementation for Acceleration.................... 93 5.4.1 Hardware Support for Acceleration Interface.............. 93 5.5 Uop Runtime................................... 94 5.5.1 Handle Multiple Virtual Machine Instances............... 96 5.5.2 Handle HW Interrupt and Exception.................. 96 5.5.3 Handle Non-Supported Instruction................... 97 5.5.4 Handle Floating Point Operations.................... 97 5.6 Experiment Setup................................. 98 5.7 Evaluation..................................... 103 5.7.1 Energy Consumption........................... 107 5.7.2 Startup Overhead Reduction....................... 107 5.8 Conclusion.................................... 108 6 Future Work 111 6.1 Promotion of Stack Variables to Registers.................... 111 6.2 Universal Acceleration Bytecode......................... 115 6.3 Fill the Dark Silicon with Specialized cores for Bytecode Acceleration.... 116 6.4 HW/SW Codesigned Security.......................... 116 7 Conclusion 118 7.1 Discussion..................................... 118 7.2 Limitations.................................... 121 7.3 A Final Word................................... 122 Bibliography 124 Appendices134 A Dalvik Virtual Machine.............................. 134 A.1 Dalvik Bytecodes............................. 134 A.2 Dalvik Interpreter............................. 138 A.3 Trace Based Just-in-Time compiler................... 139 B Tramseta Efficeon Processor........................... 140 B.1 Hardware Support for Speculative Execution............. 142 B.2 Bytecode Execution Time Breakdown.................. 143 B.3 Transmeta Code Morphing Software.................. 144 C Translation Example............................... 149 v LIST OF FIGURES Page 1.1 Modern CPU design...............................6 1.2 Bytecode Code Accelerator Design.......................8 2.1 Emulation Process................................ 24 3.1 The Benefit of Using AccelDroid for Bytecode Execution........... 30 3.2 Android Software Stack............................. 33 3.3 Flow Chart for the Acceleration Driver..................... 34 3.4 Bytecode Execution through a regular VM and through AccelDroid..... 38 3.5 Translation of Call/Return Instructions with FLOOK.............. 43 3.6 Speedup on CaffeineMark............................ 53 3.7 Acceldroid speedup on some popular algorithms................ 54 3.8 SPEC CPU 2000 Performance Comparison................... 55 3.9 CaffeineMark Performance Comparison..................... 55 3.10 Optimization Benefits.............................. 56 3.11 Interpretation Performance........................... 57 3.12 LINKPIPE Benefit................................. 58 3.13 Energy Savings without warmup overhead................... 59 3.14 Energy Savings including JIT warmup..................... 60 3.15 Performance Counters for the Energy Analysis of Figure 3.14 on page 60.. 61 4.1 Application source being compiled into different binaries for execution... 65 4.2 Simulation Control Interface on A HS/SW co-designed System........ 68 4.3 Flow Chart for the Simulation Driver...................... 71 4.4 Simulation Control Interface........................... 73 4.5 Application source compilation into binary and bytecode format....... 76 4.6 Application Instrumentation and Simulation Control............. 79 4.7 Execution overhead for CaffeineMark with bytecode marker......... 81 4.8 Bytecode vs. Native Execution for CaffeineMark................ 82 5.1 Accelerated Bytecode Execution......................... 89 5.2 Flow Chart for Trap Handling in Uop Runtime................. 95 5.3 CaffeineMark Performance............................ 104 5.4 Instruction Reduction............................... 105 5.5 Allocation Stalls.................................. 106 vi 5.6 AndEBench and 0xBench Performance..................... 107 5.7 CaffeineMark Energy Consumption....................... 108 5.8 AndEBench and 0xBench Energy Consumption................ 109 5.9 Startup Overhead Reduction........................... 110 1 Stack layout of a method with 2 parameters and 3 local variables....... 136 2 Stack layout of a method nonInlineableSeries.................. 137 3 Efficeon Processor Package and Die Area.................... 142 4 Interpretation and profiling of x86 Instructions................ 145 5 Translation of x86 Instructions......................... 146 6 Chaining X86 Translations............................ 146 7 Speculative Support for Agressive Optimizations................ 147 vii LIST OF TABLES Page 3.1 Processor Specifications............................. 54 4.1 Percentage of Dynamic Code Execution on Android Benchmarks....... 81 5.1 Important Microarchitecture Parameters.................... 99 5.2 Hardware Acceleration Support......................... 99 1 Execution Time Breakdown for DaCapo and Spec 2000...........
Load more

Recommended publications
  • SIMD Extensions
    SIMD Extensions PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 12 May 2012 17:14:46 UTC Contents Articles SIMD 1 MMX (instruction set) 6 3DNow! 8 Streaming SIMD Extensions 12 SSE2 16 SSE3 18 SSSE3 20 SSE4 22 SSE5 26 Advanced Vector Extensions 28 CVT16 instruction set 31 XOP instruction set 31 References Article Sources and Contributors 33 Image Sources, Licenses and Contributors 34 Article Licenses License 35 SIMD 1 SIMD Single instruction Multiple instruction Single data SISD MISD Multiple data SIMD MIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously. Thus, such machines exploit data level parallelism. History The first use of SIMD instructions was in vector supercomputers of the early 1970s such as the CDC Star-100 and the Texas Instruments ASC, which could operate on a vector of data with a single instruction. Vector processing was especially popularized by Cray in the 1970s and 1980s. Vector-processing architectures are now considered separate from SIMD machines, based on the fact that vector machines processed the vectors one word at a time through pipelined processors (though still based on a single instruction), whereas modern SIMD machines process all elements of the vector simultaneously.[1] The first era of modern SIMD machines was characterized by massively parallel processing-style supercomputers such as the Thinking Machines CM-1 and CM-2. These machines had many limited-functionality processors that would work in parallel.
    [Show full text]
  • Analysis and Comparison of Different Microprocessors Used in Computer
    Analysis and Comparison of Different Microprocessors used in Computer Architecture Manoj Gyanani Computer Science Department San Jose State University San Jose, CA 95192 408-455-4128 [email protected] ABSTRACT low level activities. It mainly performs the task of uploading, In the current world, it’s almost impossible to imagine that someone downloading and recalling data into and from the memory card. can live without computers. Computers have become an electronic Apart from that it also does complex mathematical calculations device of almost every day use for individuals of every age. we within a single command. cannot imagine of advancements without computers. Hence it becomes very important to understand the principal running entity of 2.2 Reduced Instruction Set Microprocessor the computer architecture. The microprocessor is the brain of a This processor is also called as RISC. These kinds of chips are made computer. it is a multipurpose, programmable device that according to the function in which the microprocessor can carry out accepts digital data as input, processes it according to instructions small things within a particular command. In this way it completes stored in its memory, and provides results as output. Hence, it is more commands at a faster rate. significant to analyze various processors and then compare them. So that we can know about pros and cons of different processors. We 2.3 Superscalar Processors have to select the best microprocessor and for that , it is really This is a processor that copies the hardware on the microprocessor important to analyze & make a comparison among them. Parameters for performing numerous tasks at a time.
    [Show full text]
  • Evolution Des X86befehlssatzes Und Seiner Erweiterungen
    Technische Universität Dresden Evolution des x86-Befehlssatzes und seiner Erweiterungen Peter Ebert Dresden, 15.07.2009 Einführung · Überblick & Historie · Konkurrierende Befehlssatzarchitekture n · Befehlsarten · Registerstruktur · x87 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 2/24 Übersicht & Historie · IBM 1981: erster PC · x86-Architektur verwendet einen CISC-Befehlssatz · alle Prozessoren seit dem Pentium Pro sind aber hybride CISC/RISC-Prozessoren 1978 1. Gen.: 8086 1982 2. Gen.: 80286 1985 3. Gen.: 80386 IA-32 1989 4. Gen.: 80486 1993 5. Gen.: Pentium MMX 1995 6. Gen.: P2, P3 3DNow!, SSE 1999 7. Gen.: Athlon (XP), P4 SSE2 2003 8. Gen.: Opteron x86-64 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 3/24 Konkurrierende Befehlssatzarchitekturen · ARM (Acorn Risc Machine) RISC-Architektur 1983 vom englischen Computerhersteller Acorn. Einsatz vor allem im eingebetteten Bereich z.B.: Mobiltelefonen, PDAs, Routern, iPod, iPhone, Internet Tablets von Nokia und den neueren PDAs von ASUS, Konsolen wie der Nintendo DS, der GP2X und die Pandora. · PowerPC (Performance optimization with enhanced RISC Performance Chip) 1991 durch ein Konsortium aus Apple, IBM und Motorola. z.B.: Nintendo GameCube und Wii, Xbox 360 von Microsoft, Playstation 3 von Sony und in vielen eingebetteten Systemen. Auch benutzen PKW und Produkte in der Luft- und Raumfahrt · SPARC (Scalable Processor ARChitecture) Von Sun Microsystems entwickelt ab 1985 und vermarktete ab 1987, offene Architektur, 1995 64-Bit-Erweiterung (UltraSparc) 15.07.2009 Evolution des x86-Befehlssatzes und seiner Erweiterungen 4/24 Befehlsarten · Transferbefehlen werden Daten innerhalb des Systems bewegt. Die Daten werden dabei nur kopiert, d. h. bleiben an ihrem Quellort unverändert.
    [Show full text]
  • O Společnosti Transmeta
    O společnosti Transmeta Společnost Transmeta byla založena roku 1995 pro návrh a vývoj vysoce efektivních procesorů, kompatibilních s procesory x86. Cílem Transmety je produkovat procesory s nízkým příkonem, vysokým výkonem, nízkou cenou a malou velikostí. První rodina procesorů Crusoe byla oznámena v roce 2000, další novou rodinou jsou procesory Efficeon vyvíjené od roku 2003. Transmeta je společnost s přibližně 300 zaměstnanci sídlící v Kalifornii a po celém světě. Prodej a servis je lokalizován především ve Spojených státech, Japonsku a Tchaj-wanu. 25. 4. 2005/MA/1 Technologie LongRun Při snaze snižovat rozměry tranzistorů narůstá problém se zvyšujícími se svodovými proudy tranzistorů. Průmysloví experti upozorňují na tento jev v souvislosti s Moorovými zákony, kdy při snižování rozměrů tranzistorů na 90nm až 65nm výrazně převládá jev svodových proudů nad klidovým proudem v pohotovostním režimu. Pokročilá technologie firmy Transmeta vylepšuje vlastnosti polovodičových prvků redukováním celkového příkonu, snižováním příkonu pohotovostního režimu, potenciálním zlepšením čipového výkonu a snížením výrobních nákladů. LongRun2 technologie se opírá o první generaci LongRun, která dynamicky přizpůsobuje kmitočet a napětí stokrát za sekundu. Tím dochází ke snížení příkonu. Technologie LongRun2 využívá nový inovovaný přístup k dynamickému nastavování prahu napětí k řízení tranzistorového svodu. Dynamické řízení snižuje svod způsobený změnami v rutinních podmínkách, jako je napětí a teplota, které nejsou při výrobě čipu předem známy. 25. 4. 2005/MA/2 Představení procesorů Efficeon od firmy Transmeta Procesory Transmeta zavádějí nový směr v oblasti mobilních počítačů - kompatibilitu, výkon a nízkou spotřebu. Pro Transmetu pracují nadšení vývojáři, kteří vytvářejí aplikace a platformy využívající nové technologie. S procesory Transmeta Crusoe a Efficeon se předpovídá nový pohled na mobilní technologie.
    [Show full text]
  • Transmeta Efficeon
    Transmeta Efficeon Rogério Alves Cardoso Institute of Computing UNICAMP Transmeta Efficeon 1 Tecnologia da Transmeta Baixo + CMS = Consumo VLIW Hardware Code Morphing Software Compatibilidade ● ● Very Long Instruction Word Provê compatibilidade x86 Processor ●Traduz instruções x86 para ●Simples e Rápido (?) operações VLIW equivalentes. ● Poucos Transistores ●Aprende e Melhora com o Bom tempo Desempenho Transmeta Efficeon 2 Hierarquia Processador/Software Aplicações x86 Software x86 Sistemas Operacionais x86 (Linux, Windows, etc.) Hardware BIOS x86 Drivers Code Morphing Software Efficeon TM8300/8600 Processador VLIW Hardware Transmeta Efficeon 3 Características do Efficeon ● VLIW: Até 8 operações e modificadores; ● Unidades Funcionais: ALUs, memória, FP/media, branch; ● Registradores: 64 GPRs, 64 FPRs, 4 dedicados ao conjunto x86, Shadow Registers; ● Poucos interlocks: CMS evita os hazards; ● Semântica compatível com x86: modos de endereçamento, tipos de dados, condition codes, partial word operations. Transmeta Efficeon 4 Outras Características ● Suporte a instruções multimídia (SSE, SSE2 e MMX); ● Interface Northbridge; ● Interface gráfica AGP; ● Tecnologia HyperTransportTM; ● Tecnologia LongRun2; ● Cache de Dados (L1 64KB e L2 512KB/1MB*) e de Instruções (L1 64KB e L2 512KB/1MB*) separadas. Transmeta Efficeon 5 Diagrama de Blocos do Efficeon Transmeta Efficeon 6 Diagrama de Blocos do Efficeon Transmeta Efficeon 7 VLIW ● O Efficeon é um processador VLIW; ● Uma instrução VLIW é chamada de molécula ● Cada molécula pode conter até 8 instruções chamadas de átomos (RISC-like operations). ● Uma molécula pode ter uma largura de até 256 bits. Transmeta Efficeon 8 Características VLIW ● O Efficeon é um processador VLIW; ● Uma instrução VLIW é chamada de molécula ● Cada molécula pode conter até 8 instruções chamadas de átomos. ● Uma molécula pode ter uma largura de até 256 bits.
    [Show full text]
  • Processor Microarchitecture an Implementation Perspective Ii
    Processor Microarchitecture An Implementation Perspective ii SynthesisChapter Lectures Title on here Computer ArchitectureKratos Editor Mark D. Hill, University of Wisconsin Synthesis Lectures on Computer Architecture publishes 50- to 100-page publications on topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. The scope will largely follow the purview of premier computer architecture conferences, such as ISCA, HPCA, MICRO, and ASPLOS. Processor Microarchitecture: An Implementation Perspective Antonio González, Fernando Latorre, and Grigorios Magklis 2011 Transactional Memory, 2nd edition Tim Harris, James Larus, and Ravi Rajwar 2010 Computer Architecture Performance Evaluation Models Lieven Eeckhout 2010 Introduction to Reconfigurable Supercomputing Marco Lanzagorta, Stephen Bique, and Robert Rosenberg 2009 On-Chip Networks Natalie Enright Jerger and Li-Shiuan Peh 2009 iii The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It Bruce Jacob 2009 Fault Tolerant Computer Architecture Daniel J. Sorin 2009 The Datacenter as a Computer: An Introduction to the Design of Warehouse-Scale Machines Luiz André Barroso and Urs Hölzle 2009 Computer Architecture Techniques for Power-Efficiency Stefanos Kaxiras and Margaret Martonosi 2008 Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency Kunle Olukotun, Lance Hammond, and James Laudon 2007 Transactional Memory James R. Larus and Ravi Rajwar 2006 Quantum Computing for Computer Architects Tzvetan S. Metodi and Frederic T. Chong 2006 Copyright © 2011 by Morgan & Claypool All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations in printed reviews, without the prior permission of the publisher.
    [Show full text]
  • Mobile Processors
    Mobile Processors Jose R. Ortiz Ubarri Electrical and Computer Engineering Department University of Puerto Rico, Mayagüez Campus Mayagüez, Puerto Rico 00681-5000 [email protected] Introduction ● While the wireless technology advances, the necessity and demand for more functional mobile devices that can work together with the available wireless technology have increased. ● Vendors have had to design mobile chips to minimize power consumption, both to make batteries to last longer and to prevent heat buildup in devices that lack space for fans and other cooling systems. ● In the past mobile processor could afford to run at no more than 30 MHz for PalmOS PDAs, 80 MHz for cellular phones, and 200MHz for devices that run Microsoft©s Pocket PC OS Mobile Processor Challenges ● Processor designers have to increase the processing power of the microprocessors, increase the speed to cope with the high volume of data, while keeping low the heat generation and minimizing the power consumption. ● The big problem here is that we want our mobile devices to run all day without require a recharge, but we also want performance. And performance requires power, which drains the mobile batteries. Lowering Power Consumption ● Designers can reduce the power consumption and heat generation by lowering the operating voltage at which the chips run, minimizing capacitance, and using sophisticated software and hardware power schemes designed to limit the power consumption for the execution of an instruction strictly to the electronic components (gates) that contribute to the execution of the instruction System on Chip ● Important companies in the mobile processor marketing such as ARM, IBM, Intel, or Texas Instruments are integrating many system functions on a single chip.
    [Show full text]
  • Transmeta Efficeon TM8820 Processor Interconnect, Andanagp 4Xgraphics Interface
    Transmeta™ Efficeon™ TM8820 Processor The Transmeta Efficeon TM8820 Lead-Free Packaging processor delivers high-performance x86-compatible processing for low The Efficeon TM8820 processor is Transmeta’s first Lead-Free Packaging processor to be developed in power applications. It is available in accordance with industrywide initiatives. By adhering to the a smaller 21mm x 21mm package Restriction of Hazardous Substances (RoHS) and Waste and is built upon Fujitsu’s Electronic Equipment (WEEE) initiatives, Transmeta has next-generation 90nm silicon Efficeon TM8820 Processor removed lead and other hazardous materials from processor technology using a state of the art packaging. Transmeta’s adherence to environmental manufacturing process that can produce industry-leading packaging also meets the Lead-Free Packaging standards transistors with a 40nm gate length. This advanced transistor requirements for consumer electronic devices put forth by technology yields higher frequencies and performance with the Japanese legislation and the European Union (EU). lower power requirements for cooler, fanless operation. The Efficeon processor features a 256-bit wide VLIW engine Reduced Package Size that can issue up to 8 instructions per clock cycle, a large 1 MB Streaming SIMD Extensions (SSE3) The new Efficeon TM8820 processor further increases board L2 cache, and support for MMX, SSE, SSE2 and SSE3 space by reducing the package size to a smaller 21mm x instructions for a powerful multimedia experience. It combines 21mm form factor — a savings of 48 percent! This smaller both processor and Northbridge functionality into a single package provides system designers with significantly more integrated circuit, creating a single package that reduces board flexibility when designing new and innovative thin-and-light space by eliminating the need for a dedicated Northbridge notebooks, Ultra Personal Computers (UPC) and small form chip.
    [Show full text]
  • Transmeta™ Efficeon™ TM8300 Processor
    Product Sheet Transmeta™ Efficeon™ TM8300 Processor The Transmeta Efficeon TM8300 processor is designed to address the ever-growing demand for x86 processing in value driven and energy conscious systems. Based upon a highly energy efficient design, the Efficeon TM8300 processor supports Transmeta's LongRun power and thermal management technology and fully integrated Northbridge functionality. The I/O interfaces built into the Efficeon processor's integrated Northbridge are matched with its high performance core, featuring support for DDR-400 memory, a 1.6 GB/s HyperTransport™ interconnect, and an AGP 4X graphics interface. With the new Code Morphing Software for the Efficeon processor, Transmeta extends its leadership in power management, offering a solution that provides high performance while consuming less power for the same work. To maximize performance and responsiveness, the Efficeon TM8300 processor is based upon the same architecture and feature of the Efficeon TM8600 processor. Featuring a 256-bit wide VLIW engine that can execute up to 8 instructions per clock cycle, a 512KB L2 cache, and support for SSE & SSE2 instructions, the Efficeon TM8300 processor provides for a rich and compelling multimedia experience. The result is a highly efficient x86 solution suitable for advanced web tablets, point of sale terminals (POS), high-end thin clients, notebooks and many other applications where an integrated, low power x86 processor is desirable. HIGHLY INTEGRATED ARCHITECTURE ENERGY EFFICIENT DESIGN Fully Integrated Northbridge Core
    [Show full text]
  • Introducing the Transmeta Efficeon TM8000 Microprocessor Family
    Introducing the Transmeta Efficeon TM8000 Microprocessor Family Matthew R. Perry, Ph.D. President and Chief Executive Officer David R. Ditzel Co-Founder, Vice-Chairman and CTO October 14 ,2003 Transmeta Corporation Page 1 October 14, 2003 How Crusoe Changed the Industry "Until Transmeta released the Crusoe processor in 2000, the mobile computer market was stagnating with repurposed desktop technology, oversized and overweight hardware, and disappointing growth. Crusoe showed the computer industry what was possible…” Rob Enderle, emerging technology expert for the Enderle Group Transmeta Corporation Page 2 October 14, 2003 Notebook Computer Market Evolution 12 10 lbs. 9.8 lbs. 10 Compaq Toshiba 9.0 lbs. LTE-286 T4500C Panasonic CF-41 8 7.0 lbs. Compaq Presario 6 5.5 lbs. Fujitsu Lifebook 3.3 lbs. Fujitsu 4 Loox-T 2.4 lbs. Toshiba Number of Pounds Number Libretto 1.8 lbs. 2 Sony 0.9 lbs. Vaio U OQO 0 1990 1992 1994 1996 1998 2000 2001 2002 2003 Year of Introduction Transmeta Corporation Page 3 October 14, 2003 Crusoe Was Adopted by Mobile PC Leaders Crusoe was used by 6 of top 10 worldwide leaders! Transmeta Corporation Page 4 October 14, 2003 Efficient Computing Transmeta Is A Leading Provider of Efficient Computing Processors Transmeta Corporation Page 5 October 14, 2003 Based on Transmeta’s Unique Approach Transmeta Corporation Page 6 October 14, 2003 Transmeta Corporation Page 7 October 14, 2003 Transmeta Corporation Page 8 October 14, 2003 Performance Efficient MoreMore WorkWork PerPer GHzGHz plusplus MoreMore GHzGHz Transmeta Corporation
    [Show full text]
  • Transmeta Efficeon Processor
    TM TM Product Brief Transmeta Effi ceon Processor The Transmeta Effi ceon™ x86 compatible processor ushers in a new era of energy effi cient computing. The processor was designed from the start to address the ever-growing demand for power-effi cient x86 solutions. To maximize performance and responsiveness, the Effi ceon processor features a 256-bit wide VLIW engine that can issue up to 8 instructions per clock cycle, a large 1 MB L2 cache, and support for SSE & SSE2 instructions for a compelling multimedia experience. The I/O features built into the Effi ceon processor’s integrated northbridge were selected to provide the highest system performance. These new I/O interfaces include support for DDR 400 DRAM, a 1.6 GB/s HyperTransport™ interconnect, and an AGP 4X graphics interface. With the new Code Morphing™ Software for the Effi ceon processor, Transmeta extends its leadership in power management by offering a solution that provides high performance while consuming less power for the same work. The result is a highly effi cient x86 solution suitable for notebook computers, Tablet PC’s and many other applications where an integrated, low power x86 processor is desirable. HIGH PERFORMANCE 8 Instruction Issue, 256-Bit VLIW Engine Advanced Code Morphing Software • Fully x86 compatible (P4-ISA) • Improves performance and responsiveness over 1st • Up to eight instructions issued per clock cycle generation Transmeta Crusoe technology • Up to 50% improvement in integer applications • New generation Code Morphing Software technology • SSE and SSE2 multimedia
    [Show full text]
  • Transmeta™ Efficeon™ TM8300/TM8600 Processor
    Efficeon Processor Product Brief Transmeta™ Efficeon™ TM8300/TM8600 Processor EfficeonTM Processor Model TM8300/TM8600 Features • Advanced 256-bit VLIW processor / Code Morphing™ software x86-compatible mobile platform solution • Leading edge 0.13µm fabrication technology for GHz performance at very low power levels • Standard product speeds of 900 MHz - 1.1 GHz at low power consumption • 128 KByte L1 instruction cache, 64 KByte L1 data cache, and 512 KByte (TM8300) or 1024 KByte (TM8600) L2 write-back cache for high performance • SSE, SSE2, and MMX instruction support for cinematic multimedia performance • Integrated northbridge core logic features facilitate compact system designs - DDR memory controller with 100-166 MHz, 2.5 V interface - AGP 1x/2x/4x 1.5 V graphics interface - HyperTransport™ 400 MHz 1.2 V southbridge interface • Enhanced LongRun™ Dynamic Power Management - Enables longer battery life by dynamically adjusting operating frequency and voltage to match the performance requirements of application workloads - Provides higher performance within smaller, thermally constrained environments • Enhanced LongRun Thermal Management - Maximizes performance within a thermal envelope - Low thermal characteristics enable fanless designs for quieter and more reliable systems • Full system management mode (SMM) support • Compact 783-contact organic BGA package with 1 mm ball pitch The Efficeon TM8300/TM8600 processor is a high-performance and low-power microprocessor, based on an advanced next-generation VLIW core architecture. When
    [Show full text]