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Transmeta Efficeon Transmeta Efficeon Rogério Alves Cardoso Institute of Computing UNICAMP Transmeta Efficeon 1 Tecnologia da Transmeta Baixo + CMS = Consumo VLIW Hardware Code Morphing Software Compatibilidade ● ● Very Long Instruction Word Provê compatibilidade x86 Processor ●Traduz instruções x86 para ●Simples e Rápido (?) operações VLIW equivalentes. ● Poucos Transistores ●Aprende e Melhora com o Bom tempo Desempenho Transmeta Efficeon 2 Hierarquia Processador/Software Aplicações x86 Software x86 Sistemas Operacionais x86 (Linux, Windows, etc.) Hardware BIOS x86 Drivers Code Morphing Software Efficeon TM8300/8600 Processador VLIW Hardware Transmeta Efficeon 3 Características do Efficeon ● VLIW: Até 8 operações e modificadores; ● Unidades Funcionais: ALUs, memória, FP/media, branch; ● Registradores: 64 GPRs, 64 FPRs, 4 dedicados ao conjunto x86, Shadow Registers; ● Poucos interlocks: CMS evita os hazards; ● Semântica compatível com x86: modos de endereçamento, tipos de dados, condition codes, partial word operations. Transmeta Efficeon 4 Outras Características ● Suporte a instruções multimídia (SSE, SSE2 e MMX); ● Interface Northbridge; ● Interface gráfica AGP; ● Tecnologia HyperTransportTM; ● Tecnologia LongRun2; ● Cache de Dados (L1 64KB e L2 512KB/1MB*) e de Instruções (L1 64KB e L2 512KB/1MB*) separadas. Transmeta Efficeon 5 Diagrama de Blocos do Efficeon Transmeta Efficeon 6 Diagrama de Blocos do Efficeon Transmeta Efficeon 7 VLIW ● O Efficeon é um processador VLIW; ● Uma instrução VLIW é chamada de molécula ● Cada molécula pode conter até 8 instruções chamadas de átomos (RISC-like operations). ● Uma molécula pode ter uma largura de até 256 bits. Transmeta Efficeon 8 Características VLIW ● O Efficeon é um processador VLIW; ● Uma instrução VLIW é chamada de molécula ● Cada molécula pode conter até 8 instruções chamadas de átomos. ● Uma molécula pode ter uma largura de até 256 bits. ● 2x mais que o seu antecessor o Crusoe. Mais ILP? Transmeta Efficeon 9 Mais ILP? Transmeta Efficeon 10 Diagrama VLIW O Efficeon é capaz de emitir de uma a oito instruções (átomos) por ciclo de clock 256 bits átomo 1 átomo 2 átomo 3 átomo 4 átomo 5 átomo 6 átomo 7 átomo 8 load/store ou load/store ou ALU-1 Inteiro ALU-2 Inteiro Alias Controle 32 bits add 32 bits add FP/MMX/SSE/ FP/MMX/SSE/ Branch Exec 1 Exec 2 SSE2 SSE2 Transmeta Efficeon 11 Diagrama VLIW O CMS é responsável por converter uma instrução x86 em uma instrução VLIW. A microarquitetura é transparente para o programador 256 bits átomo 1 átomo 2 átomo 3 átomo 4 átomo 5 átomo 6 átomo 7 átomo 8 load/store ou load/store ou ALU-1 Inteiro ALU-2 Inteiro Alias Controle 32 bits add 32 bits add FP/MMX/SSE/ FP/MMX/SSE/ Branch Exec 1 Exec 2 SSE2 SSE2 Transmeta Efficeon 12 Pipeline VLIW Transmeta Efficeon 13 Pipeline VLIW Transmeta Efficeon 14 CMS (Code Morphing Software) ● O CMS provê uma camada com uma implementação completa e compatível da arquitetura x86 em um processador VLIW: ● Todas as instruções alvos (incluindo CMS ● memory mapped I/O; ● Todos os registradores da arquitetura; SO Apps ● Comportamento de exceções compatíveis. ● Não assume qualquer SO ou assistência BIOS ● Vê somente código (instruções e páginas) Transmeta Efficeon 15 CMS (Code Morphing Software) Transmeta Efficeon 16 CMS (Code Morphing Software) Transmeta Efficeon 17 CMS (Code Morphing Software) Transmeta Efficeon 18 CMS (Code Morphing Software) Transmeta Efficeon 19 CMS (Code Morphing Software) ● Efetua a tradução dinâmica de um binário x86 em código nativo VLIW via software em tempo de execução ● As traduções são armazenadas em uma “Translation Cache” evitando o overhead de repetidas execuções; ● Completamente transparente para o sistema operacional; ● O CMS utiliza um esquema de interpretação e tradução dinâmica de binários para emular o código x86; Transmeta Efficeon 20 CMS Interpretação e Tradução Transmeta Efficeon 21 CMS Interpretação e Tradução Transmeta Efficeon 22 CMS Interpretação e Tradução Transmeta Efficeon 23 CMS Interpretação e Tradução Transmeta Efficeon 24 CMS Interpretação e Tradução Transmeta Efficeon 25 CMS Construção de Regiões ● No Efficeon as regiões grandes são construídas entre o commit e o rollback do bloco; ● Essas regiões ou blocos podem conter até 100 instruções x86; ● É feita bastante especulação na construção da região de forma a preencher os átomos do VLIW com o máximo de instruções possíveis. Transmeta Efficeon 26 CMS (Code Morphing Software) ● Moléculas explicitamente codificam o paralelismo em nível de instrução, permitindo a execução em um simples VLIW ● O Hardware não precisa realizar reordenações complexas de instruções ● Atualizações no processador são simplificadas ● Não existe necessidade de recompilar o programa ● O CMS pode ser atualizado de forma independente em uma flash ROM Transmeta Efficeon 27 CMS (Code Morphing Software) ● Um frontend decodifica uma instrução x86 em uma simples sequencia de átomos (RISC-like ops) ● Um otimizador aplica otimizações bem conhecidas ● incluindo eliminação de átomos desnecessários ● O scheduller reordena os átomos e os grupos em moléculas Transmeta Efficeon 28 CMS (Code Morphing Software) Transmeta Efficeon 29 Otimização de código ● O otimizador examina toda a tradução ● O CMS instrumenta o código para ajudar a determinar padrões de uso (# de vezes executado) ● O nível de otimização aplicado é escolhido baseado em heurísticas ● Quanto mais a tradução é executada mais ela é otimizada ● Se a inspeção indica que as otimizações são muito agressivas, algumas otimizações são removidas Transmeta Efficeon 30 Otimização de código ● Aggressive scheduling of instruction level parallelism for 8-wide VLIW ● Out-of-Order Execution on In-Order Hardware ● Critical path height reduction ● Common sub-expression elimination ● Software register renaming to avoid false dependencies ● Fusing operations ● Dead code elimination ● Removal of conditional branches ● Adaptive re-translation during program execution ● Loop unrolling and optimization ● Remove Exit Branches ● Code motion across back-edge ● Loop invariant code motion ● Strength reduction Transmeta Efficeon 31 Suporte em hardware ● Atribuição explicita de condition codes ● O Efficeon utiliza registradores específicos para emular o conjunto de condition codes do processador (o sufixo .c é utilizado para indicar que o condition code deve ser setado) ● Todos os registradores que mantém estados x86 são “shadowed” ● Uma operação de commit copia o estado ativo para os shadow registers ● Gated store buffers para escritas em memória ● Alias hardware para permitir ordenação de instruções (load after stores) ● Memory Mapped I/O ● Translated bit em páginas para detectar self-modifyng code ● Predição de saltos indiretos Transmeta Efficeon 32 Shadow Registers ● 64 registradores de inteiros de 32 bits (48 shadow register), 64 registradores de 80 bits de ponto flutuante(48 shadow registers) e 4 registradores de predicado (4 shadow registers) ● Se uma execução chega ao final de um bloco de tradução é feito um commit: ● Copia de todos os working registers para os shadow registers ● Se qualquer condição excepcional ocorrer dentro do bloco de tradução é feito um rollback: ● Copia de todos os registradores shadow de volta para os working registers Transmeta Efficeon 33 Suporte para commit/rollback ● Um store buffer/write queue de 14 entradas ● Uma victim cache com 32 entradas ● Suporte a store especulativo na cache de dados ● 4 Write combiners de 32 bits Transmeta Efficeon 34 CMS Schedulling ● O schedulling é feito de forma agressiva; ● As instruções são executadas fora de ordem em respeito ao programa original; ● É necessário fazer o rollback caso haja uma exceção; Transmeta Efficeon 35 Tratamento de Exceções ● O x86 possui exceções precisas; ● O CMS assume que nenhuma exceção irá ocorrer (especulação) ● Uma exceção causa um rollback até o ponto de commit anterior e o código passa a ser interpretado; ● Uma instrução que causa frequentemente uma exceção é isolada e o resto do código é retraduzido (tradução adaptativa). Transmeta Efficeon 36 Tratamento de Exceções Transmeta Efficeon 37 Interrupções ● Interrupções causam um rollback para um estado consistente (alvo); ● O código traduzido não precisa se preocupar com estados intermediários inconsistentes com um estado x86 entre as instruções; ● Interrupções não ativam a retradução adaptativa. Transmeta Efficeon 38 Movendo loads na frente dos stores ● Load → load-and-protect ● Efetua o load e guarda o endereço e o tamanho do dado ● Store → store-under-alias-mask ● Checa por uma região protegida ● Levanta uma exceção Transmeta Efficeon 39 Memory Mapped I/O ● Transações de I/O devem ser realizadas na ordem do programa original x86; ● Memory mapped I/O não podem ser distinguidas, em tempo de transação, de operações normais de memória; ● Especulação: As operações são reordenadas de forma agressiva; ● Solução: ● Os átomos load e store especificam quando eles foram reordenados em respeito a ordem original do programa. ● Se um átomo especulativo acessa uma página na memória mapeada para o espaço de I/O é lançada uma exceção. Transmeta Efficeon 40 Alias ● Especulação de dados é um outro problema ● O CMS assume que operações de memória não necessitam de alias. Load ou Stores são movidos antes de um store que pode receber um alias (especulação) ● Operações Especuladas setam um registrador de alias a menos que se prove que não há necessidade. O store potencialmente alias checa esses registradores. ● Retradução: Ordenar o código de forma mais conservadora Transmeta Efficeon 41 Alias Transmeta Efficeon 42
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