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Xtensa LX Microprocessor Overview Handbook Iii Contents Xtensa ® LX Microprocessor Overview Handbook A Summary of the Xtensa® LX Microprocessor Data Book For Xtensa® LX Processor Cores Tensilica, Inc. 3255-6 Scott Blvd Santa Clara, CA 95054 (408) 986-8000 fax (408) 986-8919 www.tensilica.com © 2004 Tensilica, Inc. Printed in the United States of America All Rights Reserved This publication is provided “AS IS.” Tensilica, Inc. (hereafter “Tensilica”) does not make any warranty of any kind, either ex- pressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Information in this document is provided solely to enable system and software developers to use Tensilica processors. Unless specifically set forth herein, there are no express or implied patent, copyright or any other intellectual property rights or licens- es granted hereunder to design or fabricate Tensilica integrated circuits or integrated circuits based on the information in this document. Tensilica does not warrant that the contents of this publication, whether individually or as one or more groups, meets your requirements or that the publication is error-free. This publication could include technical inaccuracies or typo- graphical errors. Changes may be made to the information herein, and these changes may be incorporated in new editions of this publication. Tensilica and Xtensa are registered trademarks of Tensilica, Inc. The following terms are trademarks of Tensilica, Inc.: FLIX, OSKit, Sea of Processors, Vectra, Xplorer, and XPRES. All other trademarks and registered trademarks are the property of their respective companies. Issue Date: 9/2004 PD-04-2508-10-00 Tensilica, Inc. 3255-6 Scott Blvd Santa Clara, CA 95054 (408) 986-8000 fax (408) 986-8919 www.tensilica.com Contents Contents Introducing the Xtensa LX Processor Generator ................................................................ xv Introduction to Configurable and Extensible Processor Cores................................................. xv Using Microprocessor Cores in SOC Design .......................................................................... xvii Benefitting from Microprocessor Extensibility......................................................................... xviii How the Use of Microprocessor Cores for SOC Design Differs in Board-Level Designs ........ xxi 1. Introduction to Xtensa LX Technology..............................................................................1 1.1 Ease of Configuration with the Xtensa Processor Generator.......................................... 3 1.1.1 Xtensa LX Processor Performance Summary ..................................................... 4 1.1.2 Feature Summary ............................................................................................ 5 1.1.3 Architectural Building Blocks ............................................................................. 7 1.1.4 Creating a Single Configuration Database with the Xtensa Processor Generator........ 9 1.1.5 Area, Power, and Timing Estimator ..................................................................10 1.2 Ease of Integration.................................................................................................. 11 1.2.1 Currently Supported EDA Tools....................................................................... 11 1.3 Specification Highlights............................................................................................12 1.4 Processor Performance and the Choice of Memory Subsystem ...................................13 1.5 Code Density..........................................................................................................14 1.6 FLIX (Flexible Length Instruction Xtensions) ..............................................................15 2. Xtensa Instruction Set Architecture Highlights ................................................................17 2.1 Registers ...............................................................................................................17 2.2 Memory Addressing ................................................................................................21 2.3 Memory References................................................................................................21 2.4 Program Counter ....................................................................................................22 2.5 Core Instruction Summary .......................................................................................22 2.5.1 Load/Store Instructions...................................................................................25 2.5.2 Jump and Call Instructions..............................................................................25 2.5.3 Conditional Branch Instructions .......................................................................26 2.5.4 Move Instructions ..........................................................................................27 2.5.5 Arithmetic Instructions ....................................................................................27 2.5.6 Bitwise Logical Instructions .............................................................................28 2.5.7 Shift Instructions ............................................................................................29 2.5.8 Reading and Writing the Special Registers .......................................................30 2.6 A Word About Optional Architectural Extensions ........................................................30 2.7 Zero-Overhead Loop Option.....................................................................................31 2.7.1 LCOUNT/LBEG/LEND Registers.....................................................................31 2.7.2 Loop Instruction Alignment..............................................................................32 2.7.3 Loops Disabled During Exceptions ..................................................................32 2.7.4 Loopback Semantics......................................................................................33 2.8 Extended L32R Option ............................................................................................33 2.8.1 Extended L32R Architectural Additions ............................................................33 2.8.2 The Extended L32R Literal Base Register ........................................................34 2.9 16-bit Integer Multiply Option....................................................................................34 2.9.1 16-bit Integer Multiply Architectural Additions ....................................................34 Xtensa LX Microprocessor Overview Handbook iii Contents 2.10 MAC16 Option......................................................................................................35 2.10.1 MAC16 Architectural Additions ...................................................................... 35 2.10.2 MAC16 Use With the CLAMPS Instruction...................................................... 36 2.11 32-bit Integer Multiply Option ..................................................................................37 2.11.1 32-bit Integer Multiply Architectural Additions ..................................................37 2.11.2 Sharing of Integer-Multiplier Hardware............................................................ 37 2.12 Miscellaneous Operations Option............................................................................38 2.12.1 Miscellaneous Operations Architectural Additions............................................ 38 2.13 Boolean Option.....................................................................................................39 2.13.1 Boolean Architectural Additions .....................................................................40 2.13.2 Boolean Registers........................................................................................ 40 2.14 Coprocessor Option .............................................................................................. 41 2.14.1 Coprocessor Option Architectural Additions .................................................... 42 2.14.2 Coprocessor Context Switch ......................................................................... 42 2.14.3 System-Specific TIE Instructions.................................................................... 42 2.14.4 Coprocessor Load/Store Addressing Modes ................................................... 43 2.15 Floating-Point Coprocessor Option.......................................................................... 43 2.15.1 Floating-Point State Additions........................................................................ 43 2.15.2 Floating-Point Instructions and Data Types ..................................................... 45 2.15.3 Floating-Point Exceptions ............................................................................. 47 2.15.4 Floating-Point Instructions............................................................................. 47 2.16 Vectra LX Vector DSP Engine Option ...................................................................... 49 2.16.1 Vectra LX State............................................................................................ 50 2.16.2 Vectra LX Data Types................................................................................... 51 2.16.3 Vectra LX Load and Store Instructions............................................................ 52 2.16.4 Vectra LX MAC Instructions .........................................................................
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