P1360R0: Towards Machine Learning for C++: Study Group 19
Total Page:16
File Type:pdf, Size:1020Kb
Load more
Recommended publications
-
Fault Tolerance and Re-Training Analysis on Neural Networks
FAULT TOLERANCE AND RE-TRAINING ANALYSIS ON NEURAL NETWORKS by ABHINAV KURIAN GEORGE B.Tech Electronics and Communication Engineering Amrita Vishwa Vidhyapeetham, Kerala, 2012 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science, Computer Engineering, College of Engineering and Applied Science, University of Cincinnati, Ohio 2019 Thesis Committee: Chair: Wen-Ben Jone, Ph.D. Member: Carla Purdy, Ph.D. Member: Ranganadha Vemuri, Ph.D. ABSTRACT In the current age of big data, artificial intelligence and machine learning technologies have gained much popularity. Due to the increasing demand for such applications, neural networks are being targeted toward hardware solutions. Owing to the shrinking feature size, number of physical defects are on the rise. These growing number of defects are preventing designers from realizing the full potential of the on-chip design. The challenge now is not only to find solutions that balance high-performance and energy-efficiency but also, to achieve fault-tolerance of a computational model. Neural computing, due to its inherent fault tolerant capabilities, can provide promising solutions to this issue. The primary focus of this thesis is to gain deeper understanding of fault tolerance in neural network hardware. As a part of this work, we present a comprehensive analysis of fault tolerance by exploring effects of faults on popular neural models: multi-layer perceptron model and convolution neural network. We built the models based on conventional 64-bit floating point representation. In addition to this, we also explore the recent 8-bit integer quantized representation. A fault injector model is designed to inject stuck-at faults at random locations in the network. -
In-Datacenter Performance Analysis of a Tensor Processing Unit
In-Datacenter Performance Analysis of a Tensor Processing Unit Presented by Josh Fried Background: Machine Learning Neural Networks: ● Multi Layer Perceptrons ● Recurrent Neural Networks (mostly LSTMs) ● Convolutional Neural Networks Synapse - each edge, has a weight Neuron - each node, sums weights and uses non-linear activation function over sum Propagating inputs through a layer of the NN is a matrix multiplication followed by an activation Background: Machine Learning Two phases: ● Training (offline) ○ relaxed deadlines ○ large batches to amortize costs of loading weights from DRAM ○ well suited to GPUs ○ Usually uses floating points ● Inference (online) ○ strict deadlines: 7-10ms at Google for some workloads ■ limited possibility for batching because of deadlines ○ Facebook uses CPUs for inference (last class) ○ Can use lower precision integers (faster/smaller/more efficient) ML Workloads @ Google 90% of ML workload time at Google spent on MLPs and LSTMs, despite broader focus on CNNs RankBrain (search) Inception (image classification), Google Translate AlphaGo (and others) Background: Hardware Trends End of Moore’s Law & Dennard Scaling ● Moore - transistor density is doubling every two years ● Dennard - power stays proportional to chip area as transistors shrink Machine Learning causing a huge growth in demand for compute ● 2006: Excess CPU capacity in datacenters is enough ● 2013: Projected 3 minutes per-day per-user of speech recognition ○ will require doubling datacenter compute capacity! Google’s Answer: Custom ASIC Goal: Build a chip that improves cost-performance for NN inference What are the main costs? Capital Costs Operational Costs (power bill!) TPU (V1) Design Goals Short design-deployment cycle: ~15 months! Plugs in to PCIe slot on existing servers Accelerates matrix multiplication operations Uses 8-bit integer operations instead of floating point How does the TPU work? CISC instructions, issued by host. -
Abstractions for Programming Graphics Processors in High-Level Programming Languages
Abstracties voor het programmeren van grafische processoren in hoogniveau-programmeertalen Abstractions for Programming Graphics Processors in High-Level Programming Languages Tim Besard Promotor: prof. dr. ir. B. De Sutter Proefschrift ingediend tot het behalen van de graad van Doctor in de ingenieurswetenschappen: computerwetenschappen Vakgroep Elektronica en Informatiesystemen Voorzitter: prof. dr. ir. K. De Bosschere Faculteit Ingenieurswetenschappen en Architectuur Academiejaar 2018 - 2019 ISBN 978-94-6355-244-8 NUR 980 Wettelijk depot: D/2019/10.500/52 Examination Committee Prof. Filip De Turck, chair Department of Information Technology Faculty of Engineering and Architecture Ghent University Prof. Koen De Bosschere, secretary Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Bjorn De Sutter, supervisor Department of Electronics and Information Systems Faculty of Engineering and Architecture Ghent University Prof. Jutho Haegeman Department of Physics and Astronomy Faculty of Sciences Ghent University Prof. Jan Lemeire Department of Electronics and Informatics Faculty of Engineering Vrije Universiteit Brussel Prof. Christophe Dubach School of Informatics College of Science & Engineering The University of Edinburgh Prof. Alan Edelman Computer Science & Artificial Intelligence Laboratory Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology ii Dankwoord Ik wist eigenlijk niet waar ik aan begon, toen ik in 2012 in de cata- comben van het Technicum op gesprek ging over een doctoraat. Of ik al eens met LLVM gewerkt had. Ondertussen zijn we vele jaren verder, werk ik op een bureau waar er wel daglicht is, en is het eindpunt van deze studie zowaar in zicht. Dat mag natuurlijk wel, zo vertelt men mij, na 7 jaar. -
Lecture 26: Domain Specific Architectures Chapter 07, CAQA 6Th Edition
Lecture 26: Domain Specific Architectures Chapter 07, CAQA 6th Edition CSCE 513 Computer Architecture Department of Computer Science and Engineering Yonghong Yan [email protected] https://passlab.github.io/CSCE513 Copyright and Acknowledgements § Copyright © 2019, Elsevier Inc. All rights Reserved – Textbook slides § Machine Learning for Science” in 2018 and A Superfacility Model for Science” in 2017 By Kathy Yelic – https://people.eecs.berkeley.edu/~yelick/talks.html 2 CSE 564 Class Contents § Introduction to Computer Architecture (CA) § Quantitative Analysis, Trend and Performance of CA – Chapter 1 § Instruction Set Principles and Examples – Appendix A § Pipelining and Implementation, RISC-V ISA and Implementation – Appendix C, RISC-V (riscv.org) and UCB RISC-V impl § Memory System (Technology, Cache Organization and Optimization, Virtual Memory) – Appendix B and Chapter 2 – Midterm covered till Memory Tech and Cache Organization § Instruction Level Parallelism (Dynamic Scheduling, Branch Prediction, Hardware Speculation, Superscalar, VLIW and SMT) – Chapter 3 § Data Level Parallelism (Vector, SIMD, and GPU) – Chapter 4 § Thread Level Parallelism – Chapter 5 § Domain-Specific Architecture – Chapter 7 3 The Moore’s Law TrendSuperscalar/Vector/Parallel GPUs 1 PFlop/s (1015) IBM Parallel BG/L ASCI White ASCI Red 1 TFlop/s Pacific 12 (10 ) 2X Transistors/Chip TMC CM-5 Cray T3D Every 1.5 Years Vector TMC CM-2 1 GFlop/s Cray 2 Cray X-MP (109) Super Scalar Cray 1 1941 1 (Floating Point operations / second, Flop/s) 1945 100 CDC 7600 IBM 360/195 -
SIMD in Different Processors
SIMD Introduction Application, Hardware & Software Champ Yen (嚴梓鴻) [email protected] http://champyen.blogspot.tw Agenda ● What & Why SIMD ● SIMD in different Processors ● SIMD for Software Optimization ● What are important in SIMD? ● Q & A Link of This Slides https://goo.gl/Rc8xPE 2 What is SIMD (Single Instruction Multiple Data) one lane for(y = 0; y < height; y++){ for(x = 0; x < width; x+=8){ //process 8 point simutaneously for(y = 0; y < height; y++){ uin16x8_t va, vb, vout; for(x = 0; x < width; x++){ va = vld1q_u16(a+x); //process 1 point vb = vld1q_u16(b+x); out[x] = a[x]+b[x]; vout = vaddq_u16(va, vb); } vst1q_u16(out, vout); a+=width; b+=width; out+=width; } a+=width; b+=width; out+=width; } } 3 Why do we need to use SIMD? 4 Why & How do we use SIMD? Image Processing Gaming Scientific Computing Deep Neural Network 5 SIMD in different Processor - CPU ● x86 − MMX − SSE − AVX − AVX-512 ● ARM - Application − v5 DSP Extension − v6 SIMD − v7 NEON − v8 Advanced SIMD (NEON) − SVE https://software.intel.com/sites/landingpage/IntrinsicsGuide/ http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf6 SIMD in different Processor - GPU ● SIMD − AMD GCN − ARM Mali ● WaveFront − Nvidia − Imagination PowerVR Rogue 7 SIMD in different Processor - DSP ● Qualcomm Hexagon 600 HVX ● Cadence IVP P5 ● Synopsys EV6x ● CEVA XM4 8 SIMD Optimization SIMD SIMD Framework / Software Hardware Programming Design Model 9 SIMD Optimization ● Auto/Semi-Auto Method ● Compiler Intrinsics ● Specific Framework/Infrastructure -
An Analysis and Implementation of the HDR+ Burst Denoising Method
Published in Image Processing On Line on 2021–05–25. Submitted on 2021–03–01, accepted on 2021–05–05. ISSN 2105–1232 c 2021 IPOL & the authors CC–BY–NC–SA This article is available online with supplementary materials, software, datasets and online demo at https://doi.org/10.5201/ipol.2021.336 2015/06/16 v0.5.1 IPOL article class An Analysis and Implementation of the HDR+ Burst Denoising Method Antoine Monod1,2, Julie Delon1, Thomas Veit2 1 MAP5, Universit´ede Paris, France ({antoine.monod, julie.delon}@u-paris.fr) 2 GoPro Technology, France ([email protected]) Abstract HDR+ is an image processing pipeline presented by Google in 2016. At its core lies a denoising algorithm that uses a burst of raw images to produce a single higher quality image. Since it is designed as a versatile solution for smartphone cameras, it does not necessarily aim for the maximization of standard denoising metrics, but rather for the production of natural, visually pleasing images. In this article, we specifically discuss and analyze the HDR+ burst denoising algorithm architecture and the impact of its various parameters. With this publication, we provide an open source Python implementation of the algorithm, along with an interactive demo. Source Code The Python implementation of HDR+ has been peer-reviewed and accepted by IPOL. The source code, its documentation, and the online demo are available from the web page of this article1. Compilation and usage instructions are included in the README.txt file of the archive. The code is also available on GitHub2. Keywords: burst denoising; computational photography; motion estimation; temporal filter- ing; high dynamic range; image signal processor 1 Introduction Image noise is a common issue in digital photography, and that issue is even more prominent in smaller sensors used in devices like smartphones or action cameras. -
AI Chips: What They Are and Why They Matter
APRIL 2020 AI Chips: What They Are and Why They Matter An AI Chips Reference AUTHORS Saif M. Khan Alexander Mann Table of Contents Introduction and Summary 3 The Laws of Chip Innovation 7 Transistor Shrinkage: Moore’s Law 7 Efficiency and Speed Improvements 8 Increasing Transistor Density Unlocks Improved Designs for Efficiency and Speed 9 Transistor Design is Reaching Fundamental Size Limits 10 The Slowing of Moore’s Law and the Decline of General-Purpose Chips 10 The Economies of Scale of General-Purpose Chips 10 Costs are Increasing Faster than the Semiconductor Market 11 The Semiconductor Industry’s Growth Rate is Unlikely to Increase 14 Chip Improvements as Moore’s Law Slows 15 Transistor Improvements Continue, but are Slowing 16 Improved Transistor Density Enables Specialization 18 The AI Chip Zoo 19 AI Chip Types 20 AI Chip Benchmarks 22 The Value of State-of-the-Art AI Chips 23 The Efficiency of State-of-the-Art AI Chips Translates into Cost-Effectiveness 23 Compute-Intensive AI Algorithms are Bottlenecked by Chip Costs and Speed 26 U.S. and Chinese AI Chips and Implications for National Competitiveness 27 Appendix A: Basics of Semiconductors and Chips 31 Appendix B: How AI Chips Work 33 Parallel Computing 33 Low-Precision Computing 34 Memory Optimization 35 Domain-Specific Languages 36 Appendix C: AI Chip Benchmarking Studies 37 Appendix D: Chip Economics Model 39 Chip Transistor Density, Design Costs, and Energy Costs 40 Foundry, Assembly, Test and Packaging Costs 41 Acknowledgments 44 Center for Security and Emerging Technology | 2 Introduction and Summary Artificial intelligence will play an important role in national and international security in the years to come. -
Shinjae Yoo Computational Science Initiative Outline
Lightning Overview of Machine Learning Shinjae Yoo Computational Science Initiative Outline • Why is Machine Learning important? • Machine Learning Concepts • Big Data and Machine Learning • Potential Research Areas 2 Why is Machine Learning important? 3 ML Application to Physics 4 ML Application to Biology 5 Machine Learning Concepts 6 What is Machine Learning (ML) • One of Machine Learning definitions • “How can we build computer systems that automatically improve with experience, and what are the fundamental laws that govern all learning processes?” Tom Mitchell, 2006 • Statistics: What conclusions can be inferred from data • ML incorporates additionally • What architectures and algorithms can be used to effectively handle data • How multiple learning subtasks can be orchestrated in a larger system, and questions of computational tractability 7 Machine Learning Components Algorithm Machine Learning HW+SW Data 8 Brief History of Machine Learning Speech Web Deep Blue N-gram Hadoop ENIAC Perceptron Recognition Browser Chess based MT 0.1.0 K-Means KNN 1950 1960 1970 1980 1990 2000 2010 1ST Chess WWW Data Driven Softmargin Image HMM GPGPU Learning Prog. invented ML SVM Net 2010 2011 2012 2013 2014 2015 2016 NN won ImageNet NN outperform IBM Watson AlphaGo with large margin human on ImageNet 9 Supervised Learning Pipeline Training Labeling Preprocessing Validate Data Cleansing Feature Engineering Normalization Testing Preprocessing Predict 10 Unsupervised Learning Pipeline Preprocessing Data Cleansing Feature Engineering Normalization Predict 11 Types of Learning 12 Types of Learning • Generative Learning 13 Types of Learning • Discriminative Learning 14 Types of Learning • Active Learning • How to select training data? 15 Types of Learning • Multi-task Learning 16 Types of Learning • Transfer Learning 17 Types of Learning • Kernel Learning • Metric Learning 18 Types of Learning • Kernel Learning • Metric Learning 19 Types of Learning • Kernel Learning • Metric Learning • Dimensionality Reduction 20 Types of Learning • Feature Learning 21 • Lee, et al. -
Gables: a Roofline Model for Mobile Socs
2019 IEEE International Symposium on High Performance Computer Architecture (HPCA) Gables: A Roofline Model for Mobile SoCs Mark D. Hill∗ Vijay Janapa Reddi∗ Computer Sciences Department School Of Engineering And Applied Sciences University of Wisconsin—Madison Harvard University [email protected] [email protected] Abstract—Over a billion mobile consumer system-on-chip systems with multiple cores, GPUs, and many accelerators— (SoC) chipsets ship each year. Of these, the mobile consumer often called intellectual property (IP) blocks, driven by the market undoubtedly involving smartphones has a significant need for performance. These cores and IPs interact via rich market share. Most modern smartphones comprise of advanced interconnection networks, caches, coherence, 64-bit address SoC architectures that are made up of multiple cores, GPS, and many different programmable and fixed-function accelerators spaces, virtual memory, and virtualization. Therefore, con- connected via a complex hierarchy of interconnects with the goal sumer SoCs deserve the architecture community’s attention. of running a dozen or more critical software usecases under strict Consumer SoCs have long thrived on tight integration and power, thermal and energy constraints. The steadily growing extreme heterogeneity, driven by the need for high perfor- complexity of a modern SoC challenges hardware computer mance in severely constrained battery and thermal power architects on how best to do early stage ideation. Late SoC design typically relies on detailed full-system simulation once envelopes, and all-day battery life. A typical mobile SoC in- the hardware is specified and accelerator software is written cludes a camera image signal processor (ISP) for high-frame- or ported. -
Podracer Architectures for Scalable Reinforcement Learning
2021-4-14 Podracer architectures for scalable Reinforcement Learning Matteo Hessel*,1, Manuel Kroiss*,1, Aidan Clark1, Iurii Kemaev1, John Quan1, Thomas Keck1, Fabio Viola1 and Hado van Hasselt*,1 *Equal contributions, 1DeepMind Supporting state-of-the-art AI research requires balancing rapid prototyping, ease of use, and quick iter- ation, with the ability to deploy experiments at a scale traditionally associated with production systems. Deep learning frameworks such as TensorFlow, PyTorch and JAX allow users to transparently make use of accelerators, such as TPUs and GPUs, to offload the more computationally intensive parts of training and inference in modern deep learning systems. Popular training pipelines that use these frameworks for deep learning typically focus on (un-)supervised learning. How to best train reinforcement learning (RL) agents at scale is still an active research area. In this report we argue that TPUs are particularly well suited for training RL agents in a scalable, efficient and reproducible way. Specifically we describe two architectures designed to make the best use of the resources available on a TPU Pod (a special configuration in a Google data center that features multiple TPU devices connected to each other by extremely low latency communication channels). Introduction Reinforcement learning (RL) algorithms have been shown to be capable of performing well on challenging sequential decision problems, ranging from board games (Silver et al., 2016) to video games (Mnih et al., 2015) and continuous control (Lillicrap et al., 2016; Van Hasselt, 2012). Many of these advances were powered by the adoption of deep learning (Krizhevsky et al., 2012) in RL. -
Patent Claim Generation by Fine-Tuning Openai GPT-2
Patent Claim Generation by Fine-Tuning OpenAI GPT-2 Jieh-Sheng Lee and Jieh Hsiang Department of Computer Science and Information Engineering National Taiwan University {d04922013, jhsiang}@ntu.edu.tw Abstract (Bidirectional Encoder Representations from Transformers) [4] has become the best practice In this work, we focus on fine-tuning an for state-of-the-art results. GPT-2 is the successor OpenAI GPT-2 pre-trained model for to GPT. Although both GPT-2 and BERT are generating patent claims. GPT-2 has capable of text generation, Wang and Cho [5] demonstrated impressive efficacy of pre- trained language models on various tasks, found that GPT-2 generations are of better particularly coherent text generation. quality. In fact, GPT-2 is claimed to be so Patent claim language itself has rarely powerful that the risk of its malicious use is high. been explored in the past and poses a For this reason, OpenAI decided to keep its unique challenge. We are motivated to largest model (1.5B parameters) closed so that generate coherent patent claims there is more time to discuss its ramifications. automatically so that augmented inventing In this work, we generated patent claims by might be viable someday. In our fine-tuning the released 345M medium version implementation, we identified a unique [6]. Overall we are impressed by how coherent language structure in patent claims and and complicate the generated patent claims could leveraged its implicit human annotations. We investigated the fine-tuning process by be, although not all text are generated equally in probing the first 100 steps and observing terms of quality. -
Euphrates: Algorithm-Soc Co-Design for Low-Power Mobile Continuous Vision
Euphrates: Algorithm-SoC Co-Design for Low-Power Mobile Continuous Vision Yuhao Zhu1 Anand Samajdar2 Matthew Mattina3 Paul Whatmough3 1University of Rochester 2Georgia Institute of Technology 3ARM Research Abstract Haar HOG Tiny YOLO 2 SSD YOLO Faster R-CNN 10 Continuous computer vision (CV) tasks increasingly rely on SOTA CNNs 1 convolutional neural networks (CNN). However, CNNs have 10 Compute Capability massive compute demands that far exceed the performance 0 @ 1W Power Budget and energy constraints of mobile devices. In this paper, we 10 propose and develop an algorithm-architecture co-designed -1 Scaled-down 10 CNN Better system, Euphrates, that simultaneously improves the energy- -2 10 efficiency and performance of continuous vision tasks. Hand-crafted Approaches -3 Our key observation is that changes in pixel data between 10 Tera Ops Per Second (TOPS) Tera 0 20 40 60 80 100 consecutive frames represents visual motion. We first propose Accuracy (%) an algorithm that leverages this motion information to relax the number of expensive CNN inferences required by contin- Fig. 1: Accuracy and compute requirement (TOPS) comparison be- uous vision applications. We co-design a mobile System-on- tween object detection techniques. Accuracies are measured against the widely-used PASCAL VOC 2007 dataset [32], and TOPS is based a-Chip (SoC) architecture to maximize the efficiency of the on the 480p (640×480) resolution common in smartphone cameras. new algorithm. The key to our architectural augmentation is to co-optimize different SoC IP blocks in the vision pipeline col- requirements measured in Tera Operations Per Second (TOPS) lectively. Specifically, we propose to expose the motion data as well as accuracies between different detectors under 60 that is naturally generated by the Image Signal Processor (ISP) frames per second (FPS).