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Broadband Amplifiers for High Data Rates Using Inp/Ingaas Double Karl Schneider Broadband Amplifiers for High Data Rates using InP/InGaAs Double Heterojunction Bipolar Transistors Broadband Amplifiers for High Data Rates using InP/InGaAs Double Heterojunction Bipolar Transistors von Karl Schneider Dissertation, Universität Karlsruhe (TH) Fakultät für Elektrotechnik und Informationstechnik, 2006 Impressum Universitätsverlag Karlsruhe c/o Universitätsbibliothek Straße am Forum 2 D-76131 Karlsruhe www.uvka.de Dieses Werk ist unter folgender Creative Commons-Lizenz lizenziert: http://creativecommons.org/licenses/by-nc-nd/2.0/de/ Universitätsverlag Karlsruhe 2006 Print on Demand ISBN 3-86644-021-9 Broadband Amplifiers for High Data Rates using InP/InGaAs Double Heterojunction Bipolar Transistors Zur Erlangung des akademischen Grades eines DOKTOR-INGENIEURS von der Fakult¨at f¨ur Elektrotechnik und Informationstechnik der Universit¨at Fridericiana Karlsruhe genehmigte DISSERTATION von Dipl.-Ing. Karl Schneider aus Hannover Tag der m¨undlichen Pr¨ufung: 16. Januar 2006 Hauptreferent: Prof. Dr. rer. nat. G. Weimann Korreferent: Prof. Dr.-Ing. W. Wiesbeck Contents Kurzfassung 1 Abstract 2 1 Introduction 3 1.1Motivation.................................... 3 1.1.1 ScopeoftheWork........................... 5 1.2StateoftheArt................................. 6 1.2.1 BroadbandAmplifiers......................... 6 1.2.2 Devices................................. 7 2 InP-based Double Heterojunction Bipolar Transistor 11 2.1OperatingPrinciple............................... 12 2.2Technology................................... 16 2.2.1 ActiveDevices............................. 16 2.2.2 PassiveStructures........................... 18 2.3LayerStructureOptimization......................... 19 2.3.1 InitialLayerStructure(A)....................... 19 2.3.2 ImprovedLayerStructure(B)..................... 24 2.3.3 OptimizedLayerStructure(C).................... 28 2.3.4 Summary................................ 33 2.4TransistorLayoutOptimization........................ 34 2.4.1 EmitterWidthDesign......................... 36 2.4.2 BaseContactWidthDesign...................... 38 2.4.3 CollectorContactDesign........................ 40 2.4.4 EmitterLengthDesign......................... 40 2.4.5 Summary................................ 43 3 Transistor Models 45 3.1Large-SignalModels.............................. 46 3.1.1 Gummel-PoonModel.......................... 46 3.1.2 AlternativeModels........................... 47 3.1.3 UCSDModel.............................. 47 III IV Contents 3.2UCSDModelExtraction............................ 49 3.2.1 DiodeParameters............................ 49 3.2.2 Resistances............................... 51 3.2.3 JunctionCapacitances......................... 55 3.2.4 TransitandDelayTimes........................ 56 3.3Small-SignalModel............................... 60 3.3.1 ModelExtraction............................ 60 3.3.2 InvestigationofTransistors....................... 63 3.4Summary.................................... 68 4 Methods of Broadband Amplifier Characterization 69 4.1FiguresofMerit................................. 69 4.1.1 Bandwidth................................ 69 4.1.2 GroupDelay............................... 71 4.1.3 OutputPower.............................. 71 4.2 Small-Signal-Characterization (S-Parameter) . 72 4.3Large-Signal-Characterization......................... 73 4.3.1 OutputPower.............................. 73 4.3.2 SignalDistortion(Eye-Diagram).................... 74 5 Realization of Compact Lumped Amplifiers 77 5.1DesignConsiderations............................. 77 5.2RealizedAmplifiers............................... 79 5.2.1 Comparison of Lumped Amplifier Approaches . 79 5.2.2 High-Gain Amplifier for 40 Gbit/s . 82 5.2.3 Low-PowerAmplifierfor80Gbit/s.................. 85 5.3OutputPowerLimit.............................. 87 6 Distributed Amplifiers for 80 Gbit/s 91 6.1DesignConsiderations............................. 92 6.1.1 GainCellDesignConcepts....................... 93 6.1.2 AttenuationCompensation....................... 93 6.1.3 Coplanar and Microstrip Transmission Lines . 96 6.1.4 TransmissionLineTermination.................... 97 6.1.5 LinearandMatrixDesign....................... 98 6.1.6 Single-ended and Differential Design . 98 6.2RealizedAmplifiers............................... 99 6.2.1 Low-Power 100 GHz Bandwidth Amplifier . 99 6.2.2 Tunable Amplifier for Loss Compensation . 103 6.2.3 High-PowerAmplifierfor80Gbit/s.................. 108 6.3Summary.................................... 114 7 Conclusion and Outlook 115 Contents V A Extracted Large-Signal Model Parameters 117 Bibliography 119 List of Abbreviations 129 Acknowledgments 131 Curriculum Vitae 132 VI Contents Kurzfassung Diese Arbeit beschreibt die Entwicklung von elektrischen Breitbandverst¨arkern, die f¨ur den Einsatz als Modulatortreiber in optischen Nachrichten¨ubertragungssystemen, die bei einer Datenrate von 80 Gbit/s arbeiten, geeignet sind. Diese Systeme erm¨oglichen die Daten¨ubertragung bei sehr hohen Bitraten, die die Anforderungen der stetig wachsenden Informationstechnologien, zu denen der Mobilfunk und das Internet geh¨oren, erf¨ullen k¨on- nen. Die Realisierung der Verst¨arker wird in einem dreistufigen Entwicklungsprozess er- reicht. Als erstes werden die geometrischen Dimensionen, d.h. die vertikale Schichtstruktur und die lateralen Abmessungen der Einzeltransistoren der verwendeten InP-basierten Dop- pel-Hetero-Bipolartransistortechnologie optimiert. Dieses ist ein wichtiger Beitrag zur Ent- wicklung einer Transistortechnologie, die eine Kombination von sehr hoher Geschwindigkeit und hoher Durchbruchspannung bietet, die f¨ur die Herstellung von Modulatortreibern f¨ur 80 Gbit/s erforderlich ist und die von Silizium-basierten Technologien nicht geleistet wer- den kann. Experimentelle Untersuchungen verschiedener Transistoren zeigen, dass die vertikalen und laterale Abmessungen entscheidenden Einfluss auf das Transistorverhalten haben. Nach drei Iterationen haben die Transistoren eine G¨ute erreicht, die die Entwik- klung von integrierten Schaltungen f¨ur 80 Gbit/s erlaubt. Im zweiten Entwicklungsschritt werden geeignete Transistormodelle bereitgestellt. Aus mehreren publizierten Modellierungsans¨atzen, wird der aussichtsreichsteubernommen ¨ und f¨ur die beabsichtigte Anwendung optimiert. Die G¨ultigkeit der Modelle wird durch den Vergleich von Messung und Simulation einzelner Transistoren und komplexer Schaltungen verifiziert. Die erzeugten Modelle sind nicht nur f¨ur die Groß- und Kleinsignalsimulation von analogen Schaltungen, sondern auch f¨ur die Entwicklung der digitalen Schaltungen eines Nachrichten¨ubertragungssystems geeignet. Schließlich werden mit Hilfe der optimierten Transistoren und Modelle verschiedene Verst¨arker auf Grundlage unterschiedlicher Konzepte entworfen, hergestellt und mit S- Parameter-, Leistungs- und Augendiagrammmessungen untersucht. Die konzentrierten Verst¨arker weisen Vorteile wie geringe Leistungsaufnahme, kleine Abmessungen und damit geringe Herstellungskosten auf. Ihre Ausgangsleistung ist jedoch sehr begrenzt. Im Gegen- satz dazu bieten die verteilten Verst¨arker mehr Ausgangsleistung und h¨ohere Bandbreite. Ein auf Leistung optimierter verteilter Verst¨arker erweist sich als besonders geeignet f¨ur die Entwicklung von Modulatortreibern f¨ur 80 Gbit/s und geh¨ort zu besten Ergebnissen, die in diesem Bereich bisher ver¨offentlicht wurden. 1 Abstract This work describes the development process of electrical broadband amplifiers, which are suitable as modulator drivers in electrical time division multiplex (ETDM) systems, operating at 80 Gbit/s. Such systems are promising candidates for the next generation of high bit rate data transmission systems, which can satisfy the demands of the continuously growing information technologies, including mobile communications and internet. The realization is accomplished in three major development steps. First, the vertical dimensions, i.e. the epitaxial layer structure, as well as the lateral dimensions, i.e. the transistor layout, of InP-based Double Heterojunction Bipolar Tran- sistors (DHBT) are optimized. This is an important contribution in the development of an InP-technology, which offers devices with a combination of high speed and breakdown volt- age, suitable for modulator driver development at 80 Gbit/s and not achievable with silicon based technologies. Various direct current (DC) and high frequency (HF) measurements of different DHBTs are conducted and the results are related to the devices’ geometries. It is shown, that optimized vertical and horizontal dimensions are crucial for realizing high per- formance transistors. The optimized devices feature state-of-the-art performance allowing the development of integrated circuits for 80 Gbit/s. Second, transistor models are obtained from extracted device data. From several pub- lished models, the most suitable approach is adopted and subsequently refined and op- timized to make a compromise between accuracy and complexity. The validity of these models is confirmed by comparing not only measurement and simulation results of tran- sistors, but also of complex circuits. In addition, these models are not only used for small-signal and large-signal simulations in analog circuits, but are equally suitable for developing digital circuits of an ETDM system. Third, using the optimized transistors and models, several amplifiers representing dif- ferent design concepts are realized and experimentally evaluated using S-parameter, power and eye diagram measurements. Lumped amplifiers
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