H8S and H8/300H

Smart Card Interface 28 Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) 29 Controller Area Network 30

Memory Type and Size 22

H8S and H8/300H Selector Guide 23

In Brief 27

Example Block Diagrams 31

Ordering Information Notes and Packages 37 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. Tools 43 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and Third Party Tools 46 performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Related Literature/Internet/ 5. No license is granted by implication or otherwise under any patents or other rights of any third party or CD-ROM/Application notes 47 Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorised for use in MEDICAL APPLICATIONS without the written consent of the appropriate ofﬁcer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales ofﬁces when planning to use the products in MEDICAL APPLICATIONS.

1 Welcome To

Hitachi’s 16-bit microcontroller families customers, H8/300H is an excellent H8S and H8/300H. example where this policy has worked for our customers and Hitachi. Hitachi is the second biggest supplier of In continuation of this policy H8S is 16-bit microcontrollers to the European Hitachi’s answer to our customers request market (according to Dataquest), as well for more performance and lower power as the third for 4-bit, sixth for 8-bit and consumption at better cost/performance number 2 for 32-bit RISC ratios. Hitachi also added larger microcontrollers (the latter on a world- memories and improved the peripherals wide basis). to allow single-chip systems, where previously several components have been At Hitachi Europe we think that this necessary. Switching such a multi-chip success is driven by our strong system to a single-chip system can commitment to be a leading force in the drastically reduce radiation, in today’s microcontroller marketplace and our electronic industry a very important belief that we must listen to our concern. customer’s requirements and then meet these. As H8/300H is the result of H8S combining many years of experience of • 50ns cycle time Hitachi with the experience of our • 16/32-bit CPU • 16MByte address space H8/300H • TPU, PPG, ADC, DAC DMAC, DTC, SCI, WDT • 100ns cycle time subclock, CAN • 16/32-bit CPU • 16MByte address space • ITU, TPC, DMAC, ADC, DAC SCI, WDT H8/300 • 125ns cycle time • 8/16-bit CPU H8S/21xx • 64K address space • FRT, ADC, DAC, SCI, WDT • 50ns cycle time • 16/32-bit CPU • 16MByte address space • FRT, TMR, ADC, DAC, PWM H8/300L IRDA, DTC, SCI, WDT • 250ns cycle time • 8/16-bit CPU • Sub-Clock (32KHz) • LCD Drive, Timers, ADC FRT 16-bit Timer Serial ITU 16-bit Timer x 5 TPU 16-bit Timer x 6 TMR 8-bit Timer x 3 PPG Programmable Pulse Generator DMAC Direct Memory Access DTC Data Transfer Controller ADC A/D Converter DAC D/A Converter SCI Serial I/O WDT Watchdog Timer PWM 14-bit Pulse Width Modulation IRDA Infrared Interface H8 OVERALL ROADMAP TPC Timing Pattern Controller Figure 1 CAN Controller Area Network

2 The European electronics industry produces and ships over 20 million H8 From a statistics point of view, every day demands full service and support. microcontrollers every month, in a vast 2 customers decide to use a 16-bit Hitachi, responded by setting up a range of advanced packaging and microcontroller made by Hitachi. European engineering and tool design temperature options. subsidiary 12 years ago: Hitachi Usually our customer’s product Microsystems Europe (HMSE) based in H8S offers up to 25 native MIPS peak development will continue to proliferate Maidenhead (UK). performance (resulting in almost 10 over the years. For those customers who HMSE provides our customers with Dhrystone MIPS), the peripherals and may need more performance than 16-bit locally designed and supported tools the memory options (for example microcontrollers can offer, it is good to ranging from low cost evaluation boards H8S/2238F with 256KB Flash and 16K know that Hitachi is an industry leader to fully featured real time emulators RAM) to make it an industry standard in in 32-bit RISC microcontrollers as well. based on IBM-compatible PC’s at a very telecommunications and very successful Hitachi’s SH1 and SH2 RISC competitive price. Software ranges from in industrial (e. g. motor control, microcontroller families offer 10 MIPS Assembler, an ANSI C-Compiler via a vending machines, security systems) and or more (Dhrystone), as well as similar or C-level debugger to MakeApp, a tool emerging consumer applications like new in some cases even the same peripherals that sets up peripherals and creates driver electronic video cameras, still cameras and memory options up to 256K Flash routines on the click of a mouse. and advanced car radios. Just recently and 10K RAM. Please order Hitachi’s H8S and H8/300H have also enjoyed SH RISC microcontroller shortform to H8S and H8/300H are part of Hitachi’s much success in automotive applications, get a detailed introduction! software compatible H8 product range, as CAN is now available on-chip and in which covers a performance range from the rapidly growing ﬁeld of smart-card 400ns to 40ns cycle time, whilst appliances, because many derivatives SH2 increasing word length from 8 to 16 bit include one or more ISO7816-compliant • 32-bit RISC CPU and memory space from 64KB to 16MB. serial interfaces. • 33 MIPS/5V • 17 MIPS/3V This product range offers an industry • ITU, TPC, DMAC, MAC leading mix of memory options ADC, SCI (including many ﬂash derivatives), • Motor control and automotive ASSP peripherals and performance/power consumption, all of this being software compatible for protection of our SH1 customer’s software investment. Hitachi • 32-bit RISC CPU • 20 MIPS/5V • 12 MIPS/3V • ITU, TPC, DMAC, MAC ADC, SCI

H8/300H H8S

Figure 2

3 H8S Roadmap

H8S+CAN (F)* H8S/26xx H8S/2655 series H8S/2633 series (F)* H8S/267x series (F)* highest up to 128K/4K up to 256K/16K up to 256K/8K Multiply-Accumulate Multiply-Accumulate Multiply-Accumulate performance 20MHz at 5V 25MHz at 3.3V 33MHz at 3.3V

H8S/2357 series (F) H8S/2345 series (F) H8S/232x series (F) H8S/23xx up to 128K/8K up to 128K/4K up to 256K/8K general purpose 20MHz at 5V 20MHz at 5V 25MHz at 3.3V

H8S/2246 series H8S/2238 series (F) H8S/22xx up to 128K/8K up to 256K/16K lowest power low power low power/32KHz SC large memory 20MHz at 5V 13MHz at 3V Performance/ Memory/ Integration H8S/212x series (F) H8S/213x series (F) H8S/214x series (F) H8S/21xx up to 128K/4K up to 128K/4K up to 128K/4K lowest cost 64 pin package 80 pin package 100 pin package 20MHz at 5V 20MHz at 5V 20MHz at 5V

* Under development (F) FLASH version available Note: most 5V derivatives are also available in 3V/10MHz or 3V/13MHz H8/300H Roadmap

H8/3022 series (F)* H8/3052 series (F)* H8/300H up to 256K/8K 512K/8K 3rd generation low voltage operation big memory option large memory 18MHz at 3V 18MHz at 3V

H8/3042 series H8/3048 series (F) H8/306x series (F) H8/304x, 6x up to 64K/2K up to 128K/4K up to 128K/4K general small memory option high integration 2nd generation purpose 16MHz at 5V 16MHz at 5V 20MHz at 5V

H8/3032 series H8/3035 series H8/3039 series (F) H8/303x up to 64K/2K up to 256K/4K up to 128K/4K low cost small memory option big memory option with ROM 16MHz at 5V 18MHz at 5V 18MHz at 5V Performance/ Memory/ Integration

H8/3001, 2, 3 series H8/3004, 6 series H8/3005, 7 series H8/300x 512Byte RAM 2K RAM 4K RAM low cost 80, 100, 112 pin 80, 100 pin 80, 100 pin ROM-LESS 16MHz at 5V Up to 20MHz at 5V Up to 20MHz at 5V

* Under development (F) FLASH version available Note: most 5V derivatives are also available in 3V/8MHz or 3V/10MHz

Figure 3 4 CPU

All H8 share a common CPU Being general purpose there is no In addition to the general purpose architecture, a general purpose register restriction placed on how each register is registers there are two control registers, a architecture that allows efficient used, thus they can be used for pointer Condition Code Register (CCR) and a execution of software written in C and or data operations. The architecture also Program Counter (PC). The CCR is an produces dense code. A good code allows any of the data addressing modes 8-bit wide register which contains all the density is important to reduce the to be used in conjunction with any CPU flags such as overflow, zero and amount of memory needed, which in register. carry as well as the interrupt flags. The turn results in a lower system cost and carry flag also doubles as a bit helps to avoid external memory. As This rich set of general purpose accumulator when the bit manipulation shown below in figure 5 the 8-bit H8 registers provides the compiler writer operations are used. families have 16-bit wide registers and with ample opportunities to optimise the 16-bit families have 32-bit wide the code generated by the compiler. The H8/300H CPU offers a H8/300 registers, all of which can also be used Local variables can be optimised into compatible mode which allows partially (for example in bytes). H8S registers wherever possible, thus straightforward reuse of existing H8/300 adds an extended Condition Code reducing the number of bytes of code software. This mode is available in Register (EXR) to allow improved needed to manipulate them. Also, H8/3032, H8/3042 and µCBIC interrupt control and H8S/2655 adds a because each register can be used as an products. Multiply-Accumulate Unit (MAC) to accumulator, index register or address boost performance in DSP-type pointer, the address arithmetic which applications. must be performed by the compiler can be done very effectively. Register ER7 Furthermore H8S executes basic is used as a stack pointer, so all accesses instructions in only one clock cycle, half to stack based data can be performed as many as H8/300H. very fast.

H8S 0 7 R0 15 R1 31 R2 H8/300H ER0 R3 0 ER1 7 R0 R4 15 ER2 R1 R5 H8/300 ER3 31 R2 R6 H8/300L ER0 ER4 R3 R7 0 ER1 ER5 7 R4 15 R0 ER2 ER6 0 R5 PC R1 ER3 ER7 15 31 R6 R2 ER4 23 R7 R3 ER5 CCR R4 ER6 0 R5 PC ER7 15 EXR R6 23 R7 CCR MAC 0 PC 15 EXR 23 Sign Extended

CCR MAC MAC on H8S/26xx only EXR Sign Extended MAC

Figure 5

5 Instruction Set

H8/300H has an instruction set which Function Instruction suits the combined needs of HLL Data transfer MOV,PUSH, POP,MOVTPE, MOVFPE, LDM, STM programming and embedded applications. Arithmetic ADD, SUB,ADDX, SUBX, INC, DEC,ADDS, SUBS, It comprises of 62 instructions, with an operations DAA, DAS, MULXU, DIVXU, MULXS, DIVXS, CMP, emphasis on arithmetic instructions, NEG, EXTS, EXTU, TAS, MAC, LDMAC, STMAC, address manipulation and bit processing. CLRMAC More than half of all instructions have an Logic operations AND, OR, XOR, NOT instruction length of only 2 Bytes making Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR very compact code. H8S extends the Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR instruction set to 69 instructions. BOLD BXOR, BIXOR, BLD, BILD, BST, BIST instructions are new on H8S. Branch Bcc, JMP,BSR, JSR, RTS System control TRAPA, RTE, SLEEP,LDC, STC,ANDC, ORC, XORC, NOP In comparison with the H8/300 CPU most of the data transfer, logical, shift and and multiplication of 16 x 16-bit data Operation H8S H8/300H arithmetic instructions are improved to and division of 32 / 16-bit data. Add 32bit 50ns 125ns handle 16 and 32-bit data. New Multiplication and division are both operands instructions added to the H8/300H available as signed and unsigned AND 32 bit 50ns 125ns include signed multiplication, sign operations, which eliminate the need for operands extension, 16-bit branch instructions and time consuming library calls. The table multiply/divide 200ns/ 875ns a software trap instruction. below gives a guide to the execution 16bit operands 650ns speed of various arithmetic instructions (32bit result, signed) H8S further improves the instruction set with a clock of 16MHz (H8/300H) and by adding STM (store multiple) and 20MHz (H8S). LDM (load multiple). These instructions allow to evacuate multiple registers on to the stack, thus drastically shortening the time if compared with multiple PUSH and POP. For example, pushing 4 registers onto the stack takes 40 states on Instruction: BTST R1L, R1H H8/300H and only 11 on H8S. Also R1L points to a bit position within R1H improved are some bit manipulations (to include 16/32-bit absolute addressing) R1L 0 0 0 0 0 1 0 1 7 and shift operations to support 2-bit = 5 shifts. H8S/2655 also adds instructions to support the Multiply-Accumulate-Unit.

Arithmetic R1H 0 0 1 0 0 0 0 0 Instructions

In order to perform complex algorithms bit # 5 such as digital ﬁltering, H8S and H8/300H are equipped with powerful arithmetic instructions, including Z in CCR addition and subtraction on 32-bit data Figure 6

6 Bit Processing Addressing

In microcontroller applications it is often To support large memory systems, the available addressing modes. Supporting necessary to manipulate data on a bit by linear address space of the H8/300H and both, array and stack data types, the CPU bit basis. A good example would be the H8S CPU core allows direct access has indirect addressing with either where an I/O pin needs to be set to to every address in the whole 16MByte postincrement or predecrement. These switch on a lamp or a solenoid. To meet address space via 24-bit address pointers. modes support byte, word and long word this demand H8S and H8/300H have 14 The linear address space means there is data (±1,2 and 4) as shown in figure 7. separate bit processing instructions which no need to set up page registers and allow the programmer to manipulate bit there are also no limitations on the size Three absolute addressing modes are data very easily. of code modules or data arrays and provided using 8, 16 or 24-bit absolute structures. addresses. Using the 24-bit address the It is also possible to perform boolean entire 16MBytes address space is algebra on bit data using the carry flag of Addressing accessible. The 8 and 16-bit absolute the CCR register as a bit accumulator. In Modes address modes assume that the upper a microcontroller application it is often byte or word of the address is H’FFFF or necessary to perform a branch depending Another way a CPU architecture can H’FF respectively. This allows for the on the values of two bit flags located in support the efficiency of the compiler is efficient address specification for the on- RAM or I/O ports. Using the boolean by providing a full set of powerful and chip I/O area and RAM areas which are operations provided by H8S and flexible addressing modes. To ensure that both placed at the top of the address H8/300H the first bit can be loaded into the compiler is as efficient as possible the map. These shortened addresses save the carry flag. Then a bitwise logical H8S and H8/300H CPU’s provide eight significant amounts of code when these operation can be executed using the addressing modes as shown in the table. areas are accessed. second bit. This sequence would then be Each instruction can use a subset of the followed by a branch depending on the value of the carry flag. Register direct R n Register indirect @ E R n Another feature of the H8S and H8/300H Register indirect @ (d: 16, E R n) bit processing capability is its ability to with displacement @ (d: 24, E R n) access bits indirectly, using the value from Register indirect with post-increment/ @ E R n +, @ - E R n a general purpose register as a bit pointer. Register indirect with pre-decrement This mechanism is shown in figure 6 and Absolute address @ a a : 8, @ a a : 16, @ a a : 24 is useful for scanning a byte for set or Immediate # x x : 8, # x x : 16, # x x : 32 PC-relative @ (d : 8, PC), @ (d : 16, PC) cleared bits. Memory indirect @@ a a : 8 Software Interrupt

Register indirect with post-increment or pre-decrement The TRAPA instruction has been *Register indirect with post-increment @ERn+ 31 0 23 0 implemented in the H8S and H8/300H Register contents CPU. This instruction implements a software interrupt, jumping to a service op reg routine via one of four exception vectors 1, 2 or 4 *Register indirect with pre-increment @ERn (TRAPA 0 - 3). This operation can be 31 0 used to implement fast, space efﬁcient Register contents 23 0 calls to often used sub-routines such as schedulers and other O/S routines. The op reg Operand Size Added Value TRAPA instruction can also be used as a Byte 1 1, 2 or 4 Word 2 call to an error handling routine. Longword 4 Figure 7

7 Low Power

In today’s electronics industry, low power Current dissipation (mA) consumption is an ever increasing Conditions: 15 concern for many engineers. Beyond HD6472246 typ. Sample 10Mhz/3.0V obvious reasons like longer battery life Ta=25°C for example in mobile phones, notebooks Singlechip mode 10 and electronic cameras, there are many more reasons why low power is Active mode Sleep mode paramount: 5 Values based on sample • Some applications have legal measurements, values not guaranteed restrictions on power consumption like gas meters (to avoid a spark 0 Icc-ope. Sleep DTC TPU TMR A/D SCi0 SCi1 SCi2 TMR All causing an explosion), electricity All Mode Stop Stop Stop Stop Stop Stop Stop only module module Operate Stop metering to avoid unnecessary loading Figure 8 of the mains network or fixed proportion. A H8S/2246 for example telecommunication equipment that is DTC stop 0. 3mA will only draw appr. 4mA (typical) at powered off the line TPU stop 9mA 3V and at 2MHz with all the modules • other applications can draw much TMR stop 2mA operating. current under normal conditions but DAC stop 2. 2mA • The CPU can be stopped (sleep have to run of a battery when mains ADC stop 2mA mode), with all the registers and fails, e. g. security systems and cash each SCI stop 2mA memory contents being retained. registers Sample data (not guaranteed), typical, at 5V /20MHz • Some car electronics must keep up a Peripherals continue to operate and for a H8S/2355 minimum level of activity while a car any interrupt will wake up the CPU is parked, nevertheless the car battery instantly. Sleep mode reduces power case of H8/300H clock gearing must not be flat when the car is to be consumption by about one third. effects the entire chip, so reduction used again • Just like the CPU can be stopped at will be almost proportional, in case of • and last but not least, low power goes times of low activity, some H8/300H H8S clock gearing effects only bus hand in hand with low radiation! and all H8S derivatives allow to stop masters (CPU, DMA, DTC) to avoid peripheral modules. For example, reprogramming of e. g. timers. The Numerous measures have been taken to while the ADC is not needed the effect is shown in Figure 9. allow H8/300H and H8S to meet all software simply clears the • Some H8S derivatives also feature a these demands: corresponding bit in the module stop 32KHz subclock, which allows to • All derivatives are available in low register. Figure 8 shows how much run the CPU, the 8-bit timers and the voltage versions as well (except current is saved per module for a watchdogs at 32KHz (‘subactive’), or H8/3039). Low voltage operation not H8S/2355 and also shows a curve for just the 8-bit timers and watchdogs only significantly reduces power H8S/2246 with one module after the (‘subsleep’) or finally the watchdogs consumption, but also allows battery other being turned off. The lower only (‘watch mode’). In watch mode operation with a smaller number of curve shows the same, if the CPU is a periodical interrupt, which is cells and reduces radiation drastically, brought into sleep as well. generated from the subclock at a rate especially where external busses have to • Beyond the possibility to run of once per second for example, be used. H8/H8S off a slower clock statically, wakes up the CPU. The CPU then • All derivatives can be run off a slower some H8/300H and all H8S offer the checks system status (e. g. key clock, down to 2MHz. Power ability to dynamically reduce the pressed?) and then activates other consumption will drop almost in clock internally (‘clock gearing’). In modules or returns to sleep, as

8 required. Hence, very low average As an example for such a combination, power consumption can be achieved, let’s assume the DTC would be used to even with a real time clock being move results of ADC conversions from implemented in software. the ADC to a RAM buffer (e. g. 64 • If no activity is required, but RAM Byte). The CPU does not need to contents must be retained, H8/H8S process the data before acquisition of all microcontrollers can be brought into data has ﬁnished. This scenario would standby. In this mode the oscillator is allow to turn off all the modules, except stopped and power consumption the ADC and the DTC, and put the drops to leakage current levels CPU into sleep during acquisition. (0. 01µA, typical at room The resulting current would be only temperature). Two modes are appr. 3mA at 10MHz and 3V Vcc. provided, software standby which After acquisition of all 64 Byte has allows to retain IO ports and ended, an interrupt wakes up the CPU hardware standby, which only retains to process the data. While doing so the RAM. RAM retention voltage is software may choose to activate other only 2V. peripheral modules as required. Please note that power consumption in Some of these methods can be combined this scenario could be further reduced if to achieve outstanding average power 10MHz clock gives more performance consumption values, while allowing high then needed. Typical Icc between 2mA performance operation at times of high and 3mA are possible. activity.

Figure 9

Ta=R.T. 80

70 5.5V, 20MHz 60

30 Current consumption (mA) 20 3.0V, 10MHz

0 ø/8 ø/4 ø/2 ø Clock Values based on sample measurements, values not guaranteed

9 Exceptions Trap instruction priority interrupt sources, which are and exceptions (TRAPA) capable of interrupting a low priority Interrupt ISR which is already running. The These exceptions start when a TRAPA priority of individual interrupt sources Controller instruction is executed in program is programmed in a number of execution state. The TRAPA instruction interrupt priority registers (IPR). H8/300H and H8S feature a has four vectors as specified by its sophisticated interrupt system, that allows argument. This exception can be used as Interrupt to respond quickly to asynchronous an efficient mechanism for calling controller events. The worst case interrupt response operating system functions, as it takes on H8S time is 2. 6µs for H8/300H (at 16MHz) only 2 Byte to execute a TRAPA and 1. 5µs for H8S (at 20MHz). instruction, compared to 4 Byte for a The interrupt controllers within the H8S Because almost every interrupt source BSR and 8 Byte for a JSR. family differ, depending on the particular has its own vector, the interrupt service H8S series. H8S/2655 has an interrupt routine can immediately start to do some Interrupt controller that provides four modes useful work, instead of polling status flags Controller (0...3) and the other series provide a to find the cause of the interrupt. on H8/300H subset. If two or more exceptions occur simultaneously, they are accepted and The H8/300H interrupt controller can • Mode 0 processed in order of priority. Software be operated in two modes, either This mode provides the mechanism interrupts (‘Trap’) are accepted at all maintaining compatibility with the known from H8/300. Acceptance is times, in the program execution state. standard H8/300 interrupt controller, or solely controlled by the I-bit. in a more advanced mode. Interrupts are handled as follows: • Mode 1 • The PC and the CCR are pushed • H8/300 compatible In this mode acceptance is controlled onto the stack mode by I and UI, thus providing functional • The interrupt mask bits are updated In this mode the acceptance of compatibility with H8/300H. • A vector address corresponding to the maskable interrupts is controlled by the exception source is generated, and I-bit in the CCR. If I is set, then all • Mode 2 program execution starts from that interrupts are disabled (except NMI) This mode provides an 8-level address and if I is cleared then all interrupts are priority mechanism controlled by bits enabled. When an interrupt is I0. . I2 in the EXR register. Priorities External interrupts accepted, the controller automatically for each interrupt source can be (NMI and IRQ) sets the I-bit, thus disabling any other programmed in a set of IPR registers. maskable interrupts for the duration of H8/300H and H8S have several external the interrupt service routine (ISR), • Mode 3 interrupts, including one non-maskable- unless it is cleared by the users code. This mode combines mode 1 and 2, interrupt (NMI). NMI can be effectively providing up to 9 levels of programmed to be activated on either • H8/300H advanced priority. the rising or the falling edge. Interrupt mode request pins (IRQ) can be programmed To increase the power of the interrupt H8S/265x derivatives can use modes to recognise either a low level or a low controller, an extra interrupt status bit 0. . 4, H8S/263x, H8S/23xx, H8S/223x going edge on H8/300H, and on H8S is included in the condition code and 222x can use modes 0 and 2, and can be programmed to recognise a low register, known as the UI or User H8S/224x and 21xx can use modes 0 level, a rising or a falling edge or both Interrupt bit. This extended operation and 1. edges. allows the user to specify raised

10 Memory consumption of Hitachi’s microcontrollers, • USER Mode FLASH such a redesign will often immediately User mode is not entered via reset. It eliminate radiation problems. At the is fundamentally just like normal A traditional strength of Hitachi’s same time costly shielding measures may operation, but with Flash microcontrollers are the large integrated become unnecessary, thus lowering programming enabled via the mode memories and the advanced memory system cost and board space requirements (usually FWE) pins. technology. will become less. In user mode, an external trigger event causes the user software to copy Already for many years, it has been an Other benefits of large integrated a piece of code into RAM. Program important strategy to provide memory and especially of on-chip Flash execution then jumps to this code. microcontrollers with high-speed, on- memory are: The Flash can then be reprogrammed chip Flash memory to the European • end of line programming allows under the control of the user’s market, always at the leading edge of this flexibility in the software until application, using all the resources of industry trend. This technology is now shipment the chip (i. e. downloading the new offered in its third generation, providing • allows easy and fast update in the field code does not necessarily have to use larger memory sizes and single-voltage without the need to open the a serial interface, but could use any programming. Hitachi is currently equipment other resource). This mode is shipping over 4M Flash microcontrollers • allows software updates even remotely, intended for Flash memory updates. per month. e. g. via modem/phone line • fast response to changing customer • PROM Mode A table in the middle of this brochure requirements All H8/H8S Flash derivatives can also shows Hitachi’s 16-bit microcontrollers • non volatile storage of data and be programmed using general purpose by ROM and RAM size, including 16 parameters programming equipment, i. e. in the on-chip Flash derivatives. Please use the • full availability of all ports, if external same way OTP’s are programmed. table to select the devices which meet busses can be avoided your memory requirements. • full speed operation, often impossible or expensive if external memory is Hundreds of customers worldwide have used taken advantage of our flash based microcontrollers in their designs, about Flash programming one third in industrial and automotive applications, approximately one fourth • BOOT Mode each in consumer and office automation Boot mode is entered if the mode and the remainder in telecommunications. pins of a H8/H8S are in a certain state after reset. In boot mode Integrating large and flexible memories program execution starts from a has numerous benefits for our customers, hidden ROM. The software in this some of which are becoming crucial in ROM initialises one of the serial today’s demanding electronics industry. interfaces, downloads another piece of For example: Switching an older software (available from Hitachi, if microcontroller design, which uses desired), which then allows to external memory and peripherals, to a (re)programme the Flash memory. single-chip design, will drastically reduce Boot mode can be used to supply a radiation, because the address and data blank (i. e. new) Flash device with a busses are a major source of radiation in software, even when the device is a system. Together with the low power already soldered onto the PCB.

11 Bus State Controller (BSC)

As one of the key reasons for using the • DRAM access protocol for one area executes slow external write accesses H8S and H8/300H is the 16MBytes on 300H (=2Mbytes) and for 4 areas independently (on H8S/26xx and on linear address space, it will often be used on H8S (=8Mbytes)(not on all some H8S/23xx derivatives) and the in a system with a large amount of devices) improvement of read access time by external memory. Consequently, H8S moving the clock edge that latches the and H8/300H are supported by a Bus State Controller read data to the end of the bus cycle. powerful bus state controller (BSC) that (BSC) on H8S allows external memory and/or DRAM interface peripherals to be connected with no (in One of the major advantages of H8S over some rare cases with little) glue logic. H8/300H is its basic instruction Areas two to ﬁve can be set to interface Also, the BSC helps to get the maximum execution within a single clock cycle, that directly to DRAM on on H8S/26xx and performance out of any external devices, is only 50ns at 20MHz clock if executed on some H8S/23xx derivatives, allowing for example by avoiding address decode from internal memory. In order to up to 8MB of DRAM to be connected delays, where on-chip chip-select minimise the negative impact on without any glue logic. The BSC generation is used. performance when going off chip, every handles the address multiplexing (8,9 or effort has been made to create a BSC 10 bits), the timing and allows to use fast The BSC divides the memory space into with a maximum of throughput and page mode. DRAM with CAS-before- 8 areas. For each of these areas a number ﬂexibility. RAS (CBR) or self-refresh are of attributes is selectable, for example: supported. For CBR refresh mode the • the wait mode (automatic insertion or Major enhancements include support for BSC provides an independent refresh hardware protocol) fast-page mode DRAM (on H8S/26xx counter, so that no other timers have to • the number of wait states and on some H8S/23xx derivatives), be used. • the bus width (8/16-bit) burst mode ROM, a write buffer that

Address bus

Data Bus tACC

Address bus

Data Bus tACC Improved Access Time Figure 10

12 Improved read state internal processing continues as long access timing as there is no external access.The internal bus master, wishing to access the In order to give external devices a external bus during bus release state, may maximum of time to drive the required use the BREQO signal to indicate to the data onto the bus, the read access edge external master that the bus ownership that latches the data, has been moved to should be given back. The external bus the end of the cycle. Therefore read master should respond by dropping access time is improved by approximately BREQ. BREQO can also be used to one quarter, compared with H8/300H. signal that a refresh cycle for a DRAM is Figures 10 & 11 illustrate this effect for pending. several frequencies.

Write data buffer

Improved Access Time On H8S/26xx and on some H8S/23xx derivatives, a write data buffer is 200ns provided. This feature allows the CPU H8S to continue internal processing, while the BSC takes care of slow write accesses independently. Figure 12 shows an 100ns example of the timing when the write 50ns data buffer is used. When this function is H8/300H activated, if an external write or DMA single address mode transfer continues for 10 12 16 20 MHz 2 states or longer, and there is an internal Figure 11 access next, only an external write is executed in the ﬁrst state. But from the next state onward an internal access is On-chip memory read Internal I/O register read executed in parallel with the external access, rather than waiting until it ends. External write cycle

T1 T2 TW TW T3 Bus release

Internal address bus On all H8S devices a mechanism is Internal memory Internal I/O register address provided to allow external bus masters to Internal read signal obtain external bus ownership.

To request ownership an external master External address A23 to A0 must drive the BREQ pin low. After the CS BREQ pins has been sampled low by the External n H8S, the address bus, data bus and the space write bus control pins are placed in a high HWR, LWR impedance state and the Bus D to D Acknowledge (BACK) signal is asserted 15 0 to signal to the external master that the Figure 12 bus is now available. During bus release

13 Direct Memory Access Controller (DMAC)

In a system with a high performance Some of the major improvements on performed between any area of the full CPU and with large memory, a Direct H8S are: 16MBytes address space. This mode Memory Access Controller will • A special transfer mode has been allows either a single transfer to occur significantly increase system performance. added, single address mode, where per request (‘normal mode’), or for a Instead of wasting CPU performance to both resources must be external and block of data to be moved (‘block move data between peripherals and data is transferred in fly-by fashion for transfer mode’). In ‘normal mode’ and memory, virtually all of the CPU fastest transfer speed. with ‘auto-request’ enabled, the DMAC performance can be used for calculations, • More transfer request sources, e. g. can be set up in a burst mode, taking while the DMA handles the data A/D conversion end interrupt and at over the bus from the processor until all transfers. least 2 SCI can request a transfer the transfers are complete, or in a cycle steal mode where the processor and the If combined with other peripherals, such Short Address Mode DMAC share the bus. as timers, SCI’s or the real time outputs of the TPC/PPG, entire autonomous In this mode either the source or Single address subsystems can be built, for example to destination address is limited to only 8 mode (H8S) drive stepper motors or to communicate bits (H8/300H) or 16 bits (H8S), with with LCD modules or keyboards with the upper bits being automatically set to Figure 13 illustrates the new single hardly any CPU intervention. logic ‘1’. This allows to access the address mode. In single address mode a internal IO registers. The other address transfer of data is carried out directly As H8S almost triples the CPU is 24 bits wide, so that the entire between the data busses of two external performance of H8/300H, the DMAC on memory space is accessible. devices, e. g. an external peripheral and H8S has improvements over the H8/300H Within short address mode there is ‘IO DRAM. The advantage is the speed of DMAC, in order to keep CPU and mode’ (called sequential mode on H8S), the transfer, because the data is moved in DMAC performance in a good balance. where the full address can be a single cycle without a temporary But let us first have a look at the common automatically incremented or storage. Either the source or the features: decremented,‘idle mode’ with the full destination must be a device which can address being fixed and ‘repeat mode’, be accessed with a strobe alone, using the • 4 channels in short address mode which allows cyclic data buffers to be DACK pin. The address bus is used to (used for transfers between internal automatically transferred. Cyclic data access the other resource. IO and memory)* buffers are useful for many applications, • 2 channels in full address mode (used e. g. to output a control pattern for a for transfers between memory and stepper motor.

memory, or between external IO and RD memory) Full Address HWR, LWR External • Byte or word transfer selectable Mode Address bus A23 to A0 memory • address increment, decrement or ﬁxed (Read) selectable, depending on mode To perform memory to • DMA transfer request possible by memory transfers the full H8S/2655 (Write) timer, SCI0 and external request, address mode can be D to D depending on mode used. Here, the source 15 0

(high impedance) Data bus • Interrupt request possible after each and destination addresses transfer or after speciﬁed number of are 24-bits wide each, External device transfers and therefore memory to DACK memory transfer can be * 8 channels on H8/3003 Figure 13 14 Data Transfer Controller (DTC)

Analysis of many applications that use a the block, thus practically eliminating the takes 3 cycles and the actual data transfers DMAC has shown that a substantial part overhead penalty. take 2 cycles (minimum). of these applications do not require the maximum speed of data transfers. These Also, a single trigger can request multiple The DTC could be seen as a DMAC applications use a DMAC mainly to transfers (chain mode). with only a single channel implemented reduce CPU overhead, allowing the This feature could, for example, be used in hardware. The registers for the CPU to use its performance for to move the result of an analogue-to- destination and source address, for the calculations. digital conversion to a circular buffer in transfer mode and the transfer count RAM, followed by automatic actually exist only once. However, these Therefore Hitachi conceived another reprogramming of the ADC to perform registers are loaded with the information peripheral to autonomously handle data other conversions. If the tasks given to to be used for a particular transfer from transfers, the Data Transfer Controller the ADC are stored in a table in ROM, RAM. That means that the structure of (DTC). The DTC puts emphasise on which is then used by the DTC in a the DTC registers is mirrored in a special offloading the CPU from data transfer round-robbing scheme, while the DTC RAM as many times as the tasks, while providing a maximum of conversion results are stored in a designer has chosen to implement flexibility. Unlike a DMAC the DTC can corresponding number of circular buffers transfer channels. Each transfer can be handle a very large number of transfer in RAM, the DTC and the ADC could specified to be byte- or word-wide, channels and transfers can be requested by perform a large set of completely source and destination addresses can both almost any peripheral that can request an different tasks without any CPU be 24-bits wide (i. e. cover the full interrupt as well as by software. On the intervention whatsoever. address range). Source and destination other hand a DTC transfer is Figure 14 shows the timing of such a addresses can be either incremented or approximately 5 times slower than a DMA chain transfer. Please note that one cycle decremented (by 1 or 2), or can be fixed. transfer (1000ns as opposed to 200ns at of phi is only 50ns at 20MHz. As can be A CPU interrupt can be requested for 20MHz, assuming e. g. source is a seen, the DTC vector is read after a the interrupt that triggered the DTC peripheral and destination memory). In transfer request in only one cycle, each transfer, either after each transfer or after block transfer mode the DTC overhead is move of the transfer information the specified number of transfers have divided by the number of transfers within between DTC RAM and DTC registers been performed.

Figure 14

DTC activation request

DTC request Data transfer Data transfer Vector read Address Read Write Read Write

Transfer Transfer Transfer Transfer information information information information read write read write

15 Timer

One of the most important peripherals used. Hence, more money then is being the triggering of a DMA channel. on any microcontroller is the timer unit. spent on more powerful Channels 3 and 4 allow to produce a Timers have many uses in electronic microcontrollers, could be saved on pulse with duration down to one systems. They trigger the task switch of external devices, assembly cost, board clock cycle (62. 5ns at 16MHz). real time operating systems, update space, power supply and on reduced software real time clocks, control AC, DC counter measures against radiation. In • Input Capture Functions or stepper motors, check validity of particular, electronic systems which The ITU provides up to 10 channels external signals (‘timeout’), count pulses currently use 8-bit microcontrollers of input capture. In this mode the for example from phase quadrature should be reconsidered under these timer can be set up so that a transition encoders and much more. Timers can aspects! on an input pin causes the value even act as accurate digital-to-analog currently in the count register to be converters (DAC), if used as pulse-width- Integrated Timer transferred into a capture register, thus modulator (PWM). Unit (ITU) time stamping that particular event. In order to accommodate all these The ITU can be set to capture rising applications, Hitachi has developed 2 The ITU consists of ﬁve separate 16-bit edges, falling edges and either of powerful and ﬂexible timer units for timer channels, each of which can be these. If required the timer unit can their 16-bit microcontrollers, as well as clocked from an internal derivative of the also clear the timer when the several special-function timers, for system clock (ø, ø/2, ø/4 and ø/8) or programmed external event occurs. example separate PWM timers, watch from an external pin. If the ø clock The two buffer registers (BRA and dog timers (WDT), low-power support option is selected, then the minimum BRB) provided in timer channels 3 timers, etc. These two timer units are the resolution of the timer is 62. 5ns (ø = and 4 can be used to buffer input ITU on H8/300H, a 5-channel 16-bit 16MHz). The standard timer functions time stamps. This allows events which timer unit with up to 10 input provided by the ITU include ten general occur very close to each other to be capture/output compare (IC/OC) and registers (GR), which can be used as time stamped using one capture pin. the TPU on H8S, a 6-channel 16-bit output compares or input captures. A This feature can also be used to timer unit with up to 16 IC/OC. further four 16-bit buffer registers (BR) measure the width of an incoming An exception are the H8S/21xx devices. reduce the overhead placed on the CPU pulse, by programming the capture H8S/21xx is aimed on very cost sensitive when servicing the timer block. input to be triggered on both the application, where the advanced timer rising and falling edges. functionality of the ITU/TPU is either • Output Compare Functions By using input captures to measure not needed or can be handled by the To create output waveforms or timed the timing of external signals, very high performance H8S CPU instead. interrupts, the ITU provides up to 10 accurate measurements of variables H8S/21xx has a 16-bit Free-Running- output compare registers. The output such as frequency can be taken. The Timer (FRT) with 4 IC and 2 OC and 3 compares work by producing an user can be sure that the accuracy of timers with 8-bit. A separate 14-bit output of a pre-programmed level the measurement is not compromised PWM and 2 WDT (one with 32KHz and/or an interrupt when the value by interrupt response time, as it is subclock) are also provided. in the counter matches the value entirely a hardware driven facility. stored in one of the output compare It is also possible to initiate DMA Together with the large integrated registers. The events that can be transfers when an input capture event memories and the other peripherals, initiated by these compare matches occurs. This allows time stamps to be these powerful timers are aimed at are transitions on an output pin (to automatically placed in memory via making single-chip systems possible, high, to low or toggle), a CPU the DMA controller, without needing where previously microncontrollers with interrupt (used for software timing to interrupt the CPU. additional external devices had to be functions), clearing the counter and

16 • Timer Synchronisation The table below shows the PWM frequencies which can be obtained versus device clock speed and output resolution. To allow timer channels in the ITU PWM 16 12 10 8 6 to be used in synchronisation, it is Res. MHz MHz MHz MHz MHz possible to set up two or more timers 14-bit 976. 5 Hz 732. 7 Hz 610 Hz 488 Hz 365 Hz so that they are simultaneously 12-bit 3. 9 KHz 2. 9 KHz 2. 4 KHz 2 KHz 1. 5 KHz written to via software and cleared by 10-bit 15. 6 KHz 11. 7 KHz 9. 7 KHz 7. 8 KHz 5. 8 KHz compare matches or input captures. 9-bit 31. 2 KHz 23. 4 KHz 19. 5 KHz 15. 6 KHz 11. 7 KHz When timer channels are put into this 8-bit 62. 4 KHz 46. 9 KHz 39 KHz 31. 3 KHz 23. 4 KHz mode then their input and output 7-bit 124. 8 KHz 93. 8 KHz 78 KHz 62. 5 KHz 46. 8 KHz events are also synchronised.

• Standard PWM Mode TCNT3 value Counter cleared at compare match with GRA3 Each timer channel can be GRA3 programmed to produce a single GRB3 phase PWM output. Thus the ITU GRA4 can output up to ﬁve separate GRB4 channels of PWM. In this mode H'0000 Time GRA controls the time when the pin TIOCA goes high, and GRB when the pin 3 goes low. Either GRA or GRB can TIOCB3 be set to clear the counter, thus

setting the frequency of the WM TIOCA4 output. TOCXA4 • AC Motor Control Outputs TIOCB To provide the PWM signals required 4 to drive AC machines, the ITU TOCXB4 provides two further PWM modes: Complementary 6-phase PWM and Figure 15 Reset Synchronised 6-phase PWM (shown in Figure 15). The main By utilising the phase counting mode This facility removes the requirement for differences between these two modes on the ITU, TCNT2 will count up extra hardware or interrupt handlers for are the transition points for the or down depending on the phase position monitoring. In this mode the outputs and the provision of dead of the incoming signals. Therefore, comparators of channel 2 can also be time between the phase outputs. the value of TCNT2 will reﬂect the used to generate interrupts, for example positional changes experienced by the when a certain position is reached. • Phase Counting Mode encoder. This mode ﬁnds use in servo control systems, where the position and speed feedback comes from a 2- phase TCNT2 value quadrature encoder. In this type of Counting up Counting down encoder the waveforms output change their phase relationship depending on the direction of motion, as shown in Time Figure 16 TCLKB TCLKA Figure 16

17 Modified ITU on set the duty. reset H8/306x, H8/3006 However, as the ITU puts more emphasis • Cascading of both channels to form a and H8/3007 on motor control and similar 16-bit timer applications, the TPU does not support • Channel 1 can also be used to count The ITU on H8/306x, H8/3006 and ‘Reset synchronized 6-phase PWM channel 0 compare matches H8/3007 are modified to be more mode’ and ‘Complementary 6-phase flexible. Channels 3 and 4 can be split PWM mode’. These 8-bit timers can also be used to into 4 timer channels (8-bit) instead of 2 keep up a minimum level of timer timer channels (16-bit). However, this 16-bit Free Running functionality in times of low activity of modified ITU does not have the special Timer (FRT) the overall system. The result is lowest AC motor control modes power consumption on one hand, (Complementary 6-phase PWM and The main timer unit of H8S/21xx is the because the TPU can be switched off in Reset Synchronised 6-phase PWM). The 16-bit Free Running Timer (FRT), with that situation, but a minimum of timer buffering facility has also been removed. 2 OC and 4 IC. The input capture activity on the other hand. The 8-bit facility can also be operated in buffered timer could be used to update a software Timer Pulse Unit mode, with only 2 IC available in this real time clock, for example, or scan a (TPU) case. keyboard, so that the system can return Input clock can be selected from 3 to full activity when a key has been The TPU is similar to the ITU, yet even internal clocks and an external clock, pressed. more powerful and flexible. It is found which also allows event counting. The on all H8S devices, with the H8S/224x FRT unit features one independent Enhanced 8-bit and the H8S/222x devices having only interrupt for each IC, OC and one on timers on H8S/21xx half of a TPU implemented. overflow. The TPU comprises six 16-bit timer H8S/21xx derivatives feature a similar 8 channels with a total of 16 Timer 8-bit timers bit timer module as described in the General Registers (TGR), each of which previous paragraph. However, it has a can act either as an output compare or The H8S/2655-series, H8S/2355 and 53, third 8-bit timer channel TMRY,which an input capture function. Some TGR’s H8S/224x, H8S/234x and H8S/21xx all has similar functionality like TMR0 and can also act as buffer registers to reduce have an additional 8-bit timer module TMR1, but no output pin that is under the interrupt load that is put onto the with two channels (TMR0 and TMR1). control of the compare match facility. CPU. Each channel has two time constant For each channel one out of eight input registers (TCORA and TCORB) that 14 bit PWM timer clocks can be selected in software. are constantly compared with the Possible sources are internal clocks, counter value to detect compare H8S/21xx is equipped with a two external clock pins or overflow of other matches. The 8-bit timer module can channel PWM timer, intended for use as timers, the latter effectively providing a perform a variety of functions, including a digital-to-analog converter. It is based method to cascade two 16-bit timers to pulse output with an arbitrary duty cycle on a 14-bit counter, thus enabling low- form 32-bit timers. or counting events on an external pin. ripple, 14-bit resolution analog signals to While the ITU provides one channel for be generated. phase counting the TPU provides four. The 8-bit timer module has the Also, the TPU allows to trigger an A/D following features: Watchdog Timer conversion and can trigger data transfers • Selection of internal clock phi/8, (WDT) on H8/300H by the Data transfer controller (DTC). phi/64, phi/8192 or an external clock The TPU allows to generate a 15-phase input. Often, a watchdog timer is a very PWM signal, by using one TGR as the • Selection of counter clear sources: important feature in any embedded cycle register and the other 15 TGR’s to compare match A or B, or external application. It is used to ensure that any

18 “mishap’ in the system (such as a noise seconds. This WDT can request an induced software crash) is rectified as interrupt, reset or NMI. If an interrupt quickly as possible. is requested this WDT is useful to update The principle behind a watchdog timer a software real time clock. For this is very simple - a counter is constantly usage, every peripheral module on the counting upwards, and correctly device is turned off and the CPU is operating software ensures that this brought into sleep mode. Then the counter never overflows by continuously WDT wakes up the CPU every second, resetting the count. If the software for example, the CPU updates the the crashes and the counter overflows, the software real time clock registers (usually watchdog “barks” and sends some kept in RAM) and goes to sleep again, if stimulus to the microcontroller (normally no other activity is pending. a reset) to restart system operations in a controlled manner. All H8/300H devices are equipped with a timer, which can be used either as a watchdog or as an interval timer. Its ‘bark’ is a reset if it is used as a watchdog. If used as interval timer, each overflow generates an interrupt.

Watchdog Timer (WDT) on H8S

The WDT on H8S has some improvements over the WDT on H8/300H. It has an WDTOVF-pin that can signal the watchdog overﬂow to the outside world. It can select much slower clock sources up to phi/131072, which allows up to 1. 68s (at 20MHz) for the software to reset the watchdog before overﬂow.

Watchdog Timer (WDT) operating on 32KHz subclock

On some H8S derivatives a second WDT is implemented, which is operating off a 32KHz subclock. This subclock can be divided by 2 to 256 before it is used as counter input clock. Hence, the ﬁnal overﬂow rate can be as low as 32KHz divided by 256x256 = once every two

19 Timing Pattern Controller (TPC) Programmable Pulse Generator (PPG)

These peripherals allow to generate Stepper Motor between new patterns being output to digital output signals in synchronisation Control with the allow acceleration and deceleration of the with a timer pulse, so that one could look TPC motor as shown by the velocity proﬁle. at them as ‘real time outputs’. Such a Figure 17 shows how stepper motor timer-driven digital output system allows control can be performed using the ITU, When the TPC, ITU and DMAC are to generate a continuous stream of data TPC and DMAC . In this example a working together, the acceleration and that appears on the pins precisely in the two phase stepper motor is being driven, deceleration phases, as well as the steady intervals that the timer is programmed to, using complementary transistors. It is speed phase can be controlled with without any ‘jitter’ that would be caused therefore necessary to provide a dead minimal CPU overhead. The CPU only by e. g. interrupt latencies in a system time between the switching of the phases needs to get involved when a transition where an interrupt service routine drives to eliminate any short circuit conditions from one phase to another is made. This the pins. Also the TPC and PPG allow to between the high side and low side is achieved by using a second memory to do this without any CPU intervention, if drivers. I/O DMA channel to reload the timer used together with DMA. compare register The TPC and PPG provide registers Memory after each new

called the ‘Next Data Register’. The data output pattern pattern has been data table DMA in these registers will be transferred under ITU Channel O output. Again the timer control to the ‘Port Data Registers’ OCRA DMAC can take the Clock (i. e. to the pins). The CPU, the DMA DMA next step period data OCRB Channel O or the DTC (where applicable) then have step pulse period TPC from a table of values data table pins time until the next ‘timer tick’ to copy DMA motor stored in the DMA Channel O control the next value from a data table in Channel 1 pulses memory of the memory to the ‘Next Data Register’. OCRA hosts Non-Overlap time system. Therefore, Data flow trigger OCRB holds step pulse time This mechanism works independently for by providing a table Figure 17 four groups of four pins each, so that a of increasing or decreasing values the total of 16 pins can be driven in that way. Using compare matches from the ITU to motor can be decelerated or accelerated The TPC and the PPG are ﬁrst of all stimulate the DMAC, new pattern data is with no CPU intervention (Figure 18). intended to drive stepper motors (up to provided to the TPC. This pattern data Motor velocity profile four) with only very little CPU represents the next phase drive pattern Revolutions intervention required. However, they can required, and is stored in a memory table. CPU intervention required be used in many different ways as well. It The DMAC uses its memory to I/O is quite easy, for example, to generate a function to transfer this data on each compare match. The TPC also uses the serial data stream if an additional serial Acceleration Deceleration interface is required. It is even possible to stimulus from the ITU to transfer the drive an LCD module without using any contents of the NDR to the port. Using LCD timing controller, thus eliminating a a TPC mode where transitions on the Figure 18 Differences entire peripheral chip in a microcontroller port from 0 to 1 (i. e. switching on a between H8/300H system that is to be connected to an LCD phase) are only made on compare match TPC and H8S PPG module. Such an application is described A, a dead time, equal to the value in in Hitachi’s application note No. 55 GRA, is inserted. The difference between the H8/300H TPC (using Hitachi’s SH microcontroller). When controlling a stepper motor, and the H8S PPG is mainly the addition of Hitachi’s application note No. 56 shows providing the phase patterns onto the the bit inversion to each output. how to set up such a TPC/ITU/DMA port pins is only part of the story. It is Also, the PPG is supported by the H8S system using MakeApp. also necessary to modify the time DMA as well as the DTC.

20 Serial Communications Interface (SCI)

This form of communication has many H8/300H H8S H8S/21xx uses in microcontroller applications, such Smart card interface H8/3048 series Yes No as inter-device communications, (ISO 7816) diagnostics, host communication or as an Multi-processor mode Yes Yes Yes interface to peripherals. All of Hitachi’s IIC No H8S/2238 H8S/21x7, 8 16-bit microcontrollers have at least one H8S/2633 SCI, even though most have two or IrDA No H8S/2633 Yes more. The SCI’s on H8/300H and H8S LSB/MSB-first selectable* No Yes Yes can operate in asynchronous (‘UART’) No. of SCI with 1 min. 2 No or synchronous mode. DMA support DTC support No Yes H8S/21x7, 8 They have independent baud rate * This feature allows to connect SPI compliant peripherals in most cases. generators, so that none of the general purpose timers is used up to generate transmit/receive clocks, and external 20MHz for H8/300H and over 4Mbit/s to the data transmitted. This bit is used clocking is also possible. They are double at 25MHz for H8S. to differentiate between data frames and buffered to allow ‘back-to-back’ address frames. Thus, any frame sent transmission. Break detection is possible The H8S and the H8/300H serial ports from the master with the MPB set to by reading the RxD pin level after a also support multiprocessor one can be used to activate the required framing error has been detected. communications using a master slave slave. To allow efficient SCI service by configuration in addition to the standard Slave devices on this network will only interrupt service routines each SCI is modes. produce a receive interrupt when a frame provided with 4 different interrupts, each is received with the MPB set, so the with its own interrupt vector. These are In this mode, communication between interrupt handler can check the address transmit-data-empty, transmit-end, devices is performed using an additional which has been transmitted. receive-data-full and receive error. multiprocessor bit (MPB) which is added Receive data errors are trapped using three error conditions -overflow, framing Figure 19 and parity. These three errors are indicated via one interrupt vector and Transmitting three status flags in the serial status station register. Serial transmission line

Some other capabilities vary from family to family, as shown in the table. Receiving Receiving Receiving Receiving station A station B station C station D (ID= 01) (ID= 02) (ID= 03) (ID= 04) The maximum bit rate in asynchronous Serial operation is 625kbit/s at 20MHz for data H'01 H'AA H8/300H and 781kbit/s at 25MHz for (MPB= 1) (MPB= 0) H8S, using the internal BRR. Using ID transmission cycle= Data transmission cycle= external clocks the values for receiving station Data transmission to asynchronous mode are half of that. For specification receiving station specified by ID synchronous operation with external Legend MPB: Multiprocessor bit clock the bit rate is 3.33Mbit/s at

21 Memory Type and Size

H ROM-LESS or pseudo ROM-LESS(*) H Mask-ROM H OTP and Mask H Flash and Mask (H8S/2623,33 Flash only) (UD) Under Development

22 H8S and H8/300H Selector

(UD) Under Development

Device H8/3001 H8/3002 H8/3003 H8/3004,5 H8/3006,7 H8/3020,1,2 (UD) ROM (byte) -----128,192,256k RAM (byte) 512 512 512 2,4k 2,4k 4,4,8k OTP (HD647…) or FLASH (HD64F…) -----HD64F3022

Vcc (V) / clock (MHz) 4.5-5.5/16 4.5-5.5/16 4.5-5.5/16 4.5-5.5/16 4.5-5.5/20 3.0-3.6/18 (During Operation) 3.0-5.5/13 3.0-5.5/10 3.0-5.5/10 4.5-5.5/18 3.0-5.5/13

2.7-5.5/8 2.7-5.5/8 2.7-5.5/8 3.0-5.5/10 2.7-5.5/10

2.7-5.5/8

Flash Programming Voltage (V) Vcc=3.0-3.6

External data bus (bit) 8/16 8/16 8/16 8 8/16 8 ITU / TPU / FRT (16-bit timer) 555535

no of input capture/output compare 10 IC/OC 10 IC/OC 10 IC/OC 10 IC/OC 6 IC/OC 10 IC/OC

8-bit timer - - - - 4 with 2 IC / 4 OC -

Watchdog timer -11111 14-bit PWM (channel) ------

DMAC (channels) Memory to/from I/O -48-4-

Memory to Memory -24-2-

DTC ------Bus Master Timer Vcc/Clock Memory SCI (async/sync channels) 122132 Smart card i/f (channels) ----32 IIC (channels) ------Serial IrDA (channels) ------Communication CAN V2.0B (channels) ------10-bit ADC (channels) 488888 8-bit DAC (channels) ----2- TPC (bit) / PPG (bit) 12 16 16 - 16 15 Refresh controller /DRAM interface - Yes Yes - Yes - Chip select pins -48-8-

Interrupts Internal 20 30 34 21 36 25

External 479675

I/O pins (incl. input only pins) 32 46 58 32 79 63 Other Features Analog Others

Data book 21-092 21-078 21-033A 21-106 21-117 TBA Package FP-80A FP-100B FP-112 FP-80A FP-100B FP-80A

TFP-80C TFP-100B TFP-120 TFP-80C TFP-100B TFP-80C

23 ** For availability of mask ROM versions, please contact your Hitachi sales ofﬁce or authorized distributor Guide

H8/3030,1,2 H8/3033,4,5 H8/3036,7,8,9 H8/3040,1,2 H8/3044,5,7,8 H8/3052 (UD) H8/3060,1,2 H8/3065,6,7 H8S/2120,2,3,4,6,7,8** 16,32,64k 128,192,256k 16,32,64,128k 32,48,64k 32,64,98,128k 512k 64,96,128K 64,96,128K 32,64,128,96,32,64,128k

512,1k,2k 4k 512,1,2,4k 2k 2,2,4,4k 8k 2,4,4k 2,4,4k 2,2,4,4,2,2,4k

HD6473032 HD6473035 HD64F3039 HD6473042 HD6473048 HD64F3052 HD64F3062 HD64F3067 HD64F2128

HD64F3048

4.5-5.5/16 4.5-5.5/18 4.5-5.5/18 4.5-5.5/16 4.5-5.5/16 3.0-5.5/18 4.5-5.5/20 4.5-5.5/20 4.5-5.5/20

3.0-5.5/10 3.0-5.5/10 3.0-5.5/10 3.0-5.5/10 3.15-5.5/13* 3.0-5.5/13 3.0-5.5/13 2.7-5.5/10*

2.7-5.5/8 2.7-5.5/8 2.7-5.5/8* 2.7-5.5/8 2.7-5.5/8 2.7-5.5/8* 2.7-5.5/8* (* mask only)

(* mask only) (* mask/OTP only) (* mask only) (* mask only)

Vcc=3.0-3.6 or 4.5-5.5 Vpp=12V Vcc=3.0-3.6 Vcc=3.0-3.6 or 4.5-5.5 Vcc=3.0-3.6 or 4.5-5.5 Vcc=4.5-5.5

8 8 8 8/16 8/16 8/16 8/16 8/16 8

555 5 5 5 3 3 1

10 IC/OC 10 IC/OC 10 IC/OC 10 IC/OC 10 IC/OC 10 IC/OC 6 IC/OC 6 IC/OC 4 IC / 2 OC

------4 with 2 IC / 4 OC 4 with 2 IC / 4 OC 3 on 2120,2,3,4

4 on 2126,7,8

111 1 1 1 1 1 2

------2 on 2126,7,8

--- 4 4 4 - 4 -

--- 2 2 2 - 2 -

------1 on 2126,7,8

112 2 2 2 2 3 2

--1 - 1 2 2 3 -

------2 on 2126, 7, 8

------

888 8 8 8 8 8 8

--- 2 2 2 2 2 -

16 16 15 16 16 16 16 16 -

- - - Yes Yes Yes - Yes -

--- 4 8 8 8 8 -

21 21 25 30 30 30 27 36 29 (33 on 2126,7,8)

665 7 7 7 7 7 4

63 63 63 78 78 78 79 79 51

3040x00 pseudo 3044x00 pseudo ADC 16ch x6bit mode

ROM-less avail. ROM-less avail. subclock mode

21-093 21-111 21-114 21-036 21-095A TBA 21-116 21-115 18-016

FP-80A FP-80A FP-80A FP-100B FP-100B FP-100B FP-100B FP-100B DP-64S

TFP-80C TFP-80C TFP-80C TFP-100B TFP-100B TFP-100B TFP-100B TFP-100B FP-64A, TFP-80C H8S/2130,2,3,4,7,8** H8S/2142,3,4,7,8** H8S/2223,5,7 H8S/2233,5,7 H8S/2238 H8S/2240,1,2,3,4,5,6 H8S/2310,2 H8S/2322,3,7,8 H8S/2340,1,3,5 H8S k 32,64,96,128,64,128k 64,96,128,64,128k 64,128,128k 64,128,128k 256k 0,32,32,64,64,128,128k - 0,32,128,256k 0,32,64,128k 0

2,2,4,4,2,4k 2,4,4,2,4k 4,4,16k 4,4,16k 16k 4,4,8,4,8,4,8k 2,8k 8k 2,2,2,4k

HD64F2138 (128k) HD64F2148 (128k) HD6472237 HD6472237 HD64F2238 HD6472246 - HD64F2328 HD6472345

HD64F2134 (128k) HD64F2144 (128k) HD64F2345

HD64F2132 (64k) HD64F2142 (64k)

4.5-5.5/20 4.5-5.5/20 2.7-3.6/13 2.7-3.6/13* 2.7-5.5/13 4.5-5.5/20 2.7-3.6/20 2.7-3.6/20 4.5-5.5/20 4.5

2.7-5.5/10 Mask 2.7-5.5/10 Mask 2.2-3.6/6* 2.2-3.6/6* 2.2-3.6/6* 2.7-5.5/13* 3.0-3.6/25 3.0-3.6/25 2.7-5.5/10* 2.7

3.0-5.5/10 Flash 3.0-5.5/10 Flash (* mask only) 2.7-3.6/10 (* mask only) 2.7-5.5/10 (*mask/OTP only)

(* mask only) (* mask only)

Vcc=3.0-3.6 or 4.5-5.5 Vcc=3.0-3.6 or 4.5-5.5 Vcc=2.7-5.5 or 2.7-3.6 Vcc=2.7-3.6 Vcc=4.5-5.5

8 8/16 8/16 8/16 8/16 8/16 8/16 8/16 8/16

113663666

4 IC / 2 OC 4 IC / 2 OC 8 IC/OC 16 IC/OC 16 IC/OC 8 IC/OC 16 IC/OC 16 IC/OC 16 IC/OC 16

3 on 2130,2,3,4 3 on 2142,3,4 2 with 2 OC 2 with 2 OC 4 with 4 OC 2 with 2 OC 2 with 2 OC 2 with 2 OC 2 with 2 OC

4 on 2137,8 4 on 2147,8

222221111

22------

------4-

------2-

1 on 2137,8 1 on 2147,8 Yes Yes Yes Yes Yes Yes Yes

333443232

--3443232

2 on 2137, 8 2 on 2147, 8 - - 2 - - - -

11------

------

888884888

22-22-222

------16-

------Yes-

--8888884

31 (43 on 2137,8) 34 (46 on 2147,8) 36 53 53 34 43 52 37

999999999

66 82 82 82 82 79 79 95 79

ADC 16ch x6bit mode ADC 16ch x6bit mode 32KHz subclock 32KHz subclock internal step down 2242x00 pseudo

subclock mode subclock mode 32KHz subclock ROM-less avail.

18-018 18-017 18-012 18-012 18-020 18-004 TBA 18-021/22 18-010 1

FP-80A FP-100B FP-100A, FP-100B FP-100A, FP-100B FP-100A, FP-100B FP-100B FP-100A FP-128 FP-100A, FP-100B F

TFP-80C TFP-100B TFP-100B TFP-100B TFP-100B TFP-100B TFP-100B TFP-120 TFP-100B, TFP-100GTF

TFP-100G TFP-100G TFP-100G S/2350,1 H8S/2353,5 H8S/2352,7 H8S/2623, H8S/2626 H8S/2633** H8S/2653,5 Device 0,64k 64,128k 0,128k 256k 256k 64,128k ROM (byte)

2k 2,4k 8k 12k 16k 4k RAM (byte) Memory - HD6472355 HD6472357 HD64F2623 HD64F2633 HD6472655 OTP (HD647…) or FLASH (HD64F…)

HD64F2357 HD64F2626

5-5.5/20 4.5-5.5/20 4.5-5.5/20 3.0-3.6/20 (Vcc) 3.0-3.6/25 (Vcc) 4.5-5.5/20 Vcc (V) / clock (MHz)

7-5.5/10 2.7-5.5/10 2.7-5.5/10* 4.5-5.5/20(PVcc) 4.5-5.5/25(PVcc) 2.7-5.5/10 (During Operation) Vcc/Clock

3.0-5.5/13 Flash

(*mask/OTP only)

Vcc=3.0-3.6 or 4.5-5.5 Vcc=3.0-3.6 Vcc=3.0-3.6 Flash Programming Voltage (V)

8/16 8/16 8/16 8/16 8/16 8/16 External data bus (bit) 66 6 6 6 6 ITU / TPU / FRT (16-bit timer)

6 IC/OC 16 IC/OC 16 IC/OC 16 IC/OC 16 IC/OC 16 IC/OC no of input capture/output compare

- 2 with 2 OC 2 with 2 OC - 4 with 4 OC 2 with 2 OC 8-bit timer Timer

11 1 1 2 1 Watchdog timer -- - - 4 - 14-bit PWM (channel) Bus Master 4- 4 - 4 4 DMAC (channels) Memory to/from I/O

2- 2 - 2 2 Memory to Memory

Yes Yes Yes Yes Yes Yes DTC 23 3 3 5 3 SCI (async/sync channels) Communication 23 3 3 5 3 Smart card i/f (channels)

-- - - 2 - IIC (channels) Serial -- - - 1 - IrDA (channels) -- - 1 - - CAN V2.0B (channels) Analog 88 8 16168 10-bit ADC (channels) 22 2 - 4 2 8-bit DAC (channels) 16 - 16 8 8 16 TPC (bit) / PPG (bit) Yes - Yes - Yes Yes Refresh controller /DRAM interface 88 8 - 8 8 Chip select pins Other Features

42 41 52 47 72 52 Interrupts Internal

99 9 7 9 9 External

95 95 95 70 89 95 I/O pins (incl. input only pins) PLL clock PLL clock 2655x00 pseudo Others

H8S/2626: 32KHz 32KHZ subclock ROM-less avail.

subclock

8-006 18-005 18-011 TBA TBA 18-001B Data book P-128 FP-128 FP-128 FP-100B FP-128 FP-128 Package

FP-120 TFP-120 TFP-120 TFP-120 TFP-120 In Brief

In this brochure an overview is given as • Very powerful and sophisticated in the industry for many years to come. to why H8S and H8/300H give you the peripherals designed to reduce CPU The road map points towards: technical beneﬁts that are demanded by overhead and hence to increase system • 33MHz at 3.3V H8S devices by the today’s applications.The purpose is to performance second half of 2000 give you enough insight into the features • High memory and peripheral • more large memory variants (up to of the H8S and H8/300H family to see integration to allow single-chip 512K Flash) within year 2000 how you can beneﬁt from the systems, where previously multi-chip • high-speed Flash as a standard ROM performance, the rich set of peripherals systems were necessary. Switching technology, as price is decreasing to and the memory options available.To from multi-chip to single-chip will fall from OTP levels towards mask summarise this: drastically reduce radiation, board • further decrease in power space requirements and enables the consumption by shifting Vcc to 2.2V • High performance CPU with usage of all pins as ports instead of and by adding 32kHz subclock architecture tailored for high level using them as busses. • future peripherals including 2x language software development • Full European technical and tool CAN-derivatives, high-current • Industry leading low power, low support provided by Hitachi stepper motor drivers, on-chip voltage options Microsystems Europe (HMSE) in LCDC and much more.As an • Memory line up from 16K to 256K Maidenhead (UK) example the road map below shows ROM and 512Byte to 16K RAM, There is a strong road map that underlines Hitachi’s 16-bit microcontrollers including many Flash versions up to Hitachi’s commitment to H8 as an with integrated CAN. 256K Flash architecture that will be a dominant player

H8S & CAN derivatives

Dashboard applications.

Under development. H8S/2646F 128KB/4KB 1 x HCAN General purpose/Industrial ABS, EPAS, suspension, + LCDC clutch etc...

Under development. H8S/2626F H8S/2636F 256KB/12KB 128KB/4KB 1 x HCAN 2 x HCAN + subclock Body electronics, EPAS, etc Planned. H8S/2623F H8S/261xF 256KB/12KB 128KB/4KB 1 x HCAN 1 x HCAN

QFP-100 QFP-128 QFP-144 QFP-80

27 Smart card time normally used as stop bits, thus putting the smart card’s reset under interface ISO7816-3 implements an error bit. host software control. mode (SIM) That means, that a low level on the Also, a general purpose IO of the host is RxD/TxD line at a particular position used to control a MOSFET that turns on In this mode the SCI conforms to a sub- after the data bits has to be recognised and off the power to the smart card. In set ISO7816-3. This standard is used to by the transmit side as an error in banking applications another MOSFET communicate with so called smart cards, reception on the receive side. The may be used to power a card ejection which are frequently used in banking transmitting side shall respond by mechanism. applications (electronic money), GSM retransmitting the last data. The SCI in H8/3048 and ﬁrst-generation H8S phones and many other applications like SIM mode also supports direct and products have the following limitations: building entry control or for ‘loyalty inverse convention as set out by ISO 1) The only available speed of the SIM cards’. Because these applications are 7816-3. is the default value of clock/372 and expected to grow very rapidly in the The physical interface between the host 2) There is no support for the so called next few years, Hitachi has equipped all and the smart card comprises the protocol T=1“ ” H8S devices with SCI’s that can be set to RxD/TxD pins tied together and then Latest H8S products add 3 new speeds SIM mode. connected to the I/O pin of the smart (clock/32, 64 and 256) and support for According to ISO 7816-3, the card, a clock that must be provided to T=1“.These are the H8S series ” communication used is asynchronous, the smart card and initially has to be 372 H8S/222x, H8S/223x, H8S/231x, half-duplex (i. e. only either the host or times the baudrate and a reset signal. H8S/232x, H8S/263x and all future H8S the smart card transmits at a time) and Reset is not tied to the reset pin of the products. with even parity always. Also, after host microcontroller, but is connected to transmission of the data and within the a general purpose IO pin of the host,

Vcc Figure 20

TxD0 I/O RxD0 Data Line SCK0 CLK Px (Port) Clock Line RST H8S Reset Line

Vcc Vcc I/O MOSFET

IC card

28 Analogue to Digital Converter (ADC)

In many microcontroller based systems, High speed ADC on • Simultaneous sampling operation some way of measuring analogue H8S/2655 allows the two S&H to sample electrical values is necessary. With this in simultaneously. An important feature mind, all members of the H8S and On H8S/2655 Hitachi has implemented in some applications, e. g. where at H8/300H families are equipped with a a new high speed ADC, capable of least 2 out of the 3 phases of a 3- 10-bit A/D converter, in most cases with sustaining a conversion rate of 1 million phase mains have to be observed. an 8 (up to 16) channel analog samples per second. This is achieved by • Conversion can be triggered by multiplexer to allow numerous signals to using two sample and hold (S&H) software, an external pin or the on- be processed easily. The converter works circuits which are used interleaved, i. e. chip timers using a successive approximation while S&H A is sampling, S&H B is algorithm and conversions take 138 states being converted. Digital to Analogue (or 8. 6µs if ø - 16MHz, respectively 6. Converter (DAC) 7µs at 20MHz in case of H8S). A sample But not only is this new ADC faster , but and hold circuit is used to ensure that it has also new features to make it more The H8/304x derivatives within once a conversion begins, a change of flexible. H8/300H and most H8S derivatives the input value will not be reflected in a These new features include: feature a two channel, 8-bit resolution different conversion result. A conversion • 8 A/D data registers to store the Digital-to-Analog-Converter (DAC). can be initiated by software or by means results of each channel individually The conversion time is 10µs with a 20pF of an external trigger input, and in some • Enhanced conversion modes, created load and the output voltage range is 0V devices by the timer unit. At the end of by combining ‘select’ (one channel) or to Vref. The outputs can be maintained the conversion an interrupt may be ‘group’ (more than one) with ‘single’ during software standby. requested. (one shot conversion) or ‘scan’ (continuous conversion). Both channels can be enabled or disabled As well as being able to perform single • Select single mode: one shot independently. Once a channel is conversion (single mode, where only one conversion of one channel enabled, the corresponding pin becomes channel is converted), the A/D • Select scan mode: continuous an analog output pin and the data in the converter can also be used to scan up to conversion of one channel D/A data register (DADR) is output at four channels (scan mode). To support • Group single mode: one shot the pin after the D/A conversion time this mode of operation, four A/D result conversion of a number of has elapsed. The pin remains in that state registers (ADDRA to D) are provided. channels until DADR is written to again or until Once the scan mode is selected, each • Group scan mode: continuous the D/A channel or the complete DAC channel specified is converted conversion of a number of is disabled. sequentially with the conversion value channels being stored in the appropriate result • Buffer operation allows to store results The voltage at the D/A output pin can register. This mode of operation allows in FIFO-fashion in the ADDR be calculated as DADR contents x Vref. 256 the user software to sample the current registers. Double or quadruple analogue value of an input by simply buffering can be selected. reading the appropriate data register.

29 Controller Area Network CAN

The HCAN module (Hitachi CAN)* likelihood of such a case increases in Hitachi’s HCAN module implements the complies to version 2.0B (Full CAN) as proportion to the length of the message. CAN standard by adding sophisticated defined by Bosch.Additionally, an Also, short messages keep latency low. features, which allows usage in even the independent institute has tested the Depending on the actual baudrate most demanding automotive applications HCAN module for compliance with the chosen, the length of the network can like engine management. It features: standard. CAN (Controller Area vary between approximately 40m and Network) has become a widespread 1000m (also depending on the • 15 programmable receive/transmit standard in the European automotive transceivers chosen). buffers industry, because it provides very reliable, CAN allows broadcasting or • 1 receive-only buffer with local high-speed, low-latency serial multicasting, i.e. sending messages to all acceptance filtering (LAFM) communication for harsh and or some nodes at a time, hence allows • internal priority sorting to avoid electromagnetically polluted synchronisation of the activities of several priority inversion environments.Therefore CAN has begun nodes. • flexible interrupt structure to keep to penetrate also industrial applications, A key feature of CAN is the CPU load to a minimum where these features are important. prioritisation of messages that allows • sleep-mode and auto wake-up, if CAN is a non-return to zero (NRZ), bit important messages to gain access to the CAN bus is active stuffing protocol for message-orientated physical bus with very short latency. • DMA support for mailbox 0 to serial communication via two wires, at CAN also allow arbitration of multiple reduce CPU overhead speeds of up to 1Mbit/s. Each message messages that are trying to occupy the Special emphasis was put on good real contains up to 8 Byte of user data. Using bus simultaneously. The arbitration time capabilities.An internal state these short messages is important in mechanism will inherently grant access machine sorts the messages by priority to harsh environments, where disruption or to the bus for the highest priority avoid the inherent priority-inversion noise could destroy a message, as the message. problem.

HCAN

MBI (CDLC) Message buffer CAN Mailboxes Data Link Controller Message control LAFM Bosch CAN 2.0Bactive Message data MC0–MC15, MD0–MD15 Tx buffer HTxD Peripheral data bus MPI Peripheral address bus Rx buffer HRxD Microprocessor interface CPU interface Control register Status register

* For a complete Roadmap of H8 microcontrollers with HCAN please refer to page 27.

30 H8/3039

Lowest cost H8/300H with Flash 7 6 5 4 3 2 1 0 /D /D /D /D /D /D /D /D 7 6 5 4 3 2 1 0 SS SS SS CC CC P3 P3 P3 P3 P3 P3 P3 P3 V V V V V

Port 3 ROM 16k-128k, RAM 512Byte- Address bus

4k, 128K Flash MD2 Data bus (upper) MD1 18MHz clock yields 111ns min. Data bus (lower) P53/A19 MD0 instruction EXTAL P52/A18 P5 /A XTAL Port 5 1 17 pin compatible with other P50/A16 ¿ H8/300H CPU H8/303x, but with 2x SCI STBY Bus controller RES Clock osc. popular ITU timer unit with AC RESO/FWE* motor drive modes NMI P27/A15 P2 /A Interrupt 6 14 Ideal for many industrial P2 /A ROM controller 5 13 (Flash memory, P24/A12 applications P65/WR masked ROM) P23/A11 P64/RD Port 2 P22/A10 P63/AS P21/A9 P60/WAIT Watchdog P20/A8 timer P17/A7 RAM (WDT) P16/A6 P15/A5 P14/A4 Serial P1 /A

Port 1 3 3 16-bit communication integrated P12/A2 P81/IRQ1 interface P11/A1 P8 /IRQ timer unit (SCI) x 2 channels 0 0 Port 8 Port 6 (ITU) P10/A0

Programmable A/D converter P95/SCK1/IRQ5 timing pattern P94/SCK0/IRQ4 controller (TPC) P93/RxD1 P92/RxD0 Port 9 P91/TxD1 P90/TxD0

Note: * Masked ROM : RESO Port B Port A Port 7 Flash memory: FWE 4 4 4 4 7 6 5 4 3 2 1 0 3 3 20 21 22 23 SS CC /A /A /A /A /AN /AN /AN /AN /AN /AN /AN /AN 2 2 1 1 AV AV 7 6 5 4 3 2 1 0 /TCLKB /TCLKA /TCLKD /TCLKC P7 P7 P7 P7 P7 P7 P7 P7 /TIOCB /TIOCA /TIOCB /TIOCA /ADTRG 1 0 0 0 /TOCXB /TOCXA 9 8 11 10 15 13 12 /TP /TP /TIOCB /TIOCA /TIOCB /TIOCA /TP /TP 1 0 7 6 5 4 /TP /TP 1 0 /TP /TP /TP 3 2 7 5 4 PA PA /TIOCB /TIOCA PB PB /TP /TP /TP /TP 3 2 PB PB PB 7 6 5 4 PB PB /TP /TP PA PA PA PA 3 2 PA PA

H8/3067 15 14 13 12 11 10 9 8 Enhanced successor of popular 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CC CC CC SS SS SS SS SS SS

H8/3048 V V V V V V V V V P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D P3 /D P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D P4 /D

Port 3 Port 4 nearly pin compatible with Address bus H8/3048 P5 3 /A19 MD Data bus (upper) 2 P5 2 /A18 single voltage Flash requires no MD 1 Data bus (lower) Port 5 P5 1 /A17 Vpp MD0 P5 0 /A16 20MHz clock for 20% higher EXTAL XTAL P2 7 /A15 performance STBY P2 6 /A14 H8/300H CPU RES P2 5 /A13 now 3x USART, modiﬁed timers generator FWE*/RESO Clock pulse P2 4 /A12

without AC motor drive modes NMI Port 2 P2 3 /A11 P2 2 /A10 Lower cost variant H8/3062 Interrupt controller φ/P67 P2 1 /A9 without DMA and with 2x SCI LWR/P66 DMA controller P2 0 /A8 please refer to application note HWR/P65 (DMAC) Bus controller P1 /A RD/P64 ROM 7 7 APPS/072/1.0 AS/P6 (mask ROM or P1 6 /A6 3 Port 6 flash memory) P1 /A BACK/P62 5 5 P1 /A BREQ/P61 4 4

Port 1 P1 /A WAIT/P60 3 3 P1 2 /A2 RAM P1 1 /A1 CS0/P84 Watchdog timer P1 0 /A0 ADTRG/CS1/IRQ3/P83 (WDT) CS2/IRQ2/P82 16-bit timer unit CS /IRQ /P8 Port 8 3 1 1 Serial communication RFSH/IRQ0/P80 interface 8-bit timer unit (SCI) × 3 channels P9 5 /SCK 1 /IRQ5 P9 4 /SCK 0 /IRQ4 Programmable A/D converter timing pattern P9 3 /RxD1 controller (TPC) D/A converter Port 9 P9 2 /RxD0 P9 1 /TxD1 P9 0 /TxD0

Note: *Functions as RESO in the mask ROM versions and as FWE in the Port B Port A Port 7 flash memory version.

3 1 3 2 1 0 2 7 6 5 4 0 5 6 7 4 7 6 5 4 3 2 1 0 SS CC REF /P7 /P7 /P7 /P7 /P7 /P7 /P7 /P7 /PB /PB /PA /PA /PA /PA /PB /PA /PA /PA /PA /PB /PB /PB /PB /PB V AV 7 6 5 4 3 2 1 0 AV 9 3 2 1 0 7 6 5 4 8 11 10 13 14 15 12 AN AN AN AN AN AN /TP /TP /TP /TP /TP /TP /TP /TP /AN /AN /TP 1 0 0 /TP 2 2 1 1 0 /TP /TP 1 0 3 2 2 2 DA DA TxD RxD /TMO /TMIO UCAS/TP /LCAS/TP /TMO 7 /TCLKB/TP /TCLKA/TP /TMIO 0 /TIOCB /TIOCA /TIOCB /TIOCA 2 5 1 0 1 20 21 22 23 CS CS A A A A SCK TEND TEND /DREQ TCLKD/TIOCB TCLKC/TIOCA /DREQ 6 4 CS CS 31 H8S/2134 VCC VCC VSS VSS VSS

Very low cost H8S device in 80-pin package

RES high performance CPU delivering XTAL 6 MIPS Dhrystone EXTAL 64k/128K single voltage Flash, MD1 H8S/2000 CPU 2K/4K RAM and several ROM MD0 NMI sizes STBY Bus controller Clock pulse generator P27/A15 Internal data bus IrDA compliant infra red Internal address bus P26/A14 P25/A13 interface P97/WAIT Interrupt P24/A12 P96/¿/EXCL controller subclock mode Port 2 P23/A11 P95/AS/IOS P22/A10 also version with IIC, DTC and P94/HWR P21/A9

P93/RD Port 9 P20/A8 enhanced timers (H8S/2138) P92/IRQ0 ROM nearly pin compatible with P91/IRQ1 WDT0, WDT1 P17/A7 P90/LWR/IRQ2/ADTRG P16/A6 H8/3337 series P15/A5 P67/CIN7/KIN7/IRQ7 RAM P14/A4 P66/FTOB/CIN6/KIN6/IRQ6 Port 1 P13/A3 P65/FTID/CIN5/KIN5 P12/A2 P64/FTIC/CIN4/KIN4 P11/A1

P63/FTIB/CIN3/KIN3 Port 6 P10/A0 P62/FTIA/CIN2/KIN2/TMIY 16-bit FRT P37/D15 P61/FTOA/CIN1/KIN1 P36/D14 P60/FTCI/CIN0/KIN0 14-bit PWM P35/D13 P47/PWX1 P34/D12

P46/PWX0 Port 3 P33/D11 P45/TMRI1 8-bit timer x 3ch P32/D10 P44/TMO1 (TMR0, TMR1, TMRY) P31/D9

P43/TMCI1 Port 4 P30/D8 P42/TMRI0/SCK2 10-bit A/D P41/TMO0/RxD2/IrRxD P40/TMCI0/TxD2/IrTxD SCI x 3ch 8-bit D/A (IrDA x 1ch) P52/SCK0 P51/RxD0 P50/TxD0 Port 5

Port 8 Port 7 AVCC AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80

H8S/2144 VCC VCC VCC VSS VSS VSS VSS VSS

Very low cost H8S device in 100-pin package PA7/A23/KIN15/CIN15 RES PA6/A22/KIN14/CIN14 high performance CPU delivering XTAL PA5/A21/KIN13/CIN13 6 MIPS Dhrystone EXTAL PA4/A20/KIN12/CIN12

Port A PA3/A19/KIN11/CIN11 MD1 64k/128K single voltage Flash, H8S/2000 CPU PA2/A18/KIN10/CIN10 MD0 PA1/A17/KIN9/CIN9 2K/4K RAM and several ROM NMI PA0/A16/KIN8/CIN8 STBY Bus controller sizes Clock pulse generator P27/A15

RESO Internal data bus IrDA compliant infra red Internal address bus P26/A14 P25/A13 P97/WAIT Interrupt interface P24/A12 P96/¿/EXCL controller Port 2 P23/A11 subclock mode P95/AS/IOS P22/A10 P94/HWR also version with IIC, DTC and P21/A9

P93/RD Port 9 P20/A8 enhanced timers (H8S/2148) P92/IRQ0 ROM P91/IRQ1 WDT0, WDT1 P17/A7 nearly pin compatible with P90/LWR/IRQ2/ADTRG P16/A6 H8/3437 series P15/A5 P67/CIN7/KIN7/IRQ7 P14/A4 RAM P66/FTOB/CIN6/KIN6/IRQ6

Port 1 P13/A3 P65/FTID/CIN5/KIN5 P12/A2 P64/FTIC/CIN4/KIN4 P11/A1

P63/FTIB/CIN3/KIN3 Port 6 P10/A0 P62/FTIA/CIN2/KIN2/TMIY 16-bit FRT P37/D15 P61/FTOA/CIN1/KIN1 P36/D14 P60/FTCI/CIN0/KIN0 14-bit PWM P35/D13 P47/PWX1 P34/D12

P46/PWX0 Port 3 P33/D11 8-bit timer x 3ch P45/TMRI1 P32/D10 (TMR0, TMR1, TMRY) P44/TMO1 P31/D9

P43/TMCI1 Port 4 P30/D8 P42/TMRI0/SCK2 10-bit A/D PB7/D7 P41/TMO0/RxD2/IrRxD PB6/D6 P40/TMCI0/TxD2/IrTxD SCI x 3ch PB5/D5 8-bit D/A (IrDA x 1ch) PB4/D4 PB3/D3

P52/SCK0 Port B P51/RxD0 PB2/D2 P50/TxD0 Port 5 PB1/D1 PB0/D0

Port 8 Port 7

32 AVref AVCC AVSS P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80 H8S/2238 H8S/2237 RAM with large Super lowpower, lowvoltageH8S RAM, lowpowerH8S Generation 256K Flash,16K 3rd to 2.2Voperation mask derivativesavailabledown H8S/222x pin compatiblelowcostvariant subset ofISO7816-3 a (SCI),supporting 4 USART busses external RAMtoavoidusing large incl. 32KHzsubclock excellent powermanagement, 14mA (typ.)at3V/10MHz power consumptionaslow (H8S/222x), availablein2.2V low costmaskderivatives busses external RAMtoavoidusing large excellent powermanagement lowpowerconsumptionand very for 3to5Voperation advanced on-chippowersupply H8S/2237 series nearly pincompatiblewith PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/ PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PF0/BREQ/IRQ2 PF1/BACK/BUZZ PF2/WAIT PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/ PG0/IRQ6 PG1/CS3/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 ¿ ¿ FWE NMI RES STBY OSC2 OSC1 XTAL EXTAL MD0 MD1 MD2 FWE NMI RES STBY OSC2 OSC1 XTAL EXTAL MD0 MD1 MD2

CVCC VCC Port G Port F VCC Port G Port F VCC VSS VSS VSS VSS P10/TIOCA0/A20 P10/TIOCA0/A20 P11/TIOCB0/A21 P11/TIOCB0/A21 P12/TIOCC0/TCLKA/A22

P12/TIOCC0/TCLKA/A22 Port7 Port 1 ot1Port7 Port 1 P13/TIOCD0/TCLKB/A23 P13/TIOCD0/TCLKB/A23 TPU (6channels) TPU (6channels) P14/TIOCA1/IRQ0 System P14/TIOCA1/IRQ0 Subclock System

Subclock PC breakcontroller PC breakcontroller Interrupt controller Interrupt controller clock pulse clock pulse P15/TIOCB1/TCLKC clock pulse clock pulse P15/TIOCB1/TCLKC generator generator generator (2 channels)

(2 channels) generator P16/TIOCA2/IRQ1 P16/TIOCA2/IRQ1 ROM RAM ROM P17/TIOCB2/TCLKD RAM P17/TIOCB2/TCLKD

P70/TMRI01/TMCI01/CS4 P70/TMRI01/TMCI01/CS4 P71/CS5

P71/TMRI23/TMCI23/CS5 H8S/2000 CPU H8S/2000 CPU P72/TMO0/CS6 P72/TMO0/CS6 P73/TMO1/CS7 PD7/D15 P73/TMO1/CS7 PD7/D15 P74/MRES PD6/D14 P74/TMO2/MRES PD6/D14

P75/SCK3 Port D PD5/D13

P75/TMO3/SCK3 PortE Port D PD5/D13 P76/RxD3 A/D converter(8channels) D/A converter(2channels) PD4/D12 A/D converter(8channels) D/A converter(2channels) P76/RxD3 PD4/D12 8-bit timer(2channels) WDT0 8-bit timer(4channels)

P77/TxD3 DTC PD3/D11 WDT0 SCI (4channels) P77/TxD3 DTC PD3/D11 SCI (4channels) I PD2/D10 2

C businterface PD2/D10 Vref PD1/D9

Vref [option] PD1/D9 AVCC PD0/D8 AVCC PD0/D8 AVSS operation)

(subclock PE7/D7

AVSS WDT1 Internal data bus operation) (subclock PE7/D7 PE6/D6

WDT1 Internal data bus PE6/D6 P47/AN7 Internal address bus

Port E PE5/D5 Internal address bus P47/AN7 PE5/D5 P46/AN6 PE4/D4 P46/AN6 PE4/D4 P45/AN5 Bus controller Port 4 PE3/D3 Bus controller

P45/AN5 Port 4 PE3/D3 P44/AN4 PE2/D2 P44/AN4 PE2/D2 P43/AN3 Peripheral data bus PE1/D1 P43/AN3 Peripheral data bus PE1/D1 P42/AN2 Peripheral address bus PE0/D0 P42/AN2 Peripheral address bus PE0/D0 P41/AN1 P41/AN1 P40/AN0 Port 9 Port 3 Port C Port B Port A P40/AN0 Port 9 Port 3 Port C Port B Port A P96/DA0 P97/DA1 P30/TxD0 P31/RxD0 P32/SCK0/IRQ4 P33/TxD1 P34/RxD1 P35/SCK1/IRQ5 P36 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 A11/TIOCD3 / PB3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 P96/DA0 P97/DA1 P30/TxD0 P31/RxD0 P32/SCK0/SDA1/IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCL0/IRQ5 P36 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 A11/TIOCD3 / PB3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 33 34 H8S/2345 H8S/2245 Flash, 4KRAMoption General purposeH8Swith128K cost H8S General purpose,lowpower, low (14x14mm incl.pins) smallTFP-100Gpackage very ADC aswellDAC DTC, etc. 6x 16-bittimer, 2x8-bittimer, age Flashdevice popular100-pin,singlevolt very telecom applications ideal formanyindustrialand 3V and5Voperation IC/OC, DTC,etc. 3x SCI,16-bittimerwith8 H8S/2240 ROM-lessdevice popular,very lowcost RAM 32k to128KROM,4kor8K in theH8S/2240. * Note: PG PF PF PF PF PF PF PF PF PG PG PG PG ThereisnoROM 0 1 2 3 4 5 6 7 0 1 2 3 4 /BREQ/IRQ0 /BACK/IRQ1 /WAIT/BREQO/IRQ2 /LWR/IRQ3 /HWR /RD /AS / /ADTRG/IRQ6 /CS3/IRQ7 /CS2 /CS1 /CS0 ¿ PG PF PG PG PG PG PF PF PF PF PF PF PF

0 1 2 3 4 5 6 7 0 1 2 3 4 /BREQ/IRQ0 /BACK/IRQ1 /WAIT/IRQ2 /LWR/IRQ3 /HWR /RD /AS / /ADTRG/IRQ6 /CS3/IRQ7 /CS2 /CS1 /CS0 ¿ NMI WDTOVF RES STBY XTAL EXTAL MD MD MD NMI WDTOVF RES STBY XTAL EXTAL MD MD MD 0 1 2 0 1 2 Port Port G F Port G Port F VCC VCC V P10/TIOCA0/A20 CC VCC P1 /TIOCA0/A P1 /TIOCB0/A 0 20 VSS 1 21 V P1 /TIOCB0/A P1 /TIOCC0/TCLKA/A CC 1 21 V Port 1 SS 2 22 V P1 /TIOCC0/TCLKA/A

CC Port 1 P1 /TIOCD0/TCLKB/A 2 22 VSS 3 23 V P1 /TIOCD0/TCLKB/A P1 /TIOCA1 SS 3 23 V 4 V Clock pulse SS

P1 /TIOCA1 Interrupt controller P1 /TIOCB1/TCLKC Clock pulse SS 4 V 5 Interrupt controller V generator SS generator SS P15/TIOCB1/TCLKC V P1 /TIOCA2 TPU 6 V SS TPU P1 /TIOCA2

SS ROM

6 RAM P17/TIOCB2/TCLKD ROM RAM V SS P17/TIOCB2/TCLKD P2 /TIOCA3 V 0 SS P2 * P2 /TIOCB3 0 1 P2 P2 /TIOCC3/TMRI0 1 H8S/2000 CPU 2 Port 2 H8S/2000 CPU P2 /TMRI0 P2 /TIOCD3/TMCI0 2 Port 2 3 PD /D P2 /TIOCA4/TMRI1 PD /D P23/TMCI0 7 15 4 7 15 PD /D P24/TMRI1 6 14 P25/TIOCB4/TMCI1 PD6/D14

Port D PD /D P25/TMCI1 5 13

P2 /TIOCA5/TMO0 Port D PD /D 6 5 13 PD /D P26/TMO0 4 12 P27/TIOCB5/TMO1 PD4/D12 P2 /TMO1 DTC PD3/D11

7 SCI (3channels) DTC PD /D

SCI (2channels) 3 11 V A/D converter PD2/D10 ref D/A converter A/D converter PD /D AV 2 10 8-bit timer PD /D 8-bit timer 1 9

CC WDT PD1/D9 AVSS WDT PD0/D8 PD0/D8 Vref PE /D P4 /AN7/DA1 PE /D Internal data bus 7 7 7 7 7 AVCC Internal data bus PE6/D6 P46/AN6/DA0 PE6/D6 AV Interanal address bus Internal address bus SS Port E PE5/D5

P4 /AN5 Port E PE /D 5 Port 4 5 5 PE4/D4 P44/AN4 PE4/D4 Bus conbtroller Bus controller P43/AN3 Port 4 PE3/D3 P43/AN3 PE3/D3 P42/AN2 PE2/D2 P42/AN2 PE2/D2 P41/AN1 Peripheral data bus PE1/D1 P41/AN1 Peripheral data bus PE1/D1 P40/AN0 Peripheral address bus PE0/D0 P40/AN0 Peripheral address bus PE0/D0 Port Port Port Port C B A 3 Port 5 Port 3 Port C Port B Port A PB PB PB PB PB PB PB PB P5 P3 PC PC PC PC PC PC PC PC PA PA PA PA P5 P5 P5 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 P3 PA PC PC PC PC PC PC PC PC PB PB PB PB PB PB PB PB PA PA PA 3 2 1 0 0 1 2 3 4 5 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 6 7 /SCK2 /RxD2 /TxD2 /TxD0 /TxD1 /RxD0 /RxD1 /SCK0/IRQ4 /SCK1/IRQ5 0 1 2 3 4 5 /A /A /A /A /A /A /A /A /A /A /A 0 1 2 3 4 5 6 7 0 1 2 3 /A /A /A /A /A /A /A /A 0 1 2 3 4 5 6 7 /A /TxD0 /TxD1 /RxD0 /RxD1 /SCK0/IRQ4 /SCK1/IRQ5 /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A 8 9 10 12 13 14 15 16 17 18 19 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 16 17 18 19 0 1 2 3 4 5 6 7 11 H8S/2328 H8S/2357 Flash, 8KRAMoption General purposeH8Swith128k H8S memory Generation, 256KFlash 3rd (16x16mm incl.pins) smallTFP-120package very to highpincount due resources abundant IOport could askfor! full setofperipherals,allone single voltageFlashdevice popular120/128pin, very 6 MIPSDhrystone CPUdelivering high performance (16x16mm incl.pins) smallTFP-120package very due tohighpincount resources abundant IOport could askfor! Full setofperipherals,allone MIPS Dhrystone to8 increase performance operation H8S/2357, but3V/25MHz pin compatiblewith F-ZTAT version. pin functionisnotavailableinthe F-ZTAT versiononly.TheWDTOVF Note: oe:1. Notes: *The FWEpinappliestothe 2. ROMless version. ROM isnotsupportedinthe and thispinistheFWEpin. WDTOVF pinfunctionisnotavailable, In theF-ZTATversion, PF PF PF PF PF PF PF PF PF P6 PG PG PG PG P6 P6 P6 P6 P6 P6 P6 PG 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 /LCAS/WAIT/BREQO /DREQ0/CS4 /TEND0/CS5 /DREQ1 /TEND1 /IRQ0 /IRQ1 /CS6/IRQ2 /CS7/IRQ3 /BREQ /BACK /LCAS/WAIT/BREQO /LWR /HWR /RD /AS / /CAS /CS3 /CS2 /CS1 /CS0 ¿ WDTOVF (FWE) P6 NMI WDTOVF (FWE) RES STBY XTAL EXTAL MD MD MD P6 P6 P6 0 1 0 1 2 /DREQ /TEND P6 6 7 P6 PF PF /CS /CS PF PF PG P6 P6 2 PG PG PG PG 3 0 /DREQ 1 PF PF /TEND 4 /BREQ 3 EXTAL /BACK 4 5 6 7 0 PF /HWR 1 2 3 4 0 0 /LWR STBY /IRQ /IRQ /IRQ /IRQ XTAL /CAS 5 6 /CS /CS /CS /CS /CS /CS RES MD MD MD /RD NMI /AS 7 / * ¿ 3 2 1 0 0 1 1 1 2 3 5 4 0 1 2 1 * Port Port Port Port Port Port G F 6 G F 6 V CC VCC VCC V P1 /PO /TIOCB /TCLKD CC 7 15 2 V P10/PO8/TIOCA0/DACK0 CC VCC P16/PO14/TIOCA2 P1 /PO9/TIOCB0/DACK1 VCC 1 V P1 /PO /TIOCB /TCLKC CC 5 13 1 Port 1 P1 /PO10/TIOCC0/TCLKA VCC 2 Port 1 V P1 /PO /TIOCA CC 4 12 1 V P13/PO11/TIOCD0/TCLKB SS VSS P13/PO11/TIOCD0/TCLKB P1 /PO12/TIOCA1 VSS 4 V P1 /PO /TIOCC /TCLKA Clock pulse SS 2 10 0 Interrupt controller P1 /PO13/TIOCB1/TCLKC Clock pulse V 5 Interrupt controller generator SS generator VSS P11/PO9/TIOCB0/DACK1 P16/PO14/TIOCA2 PPG V TPU PPG V SS TPU P1 /PO /TIOCA /DACK SS 0 8 0 0 RAM* P1 /PO15/TIOCB2/TCLKD

ROM 7 ROM VSS RAM VSS P27/PO7/TIOCB5/TMO1 P2 /PO0/TIOCA3 VSS 0 VSS

P26/PO6/TIOCA5/TMO0 2 P2 /PO1/TIOCB3 VSS 1 VSS P2 /PO /TIOCB /TMCI P2 /PO2/TIOCC3/TMRI0 5 5 4 1 Port 2 V Port 2 V H8S/2000 CPU 2 SS H8S/2600 CPU SS P24/PO4/TIOCA4/TMRI1 P23/PO3/TIOCD3/TMCI0 P23/PO3/TIOCD3/TMCI0 PD7/D15 P24/PO4/TIOCA4/TMRI1 PD7/D15 P22/PO2/TIOCC3/TMRI0 PD6/D14 P25/PO5/TIOCB4/TMCI1 PD6/D14 Port D P21/PO1/TIOCB3 PD5/D13 P26/PO6/TIOCA5/TMO0 Port D PD5/D13 P20/PO0/TIOCA3 PD4/D12 P27/PO7/TIOCB5/TMO1 PD4/D12 DMAC DMAC DTC DTC PD3/D11 PD3/D11 SCI (3channels) Vref SCI (3channels) V A/D converter D/A converter A/D converter D/A converter ref PD2/D10 PD2/D10 8-bit timer AVCC 8-bit timer AVCC PD1/D9 PD1/D9 WDT AVSS WDT AVSS PD0/D8 PD0/D8 P47/AN7/DA1 PE7/D7 P47/AN7/DA1 PE7/D7 Internal data bus Internal data bus P46/AN6/DA0 PE6/D6 P46/AN6/DA0 PE6/D6 Internal address bus Internal address bus

P4 /AN5 Port E PE /D

P4 /AN Port E PE /D

5 5 5 5 Port 4

Port 4 5 5 5 P4 /AN PE /D P4 /AN4 PE /D 4 4 Bus controller 4 4 4 Bus controller 4 4 P43/AN3 PE3/D3 P43/AN3 PE3/D3 P42/AN2 PE2/D2 P42/AN2 PE2/D2 P41/AN1 Peripheral data bus PE1/D1 P41/AN1 Peripheral data bus PE1/D1 P40/AN0 Peripheral address bus PE0/D0 P40/AN0 Peripheral address bus PE0/D0 Port Port Port Port Port Port Port Port Port Port C B A 5 3 C B A 5 3 P5 P3 PC PC PC PC PC PC PC PC PB PB PB PB PB PB PB PB PA PA PA PA PA PA PA P5 P5 P5 P3 P3 P3 P3 P3 PA P5 P5 P5 P3 P3 P3 P3 P3 P3 PC PC PC PC PC PC PC PB PB PB PB PB PB PB PB PA PA PA PA PA PA PA P5 PC PA 3 2 1 0 0 1 2 3 4 5 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3 4 5 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 /ADTRG /SCK2 /RxD2 /TxD2 /TxD0 /TxD1 /RxD0 /RxD1 /SCK0 /SCK1 /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /TxD /RxD /SCK /ADTRG/IRQ /TxD /TxD /RxD /RxD /SCK /SCK /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A /A5 /A /A /A 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7 11 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 6 7 11 /IRQ4 /IRQ5 /IRQ6 /IRQ7 /IRQ /IRQ /IRQ /IRQ 2 0 1 2 0 1 2 0 1 /IRQ /IRQ /IRQ 4 5 6 7 4 5 6 7 /WAIT/BREQO 35 36 H8S/2623 H8S/2633 H8S withintegratedCANV2.0B Super highintegrationH8S ports, for5Vtolerance ports, Separate powersupplyforIO etc. incl. 16chADC,3xSCI,DTC, Excellent peripheralsmix module sophisticated CANV2.0B 12K RAM generation 256K Flashand 3rd (MAC) Accumulate harware 20MHz withMultiply- for 5Vtolerance ports, Separate powersupplyforIO incl. 5xSCI,IIC,IrDA,etc. Very setofperipherals, large 16K RAM generation256KFlashand 3rd Dhrystone Delivers almost10MIPS (MAC) Accumulate hardware 25MHz withMultiply- oe:1 AppliestotheH8S/2633only. 1. Notes: P70/ P71/ P72/TMO0/TEND0/CS6/SYNCI P73/TMO1/TEND1/CS7 P74/TMO2/MRES P75/TMO3/SCK3 P76/RxD3 P77/TxD3 .TheFWEpinisusedonly 2. PG0/CAS/IRQ6 PG1/CS3/OE/IRQ7 PG2/CS2 PG3/CS1 PG4/CS0 PF0/BREQ/IRQ2 PF1/BACK/BUZZ /WAIT/ PF2/LCAS PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS/LCAS PF7/ TMR01/TMC01/DREQ0/CS4 TMR23/TMC23/DREQ1/CS5 PF0/BREQ/IRQ2 PF1/BACK PF2/WAIT/BREQO PF3/LWR/ADTRG/IRQ3 PF4/HWR PF5/RD PF6/AS PF7/ in theflashmemoryversion. ¿ ¿ FWE NMI WDTOVF RES STBY PLLVSS PLLCAP PLLVCC XTAL EXTAL MD0 MD1 MD2 FWE* NMI WDTOVF RES STBY PLLVSS PLLCAP PLLVCC XTAL EXTAL OSC1 OSC2 MD0 MD1 MD2 BREQO *2 2

Port F Port 7 Port G Port F PVCC1 PLL PLL PVCC2 PVCC1 P10/PO8/TIOCA0/DACK0/A20 P17/PO15/TIOCB2/TCLKD VCC PVCC2 P11/PO9/TIOCB0/DACK1/A21 P16/PO14/TIOCA2/IRQ1 VCC

P12/PO10/TIOCC0/TCLKA/A22 Port 1 P15/PO13/TIOCB1/TCLKC PVCC3 VSS Port 1 P13/PO11/TIOCD0/TCLKB/A23 PVCC4 P14/PO12/TIOCA1/IRQ0 P14/PO12/TIOCA1/IRQ0 VSS

VCC PC breakcontroller P13/PO11/TIOCD0/TCLKB/A23 P15/PO13/TIOCB1/TCLKC Interrupt controller Clock pulse VSS VCC flash memory generator (Mask ROM, VSS P12/PO10/TIOCC0/TCLKA/A22 (2 channels) PC breakcontroller Clock pulse P16/PO14/TIOCA2/PWM2/IRQ1 Interrupt controller PPG TPU P11/PO9/TIOCB0/A21 flash memory generator VSS P17/PO15/TIOCB2/PWM3/TCLKD VSS RAM ROM (Mask ROM, (2 channels) PPG P10/PO8/TIOCA0/A20 TPU VSS VSS RAM ROM VSS VSS *1 H8S/2600 CPU VSS ) *1 H8S/2600 CPU

) PD7/D15 PD6/D14 PD7/D15 otDPortE Port D PD5/D13 PD6/D14 PD4/D12 8bit timerx4channels DMAC WDT x2channels (IrDA x1channel) DTC SCI x5channels Port D PD5/D13 14-bit PWMtimer PD3/D11 I HRxD Vref 2 C businterface PD4/D12 A/D converter D/A converter PD2/D10 HTxD AVCC (option) PD1/D9 DTC PD3/D11 HCAN x1channel SCI x3channels Vref WDT x1channel AVSS PD0/D8 A/D converter PD2/D10 AVCC PD1/D9 P47/AN7/DA1 PE7/D7 AVSS Internal data bus PD0/D8 P46/AN6/DA0 PE6/D6 Internal address bus

P45/AN5 Port 4 PE5/D5 P47/AN7 PE7/D7 P44/AN4 PE4/D4 Internal data bus Bus controller P46/AN6 PE6/D6 P43/AN3 PE3/D3 P45/AN5 Internal address bus Port 4 P42/AN2 PE2/D2

Port E PE5/D5 P44/AN4 PE4/D4 P41/AN1 Peripheral data bus PE1/D1 Bus controller P43/AN3 PE3/D3 P40/AN0 Peripheral address bus PE0/D0 P42/AN2 PE2/D2 P41/AN1 Peripheral data bus PE1/D1 Port 9 Port 3 Port C Port B Port A P40/AN0 Peripheral address bus PE0/D0 P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 P30/TxD0/IrTxD P31/RxD0/IrRxD P32/SCK0/SDA1/IRQ4 P33/TxD1/SCL1 P34/RxD1/SDA0 P35/SCK1/SCK4/SCL0/IRQ5 P36/RxD4 P37/TxD4 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6/PWM0 PC7/A7/PWM1 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 A11/TIOCD3 / PB3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 Port 9 Port C Port B Port A P90/AN8 P91/AN9 P92/AN10 P93/AN11 P94/AN12 P95/AN13 P96/AN14 P97/AN15 PC0/A0/TxD0 PC1/A1/RxD0 PC2/A2/SCK0/IRQ4 PC3/A3/TxD1 PC4/A4/RxD1 PC5/A5/SCK1/IRQ5 PC6/A6 PC7/A7 PB0/A8/TIOCA3 PB1/A9/TIOCB3 PB2/A10/TIOCC3 PB3/A11/TIOCD3 PB4/A12/TIOCA4 PB5/A13/TIOCB4 PB6/A14/TIOCA5 PB7/A15/TIOCB5 PA0/A16 PA1/A17/TxD2 PA2/A18/RxD2 PA3/A19/SCK2 PA4 PA5 Ordering Information

The following tables show the available derivatives for each series within the H8/300H and H8S families.To build the actual part name append the desired clock rate to the part name’s body. Example: HD6413001F16 = H8/3001 in FP-80A package, 5V (±10%), 16MHz. For details (tolerance) of the operating voltage range, please refer to the selector guide in the middle of this brochure.

H8/3001 (ROM-less) H8/3006 and H8/3007 (ROM-less) Body Package suffix Package/Voltage/Temp. available clock Body Package suffix Package/Voltage/Temp. available clock HD6413001 F FP-80A/5V 16 HD6413006 F FP-100B/5V 20 TF TFP-80C/5V 16 HD6413007 TE TFP-100B/5V 20 VF FP-80A/low 8,13 VF FP-100B/low 13 VTF TFP-80C/low 8,13 VTE TFP-100B/low 13 FI FP-80A/5V/-40°C..85°C 16 VF FP-100B/low 10 TFI TFP-80C/5V/-40°C..85°C 16 VTE TFP-100B/low 10 VFI FP-80A/low/-40°C..85°C 8,13 FI FP-100B/5V/-40°C..85°C 20 VTFI TFP-80C/low/-40°C..85°C 8,13 TEI TFP-100B/5V/-40°C..85°C 20 FJ FP-80A/5V/-40°C..85°C 16 VFI FP-100B/low/-40°C..85°C 13 VTEI TFP-100B/low/-40°C..85°C 13 H8/3002 (ROM-less) VFI FP-100B/low/-40°C..85°C 10 Body Package suffix Package/Voltage/Temp. available clock VTEI TFP-100B/low/-40°C..85°C 10 FJ FP-100B/5V/-40°C..85°C 20 HD6413002 F FP-100B/5V 16 TF TFP-100B/5V 16 H8/3032 (OTP) VF FP-100B/low 8,10 Body Package suffix Package/Voltage/Temp. available clock VTF TFP-100B/low 8,10 FI FP-100B/5V/-40°C..85°C 16 HD6473032 F FP-80A/5V 16 TFI TFP-100B/5V/-40°C..85°C 16 TF TFP-80C/5V 16 VFI FP-100B/low/-40°C..85°C 8,10 VF FP-80A/low 8,10 VTFI TFP-100B/low/-40°C..85°C 8,10 VTF TFP-80C/low 8,10 FJ FP-100B/5V/-40°C..85°C 16 FI FP-80A/5V/-40°C..85°C 16 TFI TFP-80C/5V/-40°C..85°C 16 H8/3003 (ROM-less) VFI FP-80A/low/-40°C..85°C 8,10 Body Package suffix Package/Voltage/Temp. available clock VTFI TFP-80C/low/-40°C..85°C 8,10 FJ FP-80A/5V/-40°C..85°C 16 HD6413003 RF FP-112/5V 16 RTE TFP-120/5V 16 H8/3035 (OTP) TF FP-112/5V 16 Body Package suffix Package/Voltage/Temp. available clock TTE TFP-120/5V 16 RVF FP-112/low 8,10 HD6473035 F FP-80A/5V 18 RVTE TFP-120/low 8,10 TE TFP-80C/5V 18 TVF FP-112/low 8,10 VF FP-80A/low 8,10 TVTE TFP-120/low 8,10 VTE TFP-80C/low 8,10 RFI FP-112/5V/-40°C..85°C 16 FI FP-80A/5V/-40°C..85°C 18 RTEI TFP-120/5V/-40°C..85°C 16 TEI TFP-80C/5V/-40°C..85°C 18 TFI FP-112/5V/-40°C..85°C 16 VFI FP-80A/low/-40°C..85°C 8,10 TTEI TFP-120/5V/-40°C..85°C 16 VTEI TFP-80C/low/-40°C..85°C 8,10 RVFI FP-112/low/-40°C..85°C 8,10 FJ FP-80A/5V/-40°C..85°C 18 RVTEI TFP-120/low/-40°C..85°C 8,10 TVFI FP-112/low/-40°C..85°C 8,10 H8/3039 (Flash) TVTEI TFP-120/low/-40°C..85°C 8,10 Body Package suffix Package/Voltage/Temp. available clock RFJ FP-112/5V/-40°C..85°C 16 TFJ FP-112/5V/-40°C..85°C 16 HD64F3039 F FP-80A/5V 18 Note: For H8/3003 derivatives with a package suffix starting ‘R’, a crystal with TE TFP-80C/5V 18 double frequency is required, because of an internal divider by 2. VF FP-80A/low 10 VTE TFP-80C/low 10 H8/3004 and H8/3005 (ROM-less) FI FP-80A/5V/-40°C..85°C 18 Body Package suffix Package/Voltage/Temp. available clock TEI TFP-80C/5V/-40°C..85°C 18 VFI FP-80A/low/-40°C..85°C 10 HD6413004 F FP-80A/5V 16,18 VTEI TFP-80C/low/-40°C..85°C 10 HD6413005 TE TFP-80C/5V 16,18 FJ FP-80A/5V/-40°C..85°C 18 VF FP-80A/low 8,10 VTE TFP-80C/low 8,10 H8/3042 (OTP) FI FP-80A/5V/-40°C..85°C 16,18 Body Package suffix Package/Voltage/Temp. available clock TEI TFP-80C/5V/-40°C..85°C 16,18 VFI FP-80A/low/-40°C..85°C 8,10 HD6473042S F FP-100B/5V 16 VTEI TFP-80C/low/-40°C..85°C 8,10 TF TFP-100B/5V 16 FJ FP-80A/5V/-40°C..85°C 16,18 VF FP-100B/low 8,10 VTF TFP-100B/low 8,10 FI FP-100B/5V/-40°C..85°C 16 TFI TFP-100B/5V/-40°C..85°C 16 VFI FP-100B/low/-40°C..85°C 8,10 VTFI TFP-100B/low/-40°C..85°C 8,10 FJ FP-100B/5V/-40°C..85°C 16

37 H8S Ordering Information

H8/3048 (OTP) H8S/2128 (Flash) Body Package suffix Package/Voltage/Temp. available clock Body Package suffix Package/Voltage HD6473048S F FP-100B/5V 16 HD64F2128 FA20 FP-64A/5V TF TFP-100B/5V 16 PS20 DP-64S/5V VF FP-100B/low 8,13 TF20 TFP-80C/5V VTF TFP-100B/low 8,13 VFA10 FP-64A/low FI FP-100B/5V/-40°C..85°C 16 VPS10 DP-64S/low TFI TFP-100B/5V/-40°C..85°C 16 VTF10 TFP-80C/low VFI FP-100B/low/-40°C..85°C 8,13 VTFI TFP-100B/low/-40°C..85°C 8,13 H8S/2132 and H8S/2134 (Flash) FJ FP-100B/5V/-40°C..85°C 16 Body Package suffix Package/Voltage/Temp. H8/3048 (Flash) HD64F2132 FA20 FP-80A/5V Body Package suffix Package/Voltage/Temp. available clock HD64F2134 TF20 TFP-80C/5V VFA10 FP-80A/low HD64F3048 F FP-100B/5V 16 VTF10 TFP-80C/low TF TFP-100B/5V 16 FA20J FP-80A/5V/-40°C..85°C VF FP-100B/low 8 TF20I TFP-80C/5V/-40°C..85°C VTF TFP-100B/low 8 FI FP-100B/5V/-40°C..85°C 16 H8S/2138 (Flash) TFI TFP-100B/5V/-40°C..85°C 16 Body Package suffix Package/Voltage VFI FP-100B/low/-40°C..85°C 8 VTFI TFP-100B/low/-40°C..85°C 8 HD64F2138 FA20 FP-80A/5V FJ FP-100B/5V/-40°C..85°C 16 TF20 TFP-80C/5V VFA10 FP-80A/low H8/3062 and H8/3067 (Flash) VTF10 TFP-80C/low Body Package suffix Package/Voltage/Temp. available clock H8S/2142 and H8S/2144 (Flash) HD64F3062R F FP-100B/5V 20 Body Package suffix Package/Voltage/Temp. HD64F3067R TE TFP-100B/5V 20 VF FP-100B/low 13 HD64F2142 FA20 FP-100B/5V VTE TFP-100B/low 13 HD64F2144 TE20 TFP-100B/5V FI FP-100B/5V/-40°C..85°C 20 VFA10 FP-100B/low TEI TFP-100B/5V/-40°C..85°C 20 VTE10 TFP-100B/low VFI FP-100B/low/-40°C..85°C 13 FA20J FP-100B/5V/-40°C..85°C VTEI TFP-100B/low/-40°C..85°C 13 TE20I TFP-100B/5V/-40°C..85°C FJ FP-100B/5V/-40°C..85°C 20 H8S/2148 (Flash) H8/3040 (pseudo ROM-less version) Body Package suffix Package/Voltage Body Vcc/clock suffix Package suffix Package/Temp. HD64F2148 FA20 FP-100B/5V HD6433040S A, P, T, V 00F FP-100B TE20 TFP-100B/5V A, P, T, V 00TF TFP-100B VFA10 FP-100B/low A, P, T, V 00FI FP-100B/-40°C..85°C VTE10 TFP-100B/low A, P, T, V 00TFI TFP-100B/-40°C..85°C H8S/2237 (OTP) A, P 00FJ FP-100B/-40°C..85°C Body Package suffix Package/Voltage/Temp. Vcc/clock suffix: HD6472237 F10 FP-100A/low A 16MHz/5V FA10 FP-100B/low P 17MHz/5V TE10 TFP-100B/low T 10MHz/3.0..5.5V TF10 TFP-100G/low V 8MHz/2.7..5.5V F10I FP-100A/low/-40°C..85°C FA10I FP-100B/low/-40°C..85°C H8/3044 (pseudo ROM-less version) TE10I TFP-100B/low/-40°C..85°C TF10I TFP-100G/low/-40°C..85°C Body Vcc/clock suffix Package suffix Package/Temp. HD6433044S A, M, S, V 00F FP-100B H8S/2238 (Flash) A, M, S, V 00TF TFP-100B Body Package suffix Package/Voltage/Temp. A, M, S, V 00FI FP-100B/-40°C..85°C A, M, S, V 00TFI TFP-100B/-40°C..85°C HD64F2238 F13 FP-100A/low FA13 FP-100B/low A, M 00FJ FP-100B/-40°C..85°C TE13 TFP-100B/low TF13 TFP-100G/low Vcc/clock suffix: F13I FP-100A/low/-40°C..85°C A 16MHz/5V FA13I FP-100B/low/-40°C..85°C M 18MHz/5V TE13I TFP-100B/low/-40°C..85°C S 13MHz/3.15..5.5V TF13I TFP-100G/low/-40°C..85°C V 8MHz/2.7..5.5V H8S/2240 (ROM-less) Body Package suffix Package/Voltage/Temp. HD6412240 FA20 FP-100B/5V TE20 TFP-100B/5V FA13 FP-100B/low TE13 TFP-100B/low FA10 FP-100B/low TE10 TFP-100B/low FA20I FP-100B/5V/-40°C..85°C TE20I TFP-100B/5V/-40°C..85°C FA13I FP-100B/low/-40°C..85°C TE13I TFP-100B/low/-40°C..85°C FA10I FP-100B/low/-40°C..85°C TE10I TFP-100B/low/-40°C..85°C

38 H8S/2242 (pseudo ROM-less version) H8S/2355 (OTP) Body Vcc/clock suffix Package suffix Package/Temp. Body Package/clock suffix Package/Voltage/Temp. HD6432242 A,M,K 00FA FP-100B HD6472355 F20 FP-128/5V 00TE TFP-100B TE20 TFP-120/5V 00FAI FP-100B/-40°C..85°C F10 FP-128/low 00TEI TFP-100B/-40°C..85°C TE10 TFP-120/low Vcc/clock suffix: A=5V/20MHz, M=low/13MHz, K=low/10MHz F20I FP-128/5V/-40°C..85°C TE20I TFP-120/5V/-40°C..85°C F10I FP-128/low/-40°C..85°C H8S/2246 (OTP) TE10I TFP-120/low/-40°C..85°C Body Package/clock suffix Package/Voltage/Temp. H8S/2357 (OTP) HD6472246 FA20 FP-100B/5V Body Package/clock suffix Package/Voltage/Temp. TE20 TFP-100B/5V FA10 FP-100B/low HD6472357 F20 FP-128/5V TE10 TFP-100B/low TE20 TFP-120/5V FA20I FP-100B/5V/-40°C..85°C F13 FP-128/low TE20I TFP-100B/5V/-40°C..85°C TE13 TFP-120/low FA10I FP-100B/low/-40°C..85°C F10 FP-128/low TE10I TFP-100B/low/-40°C..85°C TE10 TFP-120/low F20I FP-128/5V/-40°C..85°C H8S/2322 (ROM-less) and H8S/2328 (Flash) TE20I TFP-120/5V/-40°C..85°C Body Package/clock suffix Package/Voltage/Temp. F13I FP-128/low/-40°C..85°C TE13I TFP-120/low/-40°C..85°C HD6412322 VF20 FP-128/low F10I FP-128/low/-40°C..85°C HD64F2328 VTE20 TFP-120/low TE10I TFP-120/low/-40°C..85°C VF25 FP-128/low VTE25 TFP-120/low H8S/2357 (Flash) VF20I FP-128/low/-40°C..85°C Body Package/clock suffix Package/Voltage/Temp. VTE20I TFP-120/low/-40°C..85°C VF25I FP-128/low/-40°C..85°C HD64F2357 F20 FP-128/5V VTE25I TFP-120/low/-40°C..85°C TE20 TFP-120/5V VF13 FP-128/low H8S/2340 (ROM-less) VTE13 TFP-120/low Body Package/clock suffix Package/Voltage/Temp. F20I FP-128/5V/-40°C..85°C TE20I TFP-120/5V/-40°C..85°C HD6412340 F20 FP-100A/5V VF13I FP-128/low/-40°C..85°C FA20 FP-100B/5V VTE13I TFP-120/low/-40°C..85°C TE20 TFP-100B/5V TF20 TFP-100G/5V H8S/2623 (Flash) F10 FP-100A/low Body Package/clock suffix Package/Voltage/Temp. FA10 FP-100B/low TE10 TFP-100B/low HD64F2623 FA20J FP-100B/low/-40°C..85°C TF10 TFP-100G/low F20I FP-100A/5V/-40°C..85°C H8S/2633 (Flash) FA20I FP-100B/5V/-40°C..85°C Body Package/clock suffix Package/Voltage/Temp. TE20I TFP-100B/5V/-40°C..85°C TF20I TFP-100G/5V/-40°C..85°C HD64F2633 F25 FP-128/low F10I FP-100A/low/-40°C..85°C TE25 TFP-120/low FA10I FP-100B/low/-40°C..85°C F25I FP-128/low/-40°C..85°C TE10I TFP-100B/low/-40°C..85°C TE25I TFP-120/low/-40°C..85°C TF10I TFP-100G/low/-40°C..85°C H8S/2655 (OTP) H8S/2345 (Flash) Body Package/clock suffix Package/Voltage/Temp. Body Package/clock suffix Package/Voltage HD6472655R F FP-128/5V HD64F2345 F20 FP-100A/5V TE TFP-120/5V FA20 FP-100B/5V VF FP-128/low TE20 TFP-100B/5V VTE TFP-120/low TF20 TFP-100G/5V FI FP-128/5V/-40°C..85°C TEI TFP-120/5V/-40°C..85°C H8S/2350 (ROM-less) VFI FP-128/low/-40°C..85°C Body Package/clock suffix Package/Voltage/Temp. VTEI TFP-120/low/-40°C..85°C HD6412350 F20 FP-128/5V H8S/2655 (pseudo ROM-less version) TE20 TFP-120/5V Body Package/clock suffix Package/Voltage/Temp. F10 FP-128/low TE10 TFP-120/low HD6432655A00 F FP-128/5V F20I FP-128/5V/-40°C..85°C TE TFP-120/5V TE20I TFP-120/5V/-40°C..85°C FI FP-128/5V/-40°C..85°C F10I FP-128/low/-40°C..85°C TEI TFP-120/5V/-40°C..85°C TE10I TFP-120/low/-40°C..85°C

H8S/2352 (ROM-less) Body Package/clock sufﬁx Package/Voltage/Temp. HD6412352 F20 FP-128/5V TE20 TFP-120/5V F13 FP-128/low TE13 TFP-120/low F10 FP-128/low TE10 TFP-120/low F20I FP-128/5V/-40°C..85°C TE20I TFP-120/5V/-40°C..85°C F13I FP-128/low/-40°C..85°C TE13I TFP-120/low/-40°C..85°C F10I FP-128/low/-40°C..85°C TE10I TFP-120/low/-40°C..85°C 39 Ordering Information and Packages

Naming rule for x 14mm) in standard spec. xx will be standard ROM-less commercial criteria H8/300H mask ROM determined after ROM code submission. apply (e. g. minimum order quantity). parts The part names comply with the Naming rule for masked ROM naming rule (please see HD643 + device body+ revision + H8S mask ROM parts above). code/speed + ROM code + package + temperature HD643 + device body+ revision + Microcontrollers for wide device body 4-digit code of desired code/speed + ROM code + package temperature range (WTR) H8/300H derivative, e. g. + temperature All of Hitachi’s microcontrollers are 3042 for H8/3042 device body 4-digit code of desired available in several temperature ranges. revision S for mask revision or H8S derivative, e. g. The standard temperature range is omitted, for new 2653 for H8S/2653 -20°C. . 75°C and is not indicated in the inquiries always use ‘S’ revision (2653 only) package suffix. (where applicable) B for mask revision ROM code 2-digit number assigned ROM code 2-digit number assigned -40°C. . 85°C (I and J-spec) to mask after customer to mask after customer Hitachi offers two specifications for - code submission code submission 40°C. . 85°C. These are indicated in the code/speed A. . E 16MHz/5V code/speed A 20MHz/5V package suffix by I and J. I-spec has a F.. H 12MHz/5V K 10MHz/2. 7. . 5. 5V wider temperature range compared with K,L 10MHz/5V L 16MHz/4. 0. . 5. 5V standard spec, but has the same reliability. M 18MHz/5V M 13MHz/2. 7 J-spec has improved reliability compared P 17MHz/5V (or 3. 0). . 5. 5V with standard spec. Hitachi recommends S 13MHz/3.15 When the “ROM code” overflows to use J-spec for critical applications, ...5.5V (>99) the “code/speed” digit advances, e. particularly in industrial and automotive T,U 10MHz/3. 0 g. from A99 to B00. applications. (or 3. 15V) package ...5.5V F QFP 20mm x 14mm -40°C. . 105°C (JE-spec) V,W 8MHz/2.7 FA QFP 14mm x 14mm JE-spec has the same reliability as J-spec ..5.5V TE TQFP 14mm x 14mm but extends the operating temperature When the “ROM code” overflows TF TQFP 12mm x 12mm range to 105°C. This should - for (>99) the “code/speed” digit advances, e. temperature I, J -40°C. . 85°C example - be used in critical applications g. from A99 to B00. (J-spec has special for automotive safety. package reliability) F QFP 14mm x 14mm JE -40°C. . 105°C -40°C. . 125°C (K-spec) (except H8/3003) K -40°C. . 125°C K-spec further extends the temperature FP QFP 14mm x 20mm range to 125°C and also improves TF TQFP 14mm x 14mm Example: HD6432357AxxFI is a mask reliability over JE-spec. We recommend temperature ROM H8S/2357, with 20MHz/5V in this for important safety features in the I, J -40°C. . 85°C FP-128 package (20mm x 14mm) in I- automotive market, where the product is (J-spec has special reliability) spec. xx will be determined after ROM installed e. g. near the engine. JE -40°C. . 105°C code submission. K -40°C. . 125°C If you require JE- or K-spec, please Example: HD6433032SMxxF is a mask Pseudo ROM-less derivatives contact your Hitachi sales office or ROM H8/3032S (mask revision), with These devices are mask ROM H8/300H authorized distributor. 18MHz/5V in FP-80A package (14mm or H8S with a blank ROM, for which

40 Packages

± Unit: mm 24.8 0.4 Unit: mm 22.0 ± 0.2 20 20 80 51 102 65

81 50 103 64 0.2 0.4 ± ± 14 0.65 0.5 14 16.0 18.8 31 100 128 39 1 38 1 30 0.32 ± 0.08 0.22 ± 0.05 0.13 M 2.4 0.10 M 0.30 ± 0.06 0.20 ± 0.04 1.0 0.05 0.04

0.58 ± ± 0.83 0.05 0.04

2.70 0.75 0.75 ± ± 3.10 Max 3.15 Max 0° Ð 10° 2.70 0.17 0.15 0.17 0.15 0° Ð 10° 1.2 ± 0.2 +0.10 Ð0.20 ± 0.10 0.5 0.2 0.15 0.10 +0.15 Ð 0.20

Dimension including the plating thickness 0.10 Base material dimension Dimension including the plating thickness Base material dimension

FP-100A FP-128

Unit: mm Unit: mm 16.0 ± 0.3 16.0 ± 0.2 14 14 75 51 75 51 76 50 76 50 0.3 ± 0.2 ± 0.5 0.5 16.0 16.0 100 26 100 26 1 25 125 ± 0.22 0.05 0.22 ± 0.05 ± 0.08 M M 0.05 0.20 0.04 0.20 ± 0.04 0.08 0.04 0.05 0.04 ± 1.0 1.0 ± ± ± 1.0 1.0 3.05 Max 2.70 1.20 Max 1.00 0° Ð 8° 0.17 0° Ð 8° 0.15 0.17 0.15 0.5 ± 0.1 0.10 0.12 0.5 ± 0.2 +0.13 Ð 0.10 0.10 ± 0.12 0.10

Dimension including the plating thickness Dimension including the plating thickness Base material dimension Base material dimension

FP-100B TFP-100B

41 Packages

Unit: mm

16.0 ± 0.2 14 90 61 91 60 0.2 ± 0.4 16.0

120 31 130 0.17 ± 0.05 0.04 ± 0.07 M 0.05 ± 0.15 0.04 ± 1.2 1.0 1.00 1.20 Max 0° Ð 8° 0.15 0.17

0.5 ± 0.1 0.10 0.10 ± 0.10

Dimension including the plating thickness Base material dimension

TFP-120 TFP-80C

FP-80A TFP-100G

42 Tools*

Emulators

Hitachi provides fully-featured in- circuit, real-time emulators for all of its devices, at a very competitive price/performance ratio. The ﬁrst-generation H8/300H devices are supported by PCE’s (PC based emulators). These feature: • zero-wait, real-time, in-circuit emulation up to 16MHz • soft- and hardware breakpoints • trace buffer for address, data, transfer Good tools are paramount to the • evaluation board in a metal case (CE type, interrupt mask and user probes successful development of a marked), containing H8/H8S • 3V and 5V support (were appropriate) microcontroller based application. The microcontroller, external SRAM, 2 • emulator control via HDI software, trend to greater system integration and serial ports, LED’s, RESET and NMI featuring the same GUI like HDI-M the increased complexity of new designs push buttons and headers to access all on the Evaluation boards has demanded that high quality, microcontroller signals • .... and much more professional support tools are available for • serial cable H8S as well as the second-generation all stages of the design process. Hitachi • HDI-M monitor software H8/300H devices are supported by has chosen not only to follow the market • GNU and in most cases IAR C- Hitachi’s new highly sophisticated E6000 trend, but to develop support tools which Compiler software (IAR Compiler in emulator. While remaining low cost, are powerful, highly integrated, evaluation version) E6000 provides a wealth of state-of-the- innovative and simple to use, and thus to • Tutorials, installation manual incl. art features that allow design engineers to provide it’s customers with market Circuit diagrams, device manuals and quickly get their system up and running: leading development tools. all the software manuals in electronic • zero-wait, real-time, in-circuit format emulation up to 40MHz Evaluation boards • For evaluation boards using Flash • soft- and hardware breakpoints based microcontrollers, also Hitachi’s Flash on a ‘Complex event system’ (CES) Hitachi provides a full set of quality, low programming software is included. that allows event sequencing cost Evaluation boards for its 16-bit These Evaluation boards are available for • trace buffer for address, data, transfer microcontrollers. These can be used to: the following microcontrollers type, interrupt mask and user probes, • evaluate suitability of the device for featuring acquisition ﬁltering an application, e. g. to run Device family Evaluation • timing/performance analysis with a Board benchmarks resolution as low as 20ns H8/3048F (also H8/304x) EVB3048F • develop software, while the hardware • 3V and 5V support (were appropriate) H8/3067F (also H8/3062F) EVB3067F engineers use emulators • emulator control via HDI software, H8S/2144F (also H8S/2134F) EVB2144F • build prototypes of a system quickly. featuring the same GUI like HDI-M H8S/2655 EVB2655 Each kit contains everything an engineer on the Evaluation boards H8S/2357F (also other 23xx) EVB2357F needs to get started (only a power supply H8S/2633F EVB2633F is needed in addition): H8S/2623F EVB2623F

*For a detailed description of our tools order literature number 17-001 43 C-Compiler/Hitachi spent on learning how to operate the Workbench tool is short, errors in usage are reduced and the project is kept under tight Hitachi’s C-Compiler is designed to control. exercise close control over the hardware Features of the HWB are: of the microcontroller, for example using • split screen viewing in-line function calls, or by allowing • multiple edit windows open at one interrupt service routines being written time directly in ‘C’. It is also highly • context sensitive coloration optimising for the H8/H8S families, with • bookmarks, templates, brace matching All of Hitachi’s emulators can also be the ability to select optimisation for and much more... bought together wit a full kit of software, speed or code size. • automatic placement of the cursor at including Assembler, C-Compiler, HDI It is being operated under a user-friendly, the location causing a compilation debugger and MakeApp (see below). project oriented Windows 95 GUI, called error, displaying a button to jump These popular kits are listed below, please Hitachi Workbench (HWB). Therefore from one error to the next, if there inquire with Hitachi or your authorised engineers can quickly concentrate on are several errors. Hitachi distributor if you require the writing their software instead of trying to • Graphical conﬁguration of Compiler emulator hardware (incl. HDI) only. make the Compiler work. The time and Linker options

Device families Emulator kit The following table lists the target cables for each family/package.

H8/3001, 2,3,4,5 S5-3003 Family Series Footprint Header* H8/3032, 3042 H8/300H H8/3001 FP-80A1 PHB300HQ80A1 H8/3048, 3052 S6-3048 TFP-80C1 PHB300HT80C1 H8/3048-series S5-3048F H8/3030,1,2,3,4,5 FP-80A2 PHB300HQ80A2 H8/306x, 3039 S6-3067 TFP-80C2 PHB300HT80C2 H8S/21xx S6-2148R H8/3004,5 FP-80A3 PHB300HQ80A3 H8S/265x, 234x,5x, 224x S6-2655/4 TFP-80C3 PHB300HT80C3 H8S/231x, 2x S6-2338** H8/3002, H8/3040,1,2, H8/3044,7,8 FP-100B,TFP-100B PHB300HQ100B H8S/233x, 223x S6-2633** H8/3003 FP-112 PHB300HQ112 H8S/262x S6-2623** H8/3036,7,8,9 FP-80A EHB3039Q80A H8/306x, 3006, 7 FP-100B,TFP-100B EHB3067Q100B ** available in 1Q00 H8S H8S/212x DP-64S EHB2128D64S Please note that these kits do not contain FP-64A EHB2128Q64A the target cables, which are needed to H8S/213x FP-80A EHB2138Q80A connect the emulator to your target TFP-80C EHB2138T80C hardware, because each emulator supports H8S/214x FP-100B,TFP-100B EHB2148Q100B many devices of various packages and pin H8S/223x FP-100B,TFP-100B EHB2238Q100B outs. TFP-100G EHB2238T100G H8S/224x FP-100B,TFP-100B EHB2200Q100B H8S/232x FP-128 EHB2328Q128 TFP-120 EHB2328T120 H8S/234x FP-100B,TFP-100B EHB2345Q100B H8S/235x, H8S/265x FP-128 EHB2600Q128 TFP-120 EHB2600T120 H8S/2623 FP-100B EHB2623Q100B H8S/2633 FP-128 EHB2633Q128 *Note: PHB - are for PCE emulators TFP-120 EHB2633T120 EHB - are for E6000 emulators

44 HDI Debugger MakeApp FLASH programming software (FDT) HDI is Hitachi’s debugging interface MakeApp is a visual development tool, used for all development tools ranging which automatically creates device dri- Hitachi provides free Windows software from evaluation boards to emulators. vers for all the on-chip peripherals. It which conveniently supports This enables engineers to move provides a point and click mechanism to programming its Flash microcontrollers. painlessly from one platform to the configure all of the peripherals and then The software provides the following next, without having to learn another to generate well tested and documented functions (excerpt): user interface. ‘C’ source code. • Blank check HDI is a C-source-level debugger, that Each peripheral is presented to the user • Read flash memory allows to display ‘C’ code and for to configure, dialogues are clear and • Program flash memory (with verify) example single-step through it or to provide the user with selections rather • Erase flash memory set breakpoints on C-statements. The than edit boxes. The software is designed to operate with corresponding assembler code can be MakeApp also checks for resource Hitachi’s programming boards (supplied displayed as well, or the C statements conflicts, ensuring that there will be no with the evaluation boards) or with can be shown interleaved with problem when several pieces of code are customers hardware. The boot kernel assembler. integrated into one. (the part of the software which is HDI allows to display CPU registers, Advanced drivers, for example a DMA downloaded into the H8) is supplied as control registers, memory, variables, transfer triggered by a timer, can be ‘C’ source code, to allow customization. etc. created with a few simple mouse strokes. Control over the hardware is exercised The ‘C’ source code files created can be via convenient menus using for easily included in HWB projects. example radio buttons for mutually exclusive options, thus reducing usage errors.

45 Third Party Tools Third Party Operating Systems Third Party Emulators Third party operating systems that sup- Tecsi, 18, place des Reflets, port H8/300H and H8S are available 92975 Paris La Defense Cedex; H8/300H and H8S are being supported from ATI and TECSI. Both companies Tel: +33 1 47 78 67 67 by several renowned third party emulator offer modern real time operating systems Fax: +33 1 47 78 67 68 E-mail [email protected] manufacturers. These are: that feature a compact memory footprint of only a few Kbyte of memory and a fast interrupt response in the order of EPROM Programmers only 20µs. In order to program H8/H8S OTP and Please ﬁnd the contact details below: Flash devices EPROM programmers and UK: 01256 811998 programming adapters are required. email: sales@ash- uk.demon.co.uk These are available from the following companies: Germany: 08233/32681 email: ashling.ger@t_online.de Accelerated Technology Data I/O INCORPORATED Contact: +44-1280-700262 France: (1) 46 66 27 50 Information can be found on the Dataman email: ash-fr@world_net.sct.fr WWW at Contact: +44-1300-320719 http://www.atinucleus.com Rest of Europe: 353 61 334466 Lloyd Research email: [email protected] Geoff Gibson (UK) Contact: +44-1489-574040 Phone: +44 152 766 632 Minato Electronics Inc Fax: +44 152 764 487 Contact: +44-181 953 9292 [email protected] MPQ Contact: +44-1666-825666 Michelle Anderson (USA) Lauterbach Datentechnik GmbH, SMS Holdings Tel: +1 334 661 5770 Fichtenstr. 27, Fax: +1 334 661 5788 Contact: +49-7521-97280 D-85649 Hofolding, Germany. [email protected] Stag Micro-systems Tel: +49 (08104)-8943-0 Contact: +44-1707-332148 Fax: +49 (08104)-8943-30 Michel Genard (France) E-mail: [email protected] Phone: +33 160 924 111 www: Fax: +33 169 290 919 http://www.lauterbach.com

Udo Nuelle (Germany) Phone: +49 5143 93543 Fax: +49 5143 93544

46 Related Literature / Hitachi CD-ROM Internet / CD-ROM ‘Hitachi Electronic Components Shortforms for Hitachi Databook 16-008 Microcontroller Literature no. This CD-ROM is available free of ‘H8/300 & H8/300L’ 21-017 charge from Hitachi or our authorized Hitachi’s single chip, low power H8 family distributors. Please ring ++49-(0)89-99180-128 to ‘Microcontrollers support tools’ 17-001 order your copy or send a fax to ++49- (0)89-99180-265. ‘Integrated Systems LSI’ 02-038 It contains appr. 20. 000 pages of Hitachi documentation about ‘LCD controllers/drivers’ 06-003 microcontrollers, memories and packages. This includes the actual hardware ‘SuperH RISC engine’ 19-017 manuals for almost all our microcontrollers, as well as application notes, programming manuals and overviews.

Data books Literature no. A powerful selection tool allows you to run a selection to ﬁnd out which Hitachi microcontrollers are suitable for your H8/3001 21-092 application. The CD-ROM is usable H8/3002 21-078 under Windows and Macintosh. H8/3003 21-033

H8/3004 and 3005 21-106 Internet H8/3032 series 21-093 access / WWW H8/3035 series 21-111 H8/3048 series 21-095 Under Hitachi’s Electronic Components H8/3067F series 21-115 Group (ECG) homepage (address URL: H8/3062F series 21-116 www. hitachi-eu.com/micro) you can Programming manual 21-032 access detailed technical product H8S/2655 series 18-001 information about Hitachi’s H8S/2245 series 18-004 microcontrollers, memory, displays,ASIC, H8S/2237,2227 series 18-012 discretes & power modules and optoelectronic components. For H8S/2238F 18-020 memory and microcontroller products H8S/2345 series 18-010 each user can download complete data H8S/2350 series 18-006 sheets and application notes in PDF H8S/2357F series 18-011 format. H8S/2328 series 18-021, 022 You will also ﬁnd a complete overview H8S/212x series 18-016 over Hitachi’s European Microcontroller H8S/213x series 18-018 development tools with a short H8S/214x series 18-017 description, the package contents and the H8S technical Q&A 18-007 ordering information (part names). Programming manual 18-003

47 The application notes listed are available for Hitachi’s 16-bit microcontrollers. You will ﬁnd them on our CD-ROM as well as on Hitachi’s web-site (address URL: http://www. hitachi-eu. com/hel/ecg/index. htm). Please note that most of these application notes are easily modiﬁed to be used on H8S.

Application Notes No.

DMA request and Transfer time on H8/300H Apps/012/1.0 Interfacing various bit-size DRAMS to the H8/300H Apps/013/1.0 Add. the damping resistor to the osc. line of the H8/3003 Apps/014/1.0 Enabling DMA end-of-transfer interrupts on the H8/300H Apps/015/1.0 Multiplexed I/O Functions on the H8/3003 & H8/304x Apps/016/1.0 H8/300H Instruction Timing Apps/017/1.0 H8-3042 Framework Program Apps/032/1.1 300H ITU Conﬁguration Example 1 Apps/033/1.0 H8/300H Software UART implem. using 2 Timer and 2 DMA channels Apps/036/1.0 SPI simulation using Synch. Comm. Interface of the 300H Apps/037/1.0 H8/300H Bootloader Apps/042/1.0 H8/300H DMAC Example Apps/044/1.0 H/300H DMAC-Serial Communication Example Apps/045/1.0 H8/300H CS0 During Software Standby Apps/047/2.1 LCD character module control using H8/300H Apps/048/1.1 Producing Optimised C for 300/300H Controllers Apps/049/1.1 Access Speed on the H8/300H Apps/050/1.2 MakeApp + output patterns with the TPC, ITU and DMAC of the H8/3003 Apps/056/1.0 Interfacing the H8/3334, 3048 and the HD44780 LCD driver Apps/059/1.0 Interfacing the H8 300H to the LCM EVB Apps/062/1.0 Connecting an external power supply to the PCE300H Apps/065/1.0 Current Dissipation of H8/3003 measured using the EVB3003 Apps/066/1.0 Using QFP sockets and Hitachi Emulators Apps/067/1.0 Interfacing the H8 and the HD66712 LCD driver Apps/068/1.0 Dhrystone performance H8, H8S, SH Apps/073/1.0 Generating H8S code with GNU compiler V97RIA Apps/079/1.0 Understanding the H8 Series Instruction Prefetch Apps/082/1.0 Key Matrix on H8S/21xx Apps/083/1.0

http://www.hitachi-eu.com/hel/ecg/

Hitachi Europe Ltd Hitachi Europe GmbH Nissei Sangyo GmbH* Electronic Components Group Electronics Components Group (Northern Europe) Continental Europe Nissei Sangyo GmbH (Deutschland) Germany Headquarters: Sales Offices: Dorncher Str. 3, D-85622 Feldkirchen Whitebrook Park, Lower Cookham Road, Germany Tel: (Local) (0 89) 9 91 30 0 Maidenhead, Berkshire SL6 8YA UK Dornacher Str. 3; D-85622 Feldkirchen (INT) (+49) 89 9 91 30 0 Tel: (Local) (01628) 585000 Postfach 2 01: D-85619 Feldkirchen Fax: (Local) (0 89) 9 29 11 85 (INT) (+44) 1628 585000 Tel: (Local) (0 89) 9 91 80 0 (INT) (+49) 89 9 29 11 85 Fax: (Local) (01628) 585160 (INT) (+49) 89 99 1800 (INT) (+44) 1628 585160 Fax: (Local) (0 89) 9 29 30 00 Kurfurstendamm 115b (INT) (+49) 89 929 3000 D-10711 Berlin Sales Offices: Tel: (+49) 30 89 36 81-0 Denmark North Germany/Benelux Fax: (+49) 30 8 91 10 31 Egebækvej 98, 2850 Nærum Am Seestern 18; D40547 Dusseldorf Tel: (+45) 45 80 77 11 Postfach 11 05 36; D-40505 Dusseldorf Hungary Fax: (+45) 45 80 77 54 Tel: (+49) 02 11 52 83-0 East-West Business Center; Rakoczi UT 1-3 Fax: (+49) 02 11 52 83-7 79 H-1088 Budapest Finland Tel: (+36-1) 2 66 66 58. Tap House Tapiolan Keskustorni 11 krs Central Germany Fax: (+36-1) 2 66 - 49 27 02100 Espoo. Friedrich-List-Str. 42; Tel: (+358) 9 455 2488 D-70771 Leinfelden-Echterdingen Spain Fax: (+358) 9 455 2152 Tel: (+49) 7 11 9 90 85-5 Gran Via Carlos III, 101 1°; Fax : (+49) 7 11 9 90 85-99 E-08028 Barcelona Norway Tel: (+34) 34 90 - 78 01 P.O.Box 153, Østre Strandvei 4B, South Germany/Austria Fax: (+34) 33 39 - 78 39 N-3482 Tofte Dornacher Str. 3;D-85622 Feldkirchen Tel: (+47) 32 79 51 11 Tel: (+49) 089 9 91 80. Nissei Sangyo France S.A.R.L.* Fax: (+47) 32 79 52 30 Fax: (+49) 089 9 91 80-266 France Immeuble Ariene; 18 rue Grange Dame Rose Sweden Italy F-78140 Velizy Cedex Haukadalsgaten 10, Box 1062, Via Tommaso Gulli, 39 1-20147, Milano Tel: (+33) 1 30 70 69 70 S-16421 Kista, Stockholm Tel: (+39) 2 48 78 61 Fax: (+33) 1 34 65 77 28 Tel: (+46) 85 62 712 00 Fax: (+39) 2 48 78 63 91 Fax: (+46) 87 51 50 73 Nissei Sangyo Co. Ltd.* United Kingdom Via F.D’Ovidio, 1-00135 Roma Whitebrook Park, Lower Cookham Road, Eire Tel: (+39) 6 82 00 18 24 Maidenhead, Berkshire SL6 8YA Odeon House, Eyre Square Fax: (+39) 6 82 00 18 25 Tel: (Local) (01628) 585000 Galway, Eire (INT) (+44) 1628 585000 Tel: (+353) 91 56 20 20 South Africa Fax: (Local) (01628) 585160 Fax: (+353) 91 56 20 14 7th Floor, Nedbank Gardens, 33 Bath Avenue, (INT) (+44) 1628 585160 Rosebank 2196 (Jb) France Tel: (+27) 11 44 290 80 *Nissei Sangyo GmbH, Nissei Sangyo Hitachi Europe (France) S.A. Fax: (+27) 11 442 9745 France S.A.R.L. and Nissei Sangyo Co. Ltd. are 18, rue Grange Dame Rose, B.P 134 subsidiaries of Hitachi F-78148 Veliz Cedex, France Spain Tel: (+33) 1 34 63 05 00. c/Bunganvilla , 5; E-28036 Madrid Fax: (+33) 1 34 65 34 31 Tel: (+34) 91 7 67 27 82, - 92 Fax: (+34) 91 3 83 85 11

The vital component