DOCSLIB.ORG

Powerpoint Template

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Powerpoint Template ATMs and operating systems Overview for ATMIA Africa forum Tonbridge, England August 2016 Today o Windows 10 o Windows CE o Arising alternatives o Industry RFI Windows 10 - comparison Overview o The ATM industry has been working diligently to deal with XP end of life. Many deployers upgraded ATMs to Windows 7 (end of mainstream support 2015, end of extended support 2020) o Windows 10 was released in 2015 and will be supported at least through 2025 o Microsoft has stepped up in the fight with malware with new security features. This means additional hardware requirements which may not be supported by older ATMs/PCs o ATM deployers need to evaluate which OS to use for XP upgrades, which OS to use for new ATMs and when to upgrade Windows 7 & XP when support ends Windows OS’ life cycles Client operating Latest update or End of End of extended systems service pack mainstream support support Windows XP Service Pack 3 April 14, 2009 April 8, 2014 Windows Vista Service Pack 2 April 10, 2012 April 11, 2017 Windows 7 * Service Pack 1 January 13, 2015 January 14, 2020 Windows 8 Windows 8.1 January 9, 2018 January 10, 2023 Windows 10, released in N/A October 13, 2020 October 14, 2025 July 2015 ** Source Microsoft.com System requirements - compared 10 8/8.1 7 Vista XP Prof. Processor PAE, NX, PAE, NX, SSE2 support SSE2 New Processor 1GHz 1/2 GHz (32/64 1 GHz 1 GHz 300MHz Speed bit processor) CPU 32/64 bit 32/64 bit 32/64 bit 32/64 bit Memory 2GB RAM 2GB RAM 1GB RAM 1 GB RAM 128 MB RAM Hard disk 50 GB 16/20 GB 16/20 GB 15 GB 1.5 GB (32/64 bit CPU) (32/64 bit CPU) (notto XP) Similar to 7 toSimilar Graphic card MS DirectX 9 MS DirectX 9 MS DirectX 9 MS DirectX 9 Super VGA graphics graphics device graphics graphics device with with WDDM device with device with WDDM driver driver WDDM driver WDDM driver Security • TPM 1.2+ New • Secureboot(UEFI) • Device Guard* * DeviceGuard requires the 64 bit implementation, creating high impact In comparison, a Q3 ‘15 delivered low-end Dell PC exceeds the above with 1TB disk, 3.7GHz clock and 6GB memory PAE, NX, SSE2 – old features Anecdotic evidence some of those features not supported by very old PCs. • Physical Address Extension (PAE) is a memory management feature for the IA-32 architecture, first introduced in the Pentium Pro. It defines a page table hierarchy of three levels, with table entries of 64 bits each instead of 32, allowing these CPUs to access a physical address space larger than 4 gigabytes (232 bytes). • The NX bit, which stands for No-eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (code) or for storage of data. starting with Windows XP Service Pack 2 and Windows Server 2003 Service Pack 1, the NX features were implemented for the first time on the x86 architecture. • Streaming SIMD Extensions 2, is one of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2001. Competing chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD6464-bit CPUs in 2003. Source Wikepedia TPM1.2+,SecureBoot, DeviceGuard More “new” versions” which may be already supported by existing PCs. o Trusted Platform Module (TPM) is an international standard for a secure cryptoprocessor, which is a dedicated microprocessor designed to secure hardware by integrating cryptographic keys into devices . optional support in Windows Vista and later o Secure Boot is a security standard developed by members of the PC industry to help make sure that your PC boots using only software that is trusted by the PC manufacturer. The following versions of Windows support Secure Boot: Windows 8.1, Windows Server 2012 R2, Windows RT 8.1, Windows 8, Windows Server 2012, and Windows RT. o Device Guard is a combination of hardware and software security features that, when configured together, will lock a device down so that it can only run trusted applications. To get Device Guard working, a supported IOMMU setup must be present in the PC or device. However, AMD and Intel processors, and even certain ARM and MIPS cores, have had IOMMU protection mechanisms built-in for a while now. Intel calls its IOMMU tech VT-d; AMD prefers AMD-Vi. Support existing base Database/desk study Compatibility agent o Either you specify the o Try this at your own computer components, your ATM manufacturer provides those • Beyond GHz and GB o Validate for each component Windows 10 compatibility o Right click on the windows icon and you are offered a compatibility check The road to Windows 10 The options Spread out the Windows Compliance 7 cost over the longest (as late as possible) period possible Gradual Minimise roll-out costs & (roll-out during planned benefit from malware maintenance, e.g. W7) protection W10 for Skylake ATMs Priority Business case for (as soon as possible to benefit from malware protection malware protection) Recommended activities deployers Determine roll-out HW & SW strategy readiness Stability W10 Desk study benefits & support o Every operator can analyse readiness themselves • Typically GHz & GBs are widely expected to be ready for W10, question mark security features o Please familiarise yourself with W10 releases such as Treshold 2 (aka SP1) and Redstone (aka 10.1) o Once HW & Software vendors announce their readiness date, operators can determine roll-out strategy And now for something completely different . WINDOWS CE USERS About CE and Windows 10 IoT core o Microsoft has announced a CE successor • Windows 10 IoT Core • No support last version (CE 2013) after 10 October 2023 o Characteristics • Downgraded version of Windows 10, same security features • App based, win32 code not supported (so CEN XFS not supported) • Dramatically lower hardware requirements, no end date o Recommendations/conclusions • Support of CEN XFS might have given W10 IoT Core a wider appeal • CE users to assess your software requirements & discuss with your manufacturer ALTERNATIVES TO WINDOWS Alternative operating systems o Hot spot deployment of alternative operating systems o Linux • India – low-cost/maintenance ATMs • Brazil – alternative o Windows CE • US, Canada, UK – comprehensive retail offering o Android • The young pretender Android o Different initiatives • Different market segments • New types (mobile initiated) • Proof-of-concept stage o Big ticket items • Despite increasing CEN XFS endorsement, no emerging Android standards • Compatibility existing back-office systems and R&D INDUSTRY RFI Industry RFI PC based o Rationale • Need for alternatives to Windows Device drivers • Need for proper standardisation • Need for products o ATMIA subcommittee Barcode EPP Card reader Cash Anti- reader dispenser skimming o Input by Payment Redesign App App NFC included, External Required through EMV external interface interviews/questionnaires Device-to-device to deployers Tap card IoT based Summary o First vendor has announced W10 readiness • ATM operators are recommended to look at W10 any time soon • Note the complexity o CE 2013 users to work with their suppliers to look at the impact of the 2023 support sunset o Android in the PoC phase o Industry RFI to drive further standardisation Contact us Eric de Putter www.paymentredesign.com +44 7950 449188 +31 20 808 2151 [email protected].
Load more

Recommended publications
  • Intermediate X86 Part 2
    Intermediate x86 Part 2 Xeno Kovah – 2010 xkovah at gmail All materials are licensed under a Creative Commons “Share Alike” license. • http://creativecommons.org/licenses/by-sa/3.0/ 2 Paging • Previously we discussed how segmentation translates a logical address (segment selector + offset) into a 32 bit linear address. • When paging is disabled, linear addresses map 1:1 to physical addresses. • When paging is enabled, a linear address must be translated to determine the physical address it corresponds to. • It’s called “paging” because physical memory is divided into fixed size chunks called pages. • The analogy is to books in a library. When you need to find some information first you go to the library where you look up the relevant book, then you select the book and look up a specific page, from there you maybe look for a specific specific sentence …or “word”? ;) • The internets ruined the analogy! 3 Notes and Terminology • All of the figures or references to the manual in this section refer to the Nov 2008 manual (available in the class materials). This is because I think the manuals <= 2008 organized and presented much clearer than >= 2009 manuals. • When I refer to a “frame” it means “a page- sized chunk of physical memory” • When paging is enabled, a “linear address” is the same thing as a “virtual memory ” “ ” address or virtual address 4 The terrifying truth revealed! And now you knowAHHHHHHHH!!!…the rest of the story.(Nah, Good it’s not so bad day. :)) 5 Virtual Memory • When paging is enabled, the 32 bit linear address space can be mapped to a physical address space less than 32 bits.
    [Show full text]
  • 2014 International Conference on Green Computing Communication and Electrical Engineering
    2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE 2014) Coimbatore, India 6-8 March 2014 Pages 1-875 IEEE Catalog Number: CFP1460X-POD ISBN: 978-1-4799-4981-6 1/2 TABLE OF CONTENTS VOLUME 1 A NOVEL ROBUST & FAULT TOLERANCE FRAMEWORK FOR WEBSERVICES USING WS- I* SPECIFICATION.............................................................................................................................................................1 Pandey, Akhilesh Kumar ; Kumar, Abhishek ; Zade, Farahnaz Rezaeian A SURVEY OF SELF ORGANIZING TRUST METHOD TO AVOID MALICIOUS PEERS FROM PEER TO PEER NETWORK ..............................................................................................................................................6 Samuvelraj, G. ; Nalini, N. CONTRIVANCE OF ENERGY EFFICIENT ROUTING ALGORITHM IN WIRELESS BODY AREA NETWORK.............................................................................................................................................................. 10 Sridharan, Srivatsan ; Jammalamadaka, Sridhar EFFECTIVE DEFENDING AGAINST FLOOD ATTACK USING STREAM-CHECK METHOD IN TOLERANT NETWORK................................................................................................................................................... 17 Kuriakose, Divya ; Daniel, D. ANONYMOUS ROUTING TECHNIQUE IN MANET FOR SECURE TRANSMISSION: ART .............................. 21 Vijayan, Aleesha ; Yamini, C. DEFINING THE FRAMEWORK FOR WIRELESS-AMI SECURITY IN SMART GRID.......................................
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • X86 Memory Protection and Translation
    2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Logical Diagram Binary Memory x86 Memory Protection and Threads Formats Allocators Translation User System Calls Kernel Don Porter RCU File System Networking Sync Memory Device CPU Today’s Management Drivers Scheduler Lecture Hardware Interrupts Disk Net Consistency 1 Today’s Lecture: Focus on Hardware ABI 2 1 2 COMP 790: OS Implementation COMP 790: OS Implementation Lecture Goal Undergrad Review • Understand the hardware tools available on a • What is: modern x86 processor for manipulating and – Virtual memory? protecting memory – Segmentation? • Lab 2: You will program this hardware – Paging? • Apologies: Material can be a bit dry, but important – Plus, slides will be good reference • But, cool tech tricks: – How does thread-local storage (TLS) work? – An actual (and tough) Microsoft interview question 3 4 3 4 COMP 790: OS Implementation COMP 790: OS Implementation Memory Mapping Two System Goals 1) Provide an abstraction of contiguous, isolated virtual Process 1 Process 2 memory to a program Virtual Memory Virtual Memory 2) Prevent illegal operations // Program expects (*x) – Prevent access to other application or OS memory 0x1000 Only one physical 0x1000 address 0x1000!! // to always be at – Detect failures early (e.g., segfault on address 0) // address 0x1000 – More recently, prevent exploits that try to execute int *x = 0x1000; program data 0x1000 Physical Memory 5 6 5 6 1 2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Outline x86 Processor Modes • x86
    [Show full text]
  • PCI PIN Transaction Security (PTS) Point of Interaction (POI)
    Payment Card Industry (PCI) PIN Transaction Security (PTS) Point of Interaction (POI) Modular Security Requirements Version 4.0 June 2013 Document Changes Date Version Description February 2010 3.x RFC version April 2010 3.0 Public release October 2011 3.1 Clarifications and errata, updates for non-PIN POIs, encrypting card readers February 2013 4.x RFC version June 2013 4.0 Public release Payment Card Industry PTS POI Security Requirements v4.0 June 2013 Copyright 2013 PCI Security Standards Council LLC Page 1 Table of Contents Document Changes ................................................................................................................. 1 About This Document .............................................................................................................. 4 Purpose .................................................................................................................................. 4 Scope of the Document .......................................................................................................... 4 Main Differences from Previous Version ................................................................................. 5 PTS Approval Modules Selection ........................................................................................... 6 Foreword .................................................................................................................................. 7 Evaluation Domains ...............................................................................................................
    [Show full text]
  • Operating Systems & Virtualisation Security Knowledge Area
    Operating Systems & Virtualisation Security Knowledge Area Issue 1.0 Herbert Bos Vrije Universiteit Amsterdam EDITOR Andrew Martin Oxford University REVIEWERS Chris Dalton Hewlett Packard David Lie University of Toronto Gernot Heiser University of New South Wales Mathias Payer École Polytechnique Fédérale de Lausanne The Cyber Security Body Of Knowledge www.cybok.org COPYRIGHT © Crown Copyright, The National Cyber Security Centre 2019. This information is licensed under the Open Government Licence v3.0. To view this licence, visit: http://www.nationalarchives.gov.uk/doc/open-government-licence/ When you use this information under the Open Government Licence, you should include the following attribution: CyBOK © Crown Copyright, The National Cyber Security Centre 2018, li- censed under the Open Government Licence: http://www.nationalarchives.gov.uk/doc/open- government-licence/. The CyBOK project would like to understand how the CyBOK is being used and its uptake. The project would like organisations using, or intending to use, CyBOK for the purposes of education, training, course development, professional development etc. to contact it at con- [email protected] to let the project know how they are using CyBOK. Issue 1.0 is a stable public release of the Operating Systems & Virtualisation Security Knowl- edge Area. However, it should be noted that a fully-collated CyBOK document which includes all of the Knowledge Areas is anticipated to be released by the end of July 2019. This will likely include updated page layout and formatting of the individual Knowledge Areas KA Operating Systems & Virtualisation Security j October 2019 Page 1 The Cyber Security Body Of Knowledge www.cybok.org INTRODUCTION In this Knowledge Area, we introduce the principles, primitives and practices for ensuring se- curity at the operating system and hypervisor levels.
    [Show full text]
  • Chapter 3 Protected-Mode Memory Management
    CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT This chapter describes the Intel 64 and IA-32 architecture’s protected-mode memory management facilities, including the physical memory requirements, segmentation mechanism, and paging mechanism. See also: Chapter 5, “Protection” (for a description of the processor’s protection mechanism) and Chapter 20, “8086 Emulation” (for a description of memory addressing protection in real-address and virtual-8086 modes). 3.1 MEMORY MANAGEMENT OVERVIEW The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging. Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mech- anism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is no mode bit to disable segmentation. The use of paging, however, is optional. These two mechanisms (segmentation and paging) can be configured to support simple single-program (or single- task) systems, multitasking systems, or multiple-processor systems that used shared memory. As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory space (called the linear address space) into smaller protected address spaces called segments. Segments can be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).
    [Show full text]
  • X86 Memory Protection and Translation
    x86 Memory Protection and Translation Don Porter CSE 506 Lecture Goal ò Understand the hardware tools available on a modern x86 processor for manipulating and protecting memory ò Lab 2: You will program this hardware ò Apologies: Material can be a bit dry, but important ò Plus, slides will be good reference ò But, cool tech tricks: ò How does thread-local storage (TLS) work? ò An actual (and tough) Microsoft interview question Undergrad Review ò What is: ò Virtual memory? ò Segmentation? ò Paging? Two System Goals 1) Provide an abstraction of contiguous, isolated virtual memory to a program 2) Prevent illegal operations ò Prevent access to other application or OS memory ò Detect failures early (e.g., segfault on address 0) ò More recently, prevent exploits that try to execute program data Outline ò x86 processor modes ò x86 segmentation ò x86 page tables ò Software vs. Hardware mechanisms ò Advanced Features ò Interesting applications/problems x86 Processor Modes ò Real mode – walks and talks like a really old x86 chip ò State at boot ò 20-bit address space, direct physical memory access ò Segmentation available (no paging) ò Protected mode – Standard 32-bit x86 mode ò Segmentation and paging ò Privilege levels (separate user and kernel) x86 Processor Modes ò Long mode – 64-bit mode (aka amd64, x86_64, etc.) ò Very similar to 32-bit mode (protected mode), but bigger ò Restrict segmentation use ò Garbage collect deprecated instructions ò Chips can still run in protected mode with old instructions Translation Overview 0xdeadbeef Segmentation 0x0eadbeef Paging 0x6eadbeef Virtual Address Linear Address Physical Address Protected/Long mode only ò Segmentation cannot be disabled! ò But can be a no-op (aka flat mode) x86 Segmentation ò A segment has: ò Base address (linear address) ò Length ò Type (code, data, etc).
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Architecture of VIA Isaiah (NANO)
    Architecture of VIA Isaiah (NANO) Jan Davidek dav053 2008/2009 1. Introduction to the VIA Nano™ Processor The last few years have seen significant changes within the microprocessor industry, and indeed the entire IT landscape. Much of this change has been driven by three factors: the increasing focus of both business and consumer on energy efficiency, the rise of mobile computing, and the growing performance requirements of computing devices in a fast expanding multimedia environment. In the microprocessor space, the traditional race for ever faster processing speeds has given way to one that factors in the energy used to achieve those speeds. Performance per watt is the new metric by which quality is measured, with all the major players endeavoring to increase the performance capabilities of their products, while reducing the amount of energy that they require. Based on the recently announced VIA Isaiah Architecture, the new VIA Nano™ processor is a next-generation x86 processor that sets the standard in power efficiency for tomorrow’s immersive internet experience. With advanced power and thermal management features helping to make it the world’s most energy efficient x86 processor architecture, the VIA Nano processor also boasts ultra modern functionality, high-performance computation and media processing, and enhanced VIA PadLock™ hardware security features. Augmenting the VIA C7® family of processors, the VIA Nano processor’s pin compatibility extends the VIA processor platform portfolio, enabling OEMs to offer a wider range of products for different market segments, and furnishing them with the ability to upgrade device performance without incurring the time and cost expense associated with system redesign.
    [Show full text]
  • Covering PCI and PA DSS)
    Monetra® Payment Software Secure Implementation Guide (Covering PCI and PA DSS) Revision: 3.0b3 Publication date November, 2012 Copyright © 2012 Main Street Softworks, Inc. Secure Implementation Guide: (Covering PCI and PA DSS) Main Street Softworks, Inc. Revision: 3.0b3 Publication date November, 2012 Copyright © 2012 Main Street Softworks, Inc. Legal Notice The information contained herein is provided As Is without warranty of any kind, express or implied, including but not limited to, the implied warranties of merchantability and fitness for a particular purpose. There is no warranty that the information or the use thereof does not infringe a patent, trademark, copyright, or trade secret. Main Street Softworks, Inc. shall not be liable for any direct, special, incidental, or consequential damages resulting from the use of any information contained herein, whether resulting from breach of contract, breach of warranty, negligence, or otherwise, even if Main Street has been advised of the possibility of such damages. Main Street reserves the right to make changes to the information contained herein at anytime without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of Main Street Softworks, Inc. Table of Contents 1. Monetra Security Validation (PA-DSS) ......................................................................... 1 1.1. Do Not Retain Sensitive Data ...........................................................................
    [Show full text]
  • Css241 Course Title: Basic Security and Security Threats
    CSS 241 BASIC SECURITY AND SECURITY THREATS NATIONAL OPEN UNIVERSITY OF NIGERIA COURSE CODE :CSS241 COURSE TITLE: BASIC SECURITY AND SECURITY THREATS 1 CSS 241 BASIC SECURITY AND SECURITY THREATS COURSE GUIDE CSS241 BASIC SECURITY AND SECURITY THREATS Course Developer/Writer Monsuru Adegboyega Kasali Non-Violence and Intercultural Communication Advocacy Initiatives, Ibadan, Nigeria Course Editor Rasidi Okunola, Ph. D Department of Sociology University of Ibadan Oyo State Course Coordinator Adeniyi T. Adegoke, Ph.D Criminology and Security Studies School of Arts and Social Sciences National Open University of Nigeria Programme Leader Prof. Abdul-Rasheed Yesufu Dean, School of Arts and Social Sciences National Open University of Nigeria 2 CSS 241 BASIC SECURITY AND SECURITY THREATS NATIONAL OPEN UNIVERSITY OF NIGERIA National Open University of Nigeria Headquarters 14/16 Ahmadu Bello Way Victoria Island Lagos Abuja Office No. 5 Dar es Salam Street Off Aminu Kano Crescent Wuse II, Abuja Nigeria e-mail: [email protected] URL: www.nou.edu.ng Published by National Open University of Nigeria Printed ISBN: All Rights Reserved CONTENTS PAGE Introduction……………………………………..………....i-ii What You Will Learn in this Course ...................................ii Course Aims…………………………………………..... ..ii-iii Course Objectives……………………………………… …iii-iv Working through this Course ...............................................iv Course Materials……………………………….………. …v 3 CSS 241 BASIC SECURITY AND SECURITY THREATS Study Units…………………………………….………. …v-vi Textbooks and References…………….……….……… ….vi-vii Assignment File ………………………………………. ….vii Assessment ………………………………….………. ……viii Tutor-Marked Assignment……………………………. …..viii Final Examination and Grading…………………..……. …viii Course Marking Scheme ………………………………. …viii Course Overview ………………………………………. …viii-ix Presentation Schedule …………………………………. …x How to Get the Most from this Course ……………………x Reading Section.....................................................................x-xi Facilitators/Tutors and Tutorials ……………………….
    [Show full text]