DOCSLIB.ORG

MMU-Based Access Control for Libraries

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
MMU-Based Access Control for Libraries MMU-based Access Control for Libraries Marinos Tsantekidis1 a and Vassilis Prevelakis2 1Institute of Computer Science - FORTH, Greece 2AEGIS IT RESEARCH GmbH, Germany Keywords: Runtime Monitoring, Library Calls, Access Control Gates, Security Policies. Abstract: Code Reuse Attacks can trick the CPU into performing some actions not originally intended by the running program. This is due to the fact that the execution can move anywhere within a process’s executable memory area, as well as the absence of policy checks when a transfer is performed. In our effort to defend against this type of attacks, in an earlier paper we present a Proof-of-Concept mitigation technique based on a modified Linux kernel where each library - either dynamically or statically linked - constitutes a separate code region. The idea behind this technique is to compartmentalize memory in order to control access to the different mem- ory segments, through a gate. Taking our previous work one step further, in this paper we present an updated version of our kernel-side technique, where we implement security policies in order to identify suspicious behavior and take some action accordingly. 1 INTRODUCTION or replace strings), or return an error without mak- ing the call. A key concern is the level at which the As the advancement of technology offers capabilities call intercept should be made. Some papers propose which result in attackers on every level getting more to carry out the checks at the machine code level - competent and effective, attacks have become more via call graphs (e.g., CFI (Abadi et al., 2005) and elaborate. Therefore, we need to establish an ade- variants), while others at the system call level (e.g., quate level of security in software systems. As the systrace(8)). However, because these systems per- complexity of these systems is ever-increasing, we form the checks at fairly low level, they are quite labor have not seen a commensurate improvement in code intensive and error prone and exhibit high overhead. design and development. Hence, systems are becom- Coarse-grained CFI techniques mainly try to deal ing ever more vulnerable to attacks at multiple lev- with the increased performance issues of CFI, trad- els. Complete security of a program is unfeasible. ing off security and being left vulnerable to motivated Conceding that vulnerable code will be included in adversaries. Finer-grained solutions provide higher production systems, there is a need to detect when security, although even in this case studies (Evans one or more of these vulnerabilities is exploited by et al., 2015) have shown that some implementations an attacker. By monitoring the behavior of a pro- prove ineffective in defending against code-reuse at- gram, we can detect any deviations from nominal op- tacks (CRAs). eration. Once a program goes off-nominal we need to determine whether the cause is security-related and, if Contributions. In this paper, we present our hy- so, take appropriate action. Our idea is to implement pothesis that by carrying out behavioral monitoring such actions at an abstract level, between the Operat- at a higher level, we can create a flow diagram that ing System (OS) and a running application. is closer to the program logic and hence more under- Unlike most run-time security mechanisms, where standable. We have chosen the library function call violations in most cases lead to the termination of level as the ideal boundary to install our checks, be- the offending process, the call intercept technique cause libraries are used by the main program but are offers a variety of options in dealing with the se- not part of its execution logic. We present an updated curity breach. For example, systrace(8) (Provos, version of our previous Proof-of-Concept mitigation 2003) may rewrite function arguments (e.g. truncate technique, behind which the idea is to compartmen- a https://orcid.org/0000-0001-6710-5972 talize memory in order to provide access control to 686 Tsantekidis, M. and Prevelakis, V. MMU-based Access Control for Libraries. DOI: 10.5220/0010536706860691 In Proceedings of the 18th International Conference on Security and Cryptography (SECRYPT 2021), pages 686-691 ISBN: 978-989-758-524-1 Copyright c 2021 by SCITEPRESS – Science and Technology Publications, Lda. All rights reserved MMU-based Access Control for Libraries memory segments based on security policies. We ex- gadgets to perform the write(2) system call and then tend our previous approach by installing a special cus- transfer the application’s binary from memory to the tom library, a gate, one for each separate segment and attacker’s socket. redirect the flow of execution through this gate where Over the years, important work has been carried we enforce the relevant security policies. Our mitiga- out with respect to defenses against CRAs. Backes tion technique requires kernel support, which is on of and Nurnberger¨ developed Oxymoron (Backes and its strengths since we can manipulate the memory se- Nurnberger,¨ 2014) to counter JIT-ROP attacks. Oxy- curely and efficiently. We chose to leverage the Mem- moron combines two methods: fine-grained memory ory Management Unit (MMU) and specifically the randomization with the ability to share the entire code NX-bit, because it is easier to us due to our previous among other processes. However, in order for this development experience. To the best of our knowl- defense to be effective, an executable along with all edge, it is the first time this is performed in this way. of its shared libraries need to be instrumented us- Furthermore, our mechanism can be implemented on ing Oxymoron (Mithra and Vipin P., 2015). In con- top of other defense mechanisms. trast, our approach is completely transparent, since The remainder of this paper is organized in the we require no access to the executable or its shared following manner: Section 2 offers a brief summary libraries. of the timeline of CRAs and related defenses. In Venkat, et al. (Venkat et al., 2016) propose a se- Section 3 we detail the design of our approach. In curity defense called HIPStR to thwart (JIT-)ROP. Section 4, we describe the implementation specifics. HIPStR performs dynamic randomization of run-time In Section 5, we evaluate our custom kernel both in program state. However, this measure requires ex- terms of effectiveness and performance. Discussion tensive run-time support to piece the randomized in- and conclusion are provided in Section 6. structions back together, imposing significant over- head (around 15% at best), counter to our mechanism which leaves only a minimal performance footprint. 2 BACKGROUND AND RELATED The systrace(8) (Provos, 2003) system which supports fine-grained policy generation, guards the WORK calls to the operating system at the lowest level, en- forcing policies that restrict the actions an attacker Code Reuse Attacks (CRA) work on the premise that can take to compromise a system. However, this an adversary can use code already present in a pro- fine-grain control is overly verbose. Additionally, it gram’s memory space in order to mislead the CPU may leave a library in an inconsistent state if a mis- to perform unintended by the program actions. So- configuration interrupts the sequence of these calls in phisticated approaches, such as Return Oriented Pro- the middle of execution (Kim and Prevelakis, 2006). gramming (ROP) (Shacham, 2007; Checkoway et al., Later research (Watson, 2007) showed that concur- 2010; Roemer et al., 2012) and Jump Oriented Pro- rency vulnerabilities were discovered, that gave an at- gramming (JOP) (Bletsch et al., 2011), form snippets tacker the ability to construct a race between the en- of code, “gadgets”, chaining together legitimate com- gine and a malicious process to bypass protections. mands already in memory, eventually forming a se- Our technique operates at a higher level, away from quence of gadgets that perform the unauthorized ac- low level calls, closer to the application logic, fa- tion desired by the attacker. Initially, CRAs were cilitating the generation of policies and being more based on the principle that gadgets are located at lightweight in this way. known addresses in memory. Address Space Lay- Access Controls For Libraries and Modules (Sec- out Randomization (ASLR) (PaX, 2001) was intro- Module) (Kim and Prevelakis, 2006) forces user-level duced as a defense measure, but was eventually by- code to perform library calls only via a library pol- passed (Shacham et al., 2004). icy enforcement engine providing mandatory policy Furthermore, Snow et al. introduced “Just-In- checks over not just system calls, as in the case of Time” ROP (JIT-ROP) (Snow et al., 2013) which systrace(8), but calls to user-level libraries as well. maps an application’s memory layout on-the-fly, thus Access to a specific function or procedure is con- bypassing ASLR. Next, it constructs and delivers a trolled by the kernel, however the overhead of two ROP payload based on collected gadgets. context switches per function invocation (caller to Later, Bittau et al. presented Blind Return Ori- kernel and kernel to caller), makes the technique quite ented Programming (BROP) (Bittau et al., 2014). expensive for more general use. One of the issues BROP works against modern 64-bit Linux with identified by the authors of the SecModule paper is ASLR, NX memory and stack canaries (Wagle and the difficulty in encapsulating library modules which Cowan, 2003) enabled. It can remotely find enough 687 SECRYPT 2021 - 18th International Conference on Security and Cryptography was error prone and extremely labor intensive. An- code of any application, making the mechanism suit- other issue is the inability to evaluate call arguments. able for legacy applications as well as binary pro- Although they are contained in a known structure grams.
Load more

Recommended publications
  • Intermediate X86 Part 2
    Intermediate x86 Part 2 Xeno Kovah – 2010 xkovah at gmail All materials are licensed under a Creative Commons “Share Alike” license. • http://creativecommons.org/licenses/by-sa/3.0/ 2 Paging • Previously we discussed how segmentation translates a logical address (segment selector + offset) into a 32 bit linear address. • When paging is disabled, linear addresses map 1:1 to physical addresses. • When paging is enabled, a linear address must be translated to determine the physical address it corresponds to. • It’s called “paging” because physical memory is divided into fixed size chunks called pages. • The analogy is to books in a library. When you need to find some information first you go to the library where you look up the relevant book, then you select the book and look up a specific page, from there you maybe look for a specific specific sentence …or “word”? ;) • The internets ruined the analogy! 3 Notes and Terminology • All of the figures or references to the manual in this section refer to the Nov 2008 manual (available in the class materials). This is because I think the manuals <= 2008 organized and presented much clearer than >= 2009 manuals. • When I refer to a “frame” it means “a page- sized chunk of physical memory” • When paging is enabled, a “linear address” is the same thing as a “virtual memory ” “ ” address or virtual address 4 The terrifying truth revealed! And now you knowAHHHHHHHH!!!…the rest of the story.(Nah, Good it’s not so bad day. :)) 5 Virtual Memory • When paging is enabled, the 32 bit linear address space can be mapped to a physical address space less than 32 bits.
    [Show full text]
  • Multiprocessing Contents
    Multiprocessing Contents 1 Multiprocessing 1 1.1 Pre-history .............................................. 1 1.2 Key topics ............................................... 1 1.2.1 Processor symmetry ...................................... 1 1.2.2 Instruction and data streams ................................. 1 1.2.3 Processor coupling ...................................... 2 1.2.4 Multiprocessor Communication Architecture ......................... 2 1.3 Flynn’s taxonomy ........................................... 2 1.3.1 SISD multiprocessing ..................................... 2 1.3.2 SIMD multiprocessing .................................... 2 1.3.3 MISD multiprocessing .................................... 3 1.3.4 MIMD multiprocessing .................................... 3 1.4 See also ................................................ 3 1.5 References ............................................... 3 2 Computer multitasking 5 2.1 Multiprogramming .......................................... 5 2.2 Cooperative multitasking ....................................... 6 2.3 Preemptive multitasking ....................................... 6 2.4 Real time ............................................... 7 2.5 Multithreading ............................................ 7 2.6 Memory protection .......................................... 7 2.7 Memory swapping .......................................... 7 2.8 Programming ............................................. 7 2.9 See also ................................................ 8 2.10 References .............................................
    [Show full text]
  • X86 Memory Protection and Translation
    2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Logical Diagram Binary Memory x86 Memory Protection and Threads Formats Allocators Translation User System Calls Kernel Don Porter RCU File System Networking Sync Memory Device CPU Today’s Management Drivers Scheduler Lecture Hardware Interrupts Disk Net Consistency 1 Today’s Lecture: Focus on Hardware ABI 2 1 2 COMP 790: OS Implementation COMP 790: OS Implementation Lecture Goal Undergrad Review • Understand the hardware tools available on a • What is: modern x86 processor for manipulating and – Virtual memory? protecting memory – Segmentation? • Lab 2: You will program this hardware – Paging? • Apologies: Material can be a bit dry, but important – Plus, slides will be good reference • But, cool tech tricks: – How does thread-local storage (TLS) work? – An actual (and tough) Microsoft interview question 3 4 3 4 COMP 790: OS Implementation COMP 790: OS Implementation Memory Mapping Two System Goals 1) Provide an abstraction of contiguous, isolated virtual Process 1 Process 2 memory to a program Virtual Memory Virtual Memory 2) Prevent illegal operations // Program expects (*x) – Prevent access to other application or OS memory 0x1000 Only one physical 0x1000 address 0x1000!! // to always be at – Detect failures early (e.g., segfault on address 0) // address 0x1000 – More recently, prevent exploits that try to execute int *x = 0x1000; program data 0x1000 Physical Memory 5 6 5 6 1 2/5/20 COMP 790: OS Implementation COMP 790: OS Implementation Outline x86 Processor Modes • x86
    [Show full text]
  • Operating Systems & Virtualisation Security Knowledge Area
    Operating Systems & Virtualisation Security Knowledge Area Issue 1.0 Herbert Bos Vrije Universiteit Amsterdam EDITOR Andrew Martin Oxford University REVIEWERS Chris Dalton Hewlett Packard David Lie University of Toronto Gernot Heiser University of New South Wales Mathias Payer École Polytechnique Fédérale de Lausanne The Cyber Security Body Of Knowledge www.cybok.org COPYRIGHT © Crown Copyright, The National Cyber Security Centre 2019. This information is licensed under the Open Government Licence v3.0. To view this licence, visit: http://www.nationalarchives.gov.uk/doc/open-government-licence/ When you use this information under the Open Government Licence, you should include the following attribution: CyBOK © Crown Copyright, The National Cyber Security Centre 2018, li- censed under the Open Government Licence: http://www.nationalarchives.gov.uk/doc/open- government-licence/. The CyBOK project would like to understand how the CyBOK is being used and its uptake. The project would like organisations using, or intending to use, CyBOK for the purposes of education, training, course development, professional development etc. to contact it at con- [email protected] to let the project know how they are using CyBOK. Issue 1.0 is a stable public release of the Operating Systems & Virtualisation Security Knowl- edge Area. However, it should be noted that a fully-collated CyBOK document which includes all of the Knowledge Areas is anticipated to be released by the end of July 2019. This will likely include updated page layout and formatting of the individual Knowledge Areas KA Operating Systems & Virtualisation Security j October 2019 Page 1 The Cyber Security Body Of Knowledge www.cybok.org INTRODUCTION In this Knowledge Area, we introduce the principles, primitives and practices for ensuring se- curity at the operating system and hypervisor levels.
    [Show full text]
  • Chapter 3 Protected-Mode Memory Management
    CHAPTER 3 PROTECTED-MODE MEMORY MANAGEMENT This chapter describes the Intel 64 and IA-32 architecture’s protected-mode memory management facilities, including the physical memory requirements, segmentation mechanism, and paging mechanism. See also: Chapter 5, “Protection” (for a description of the processor’s protection mechanism) and Chapter 20, “8086 Emulation” (for a description of memory addressing protection in real-address and virtual-8086 modes). 3.1 MEMORY MANAGEMENT OVERVIEW The memory management facilities of the IA-32 architecture are divided into two parts: segmentation and paging. Segmentation provides a mechanism of isolating individual code, data, and stack modules so that multiple programs (or tasks) can run on the same processor without interfering with one another. Paging provides a mech- anism for implementing a conventional demand-paged, virtual-memory system where sections of a program’s execution environment are mapped into physical memory as needed. Paging can also be used to provide isolation between multiple tasks. When operating in protected mode, some form of segmentation must be used. There is no mode bit to disable segmentation. The use of paging, however, is optional. These two mechanisms (segmentation and paging) can be configured to support simple single-program (or single- task) systems, multitasking systems, or multiple-processor systems that used shared memory. As shown in Figure 3-1, segmentation provides a mechanism for dividing the processor’s addressable memory space (called the linear address space) into smaller protected address spaces called segments. Segments can be used to hold the code, data, and stack for a program or to hold system data structures (such as a TSS or LDT).
    [Show full text]
  • X86 Memory Protection and Translation
    x86 Memory Protection and Translation Don Porter CSE 506 Lecture Goal ò Understand the hardware tools available on a modern x86 processor for manipulating and protecting memory ò Lab 2: You will program this hardware ò Apologies: Material can be a bit dry, but important ò Plus, slides will be good reference ò But, cool tech tricks: ò How does thread-local storage (TLS) work? ò An actual (and tough) Microsoft interview question Undergrad Review ò What is: ò Virtual memory? ò Segmentation? ò Paging? Two System Goals 1) Provide an abstraction of contiguous, isolated virtual memory to a program 2) Prevent illegal operations ò Prevent access to other application or OS memory ò Detect failures early (e.g., segfault on address 0) ò More recently, prevent exploits that try to execute program data Outline ò x86 processor modes ò x86 segmentation ò x86 page tables ò Software vs. Hardware mechanisms ò Advanced Features ò Interesting applications/problems x86 Processor Modes ò Real mode – walks and talks like a really old x86 chip ò State at boot ò 20-bit address space, direct physical memory access ò Segmentation available (no paging) ò Protected mode – Standard 32-bit x86 mode ò Segmentation and paging ò Privilege levels (separate user and kernel) x86 Processor Modes ò Long mode – 64-bit mode (aka amd64, x86_64, etc.) ò Very similar to 32-bit mode (protected mode), but bigger ò Restrict segmentation use ò Garbage collect deprecated instructions ò Chips can still run in protected mode with old instructions Translation Overview 0xdeadbeef Segmentation 0x0eadbeef Paging 0x6eadbeef Virtual Address Linear Address Physical Address Protected/Long mode only ò Segmentation cannot be disabled! ò But can be a no-op (aka flat mode) x86 Segmentation ò A segment has: ò Base address (linear address) ò Length ò Type (code, data, etc).
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Architecture of VIA Isaiah (NANO)
    Architecture of VIA Isaiah (NANO) Jan Davidek dav053 2008/2009 1. Introduction to the VIA Nano™ Processor The last few years have seen significant changes within the microprocessor industry, and indeed the entire IT landscape. Much of this change has been driven by three factors: the increasing focus of both business and consumer on energy efficiency, the rise of mobile computing, and the growing performance requirements of computing devices in a fast expanding multimedia environment. In the microprocessor space, the traditional race for ever faster processing speeds has given way to one that factors in the energy used to achieve those speeds. Performance per watt is the new metric by which quality is measured, with all the major players endeavoring to increase the performance capabilities of their products, while reducing the amount of energy that they require. Based on the recently announced VIA Isaiah Architecture, the new VIA Nano™ processor is a next-generation x86 processor that sets the standard in power efficiency for tomorrow’s immersive internet experience. With advanced power and thermal management features helping to make it the world’s most energy efficient x86 processor architecture, the VIA Nano processor also boasts ultra modern functionality, high-performance computation and media processing, and enhanced VIA PadLock™ hardware security features. Augmenting the VIA C7® family of processors, the VIA Nano processor’s pin compatibility extends the VIA processor platform portfolio, enabling OEMs to offer a wider range of products for different market segments, and furnishing them with the ability to upgrade device performance without incurring the time and cost expense associated with system redesign.
    [Show full text]
  • Dissertation
    An Agile and Rapidly Reconfigurable Test Bed for Hardware-Based Security Features by Daniel Smith Beard Master of Science Computer Information Systems Florida Institute of Technology 2009 Bachelor of Science Engineering, Electrical Option University of South Florida 1980 A dissertation submitted to the College of Engineering and Computer Science at Florida Institute of Technology in partial fulfillment of the requirements for the degree of Doctorate of Philosophy in Computer Science Melbourne, Florida December, 2019 © Copyright 2019 Daniel Smith Beard All Rights Reserved The author grants permission to make single copies. We the undersigned committee hereby approve the attached dissertation An Agile and Rapidly Reconfigurable Test Bed for Hardware-Based Security Features by Daniel Smith Beard Marco Carvalho, Ph.D. Professor and Dean College of Engineering and Science Committee Chair Stephen K. Cusick, J.D. Associate Professor College of Aeronautics Outside Committee Member William H. Allen, Ph.D. Associate Professor Computer Engineering and Sciences Committee Member Heather Crawford, Ph.D. Assistant Professor Computer Engineering and Sciences Committee Member Philip J. Bernhard, Ph.D. Associate Professor and Department Head Computer Engineering and Sciences ABSTRACT Title: An Agile and Rapidly Reconfigurable Test Bed for Hardware-Based Security Features Author: Daniel Smith Beard Major Advisor: Marco Carvalho, Ph.D. Current general-purpose computing hardware and the software that runs on it have evolved over more than a half century from large mainframe systems in corporate, military, and research use to interconnected commodity devices more common than wrist watches. Computational power, storage capacity, and communication capa- bilities have increased in wonderful and staggering ways; however, when we read about the latest vulnerability or data breach it seems that cybersecurity is stuck somewhere between 1983 when Matthew Broderick first heard a synthesized voice ask \Shall we play a game?", [93] and 1988 when the Morris worm hit the Internet [116].
    [Show full text]
  • The Technology Behind Crusoe™ Processors: Low-Power X86-Compatible Processors Implemented with Code-Morphing™ Software”
    “The Technology Behind Crusoe™ Processors: Low-Power x86-Compatible Processors Implemented with Code-Morphing™ Software” Alexander Klaiber Transmeta Corporation January 2000 presented by nick black <[email protected]> for cs8803dc 2010-04-15 watch this space for valuable addenda -- BIG MONEY! BIG PRIZES! YOU LOVE IT!! Motivation ● Commercial processor built around binary translation. ● Anyone remember the M680x0 emulator for PowerPC Macs?(*) ● How about PRISM's Epicode + Mica? VEST/AEST on Alpha?(**) ● One of two major GP-VLIW implementations. ● Yes, I absolutely am discounting Multiflow Computer's 125 sales. ● Integrated design of architecture and translator. ● Interesting design space: ● An attempt to reduce power and size of PC2001/x86. ● Not targeted at embedded space, where cost is a main motivator! “A Microprogrammed Implementation of an Architecture Simulation Language” (1977) (*) Tom Hormby's IBM, Apple, RISC, and the Roots of the PowerPC and Steven Levy's Insanely Great. (**) Paul Bolotoff's Alpha: The History in Facts and Comments. Anti-Motivation (*) 1917-10-23, paraphrased from John Reed's Ten Days That Shook the World (1919) pull over; that table's too fat (woop woop) Sources: Transmeta product datasheets, UIUC CS433 “Processor Presentation Series” notes for Transmeta Crusoe, sandpile.org IA-32 Implementation Guides for Crusoe/Efficeon Initial reactions, pre-paper: ● Anyone can run an x86 translator/emulator ● Why wouldn't Intel just build this instead? ● P6 was doing hardware CISC-to-RISC (CRISC) in 1995 ...though dissipating
    [Show full text]
  • Windows SMEP Bypass U=S
    Windows SMEP Bypass U=S Nicolas A. Economou Enrique E. Nissim PAGE Schedule - Reviewing Modern Kernel Protections - Introducing SMEP - Windows SMEP bypass techniques – Part 1 - Windows Paging Mechanism - Windows SMEP bypass techniques – Part 2 - DEMO - Conclusions PAGE 2 Reviewing Modern Protections - DEP/NX: is a security feature included in modern operating systems. It marks areas of memory as either "executable" or "nonexecutable". - NonPagedPoolNX: new type of pool introduced in Windows 8 - KASLR: Address-space layout randomization (ASLR) is a well- known technique to make exploits harder by placing various objects at random, rather than fixed, memory addresses. - NULL Dereference Protection: cannot alloc the null page. PAGE 3 Reviewing Modern Protections - Integrity Levels: call restrictions for applications running in low integrity level – since Windows 8.1. - KMCS: Kernel-mode software must be digitally signed to be loaded on x64-based versions of Windows Vista and later versions of the Windows family of operating systems. - KPP: Kernel Patch Protection (informally known as PatchGuard): is a feature of x64 editions of Windows that prevents patching common structures of the kernel.(Hooking IDT, SSDT, GDT, LDT is out of the table). PAGE 4 Reviewing Modern Protections - SMAP: allows pages to be protected from supervisor-mode data accesses. If SMAP = 1, software operating in supervisor mode cannot access data at linear addresses that are accessible in user mode. - SMEP: Supervisor Mode Execution Prevention allows pages to be protected
    [Show full text]
  • Quiz I Solutions
    Department of Electrical Engineering and Computer Science MASSACHUSETTS INSTITUTE OF TECHNOLOGY 6.858 Fall 2014 Quiz I Solutions 25 Grade distribution 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Histogram of grade distribution Mean 64.4, Stddev 15.5 1 I Baggy Bounds and Buffer Overflows 1. [6 points]: At initialization time, a baggy bounds system on a 32-bit machine is supposed to set all of the bounds table entries to 31. Suppose that, in a buggy implementation with a slot_size of 32 bytes, bounds table initialization is improperly performed, such that random entries are incorrectly set to 1. Suppose that a networked server uses an uninstrumented library to process network messages. Assume that this library has no buffer overflow vulnerabilities (e.g., it never uses unsafe functions like gets()). However, the server does suffer from the bounds table initialization problem described above, and the attacker can send messages to the server which cause the library to dynamically allocate and write an attacker-controlled amount of memory using uninstrumented code that looks like this: // N is the buffer size that the // attacker gets to pick. char *p = malloc(N); for (int i = 0; i < N/4; i++, p += 4) { *p = '\a'; *(p+1) = '\b'; *(p+2) = '\c'; *(p+3) = '\d'; } Assume that the server uses a buddy memory allocator with a maximum allocation size of 216 (i.e., larger allocations fail). What is the smallest N that the attacker can pick that will definitely crash the server? Why will that N cause a crash? Answer: The uninstrumented library code does not check bounds table entries when it does pointer arithmetic.
    [Show full text]