Demystifying 40 Gigabit Ethernet Physical Layer Interfaces in Data Centers

Total Page:16

File Type:pdf, Size:1020Kb

Load more

Demystifying 40 Gigabit Ethernet Physical Layer Interfaces in Data Centers Rita Horner Synopsys Santa Clara, CA USA April-May 2014 1 Evolution of Ethernet Speeds 100 GE Data Rate (4x25 GE) (Mbps) 100 GE (10x10 GE) 100,000 10 Gigabit Ethernet 10,000 Gigabit 40 GE Ethernet (4x10 GE) 1000 Fast Ethernet FDDI 100 Ethernet 10 1 1980 1990 1995 1998 2002 2010 2014 Santa Clara, CA USA April-May 2014 2 Different Interfaces in a Chassis 1. Chip-to-Chip Port side 2. Chip-to-Module (direct) 3. Chip-to-Backplane 3 2 1 2 3 1 2 1 3 Santa Clara, CA USA April-May 2014 3 Evolution of 10 GE Port Side Aggregated 10 GE (XAUI) Serial 10 GE . IEEE 802.3ae-2002 – 10 Gigabit Ethernet supporting both port side and backplane using aggregated XAUI (3.125 Gbps per lane in a x4 configuration) with 8b/10b encoding 10 GE Module form factor migration Gen1 X2 Gen2 Gen3 4-lanes XAUI 300 pins 16-lanes XSBI Xenpak SFP+ 1-lane 10G SFI 4-lanes XAUI XFP 1-lane 10G XFI Modules with Gearbox, a.k.a. MUX/De-MUX Module with Retimer Un-retimed 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 Santa Clara, CA USA April-May 2014 4 10GE Port Side Module Interfaces Size Reduction Requires Power Reduction 4x 4 XENPAK Port 3.125 Gbps Gearbox ASIC SerDes XAUI or 10 GE PHY (4:1) 4 X2 4x 4 Port 3.125 Gbps Gearbox XAUI XFI Retimer XFP 10 GE ASIC SerDes (4:1) PHY 4 10 GE Port 10.3 Gbps SerDes 10 GERetimer 10 GE SFP+ 10 GE ASIC PHY XFI SFI Santa Clara, CA USA April-May 2014 5 Evolution of Port Densities 10GE 40GE Single row 24 x 10 GE SFP+ ports 240 Gbps Two rows 48 x 10 GE SFP+ ports 480 Gbps Single row 4 x 40 GE CFP ports 160Gbps Single row 12 or 16 x 40 GE QSFP ports 480 to 640 Gbps Two rows 12 or 16 x 40 GE QSFP ports 960 to 1280 Gbps Santa Clara, CA USA April-May 2014 6 40GE Port Side Module Interfaces Size Reduction Requires Power Reduction 4x 4 Port 10.3 Gbps ASIC SerDes XLAUI Retimer CFP 40 GE PHY 4 4x Port 10.3 Gbps 40 GERetimer 40 GE QSFP 40 GE ASIC SerDes PHY XLAUI XLPPI 4x Port 10.3 Gbps 40 GE QSFP 40 GE ASIC SerDes PHY Retimer XLPPI Santa Clara, CA USA April-May 2014 7 Different Interfaces in a Chassis 1. Chip-to-Chip Port side 2. Chip-to-Module (direct) 3. Chip-to-Backplane 3 2 1 2 3 1 2 1 3 Santa Clara, CA USA April-May 2014 8 10GE and 40GE Interfaces Port Side Rate Interface Chip-to-Chip Chip-to-Module Backplane Fiber Optic Fiber Optic Copper Electrical XFI SFI (limiting & linear) SFI linear 10GBASE-KR SFP+, 10GBASE-SR SFP+, DAC XFP, 10GBASE-SR 10 GE Module SFP+, 10GBASE-LR (Direct XFP, 10GBASE-LR - types SFP+, 10GBASE-LRM Attached XFP, 10GBASE-ER SFP+, 10GBASE-ER Copper) Electrical XLAUI XLPPI 40GBASE-KR4 CFP, 40GBASE-SR4 QSFP, 40GBASE-SR4 QSFP, 40 GE Module CFP, 40GBASE-LR4 QSFP, 40GBASE-LR4 40GBASE- - types CFP, 40GBASE-ER4 QSFP, 40GBASE-ER4 CR4 Santa Clara, CA USA April-May 2014 9.
Recommended publications
  • Design of a High Speed XAUI Based on Dynamic Reconfigurable

    Design of a High Speed XAUI Based on Dynamic Reconfigurable

    International Journal of Soft Computing And Software Engineering (JSCSE) e-ISSN: 2251-7545 Vol.2,o.9, 2012 DOI: 10.7321/jscse.v2.n9.4 Published online: Sep 25, 2012 Design of a High Speed XAUI Based on Dynamic Reconfigurable Transceiver IP Core * 1Haipeng Zhang, 1Lingjun Kong, 2Xiuju Huang, 3Mengmeng Cao 1 .School of Electronics & Information, Hangzhou Dianzi University, Hangzhou, China, 310018 2. UTSTARCOM Co. Ltd. Hangzhou, China, 310052 3. North China Electric Power University, Department of electronics and Communication Engineering, Baoding, China, 071003 Email:1 [email protected],2 [email protected],3 [email protected] Abstract. By using the dynamic reconfigurable transceiver in high speed interface design, designer can solve critical technology problems such as ensuring signal integrity conveniently, with lower error binary rate. In this paper, we designed a high speed XAUI (10Gbps Ethernet Attachment Unit Interface) to transparently extend the physical reach of the XGMII. The following points are focused: (1) IP (Intellectual Property) core usage. Altera Co. offers two transceiver IP cores in Quartus II MegaWizard Plug-In Manager for XAUI design which is featured of dynamic reconfiguration performance, that is, ALTGX_RECOFIG instance and ALTGX instance, we can get various groups by changing settings of the devices without power off. These two blocks can accomplish function of PCS (Physical Coding Sub-layer) and PMA (Physical Medium Attachment), however, with higher efficiency and reliability. (2) 1+1 protection. In our design, two ALTGX IP cores are used to work in parallel, which named XAUI0 and XAUI1. The former works as the main channel while the latter redundant channel.
  • Information Specification ** INF-8474I Rev 3.0 Xenpak 10

    Information Specification ** INF-8474I Rev 3.0 Xenpak 10

    ** Information Specification ** INF-8474i Rev 3.0 SFF Committee documentation may be purchased in hard copy or electronic form SFF specifications are available at ftp://ftp.seagate.com/sff SFF Committee INF-8474i Specification for Xenpak 10 Gigabit Ethernet Transceiver Rev 3.0 September 18 2002 Secretariat: SFF Committee Abstract: This specification describes the Xenpak 10 Gigabit Ethernet Transceiver. It was developed by the MSA (Multiple Source Agreement) group in which the following companies participated: Agilent Technologies Mitsubishi Electric Blaze Network Products Molex ExceLight NEC Extreme Networks OpNext Finisar Optillion Hitachi Cable PicoLight Ignis Optics Stratos Lightwave Infineon Technologies Tyco Electronics JDS Uniphase Vitesse Semiconductor Luminent This Information Specification was not developed or endorsed by the SFF Committee but was submitted for distribution on the basis that it is of interest to the storage industry. The copyright on the contents remains with the contributor. Contributors are not required to abide by the SFF patent policy. Readers are advised of the possibility that there may be patent issues associated with an implementation which relies upon the contents of an 'i' specification. SFF accepts no responsibility for the validity of the contents. POINTS OF CONTACT: Dan Rausch I. Dal Allan Technical Editor Chairman SFF Committee Avago Technologies 14426 Black Walnut Court 350 West Trimble Rd Saratoga San Jose CA 95131 CA 95070 408-435-6689 408-867-6630 [email protected] [email protected] Xenpak 10 Gigabit Ethernet Transceiver Page 1 ** Information Specification ** INF-8474i Rev 3.0 EXPRESSION OF SUPPORT BY MANUFACTURERS The following member companies of the SFF Committee voted in favor of this industry specification.
  • Ipug68 01.3 Lattice Semiconductor XAUI IP Core User’S Guide

    Ipug68 01.3 Lattice Semiconductor XAUI IP Core User’S Guide

    ispLever TM CORECORE XAUI IP Core User’s Guide November 2009 ipug68_01.3 Lattice Semiconductor XAUI IP Core User’s Guide Introduction The 10Gb Ethernet Attachment Unit Interface (XAUI) IP Core User’s Guide for the LatticeECP2M™ and LatticeECP3™ FPGAs provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII) devices. This user’s guide implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FGPA provides a complete XAUI-to-XGMII solu- tion. The XAUI IP core package comes with the following documentation and files: • Protected netlist/database • Behavioral RTL simulation model • Source files for instantiating and evaluating the core The XAUI IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to create versions of the IP core that operate in hardware for a limited period of time (approximately four hours) without requiring the pur- chase on an IP license. It may also be used to evaluate the core in hardware in user-defined designs. Details for using the hardware evaluation capability are described in the Hardware Evaluation section of this document. Features • XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encod- ing/decoding. • Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA. • Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including: – 10 GbE Media Independent Interface (XGMII). – Optional Slip buffers for clock domain transfer to/from the XGMII interface.
  • IEEE Std 802.3™-2012 New York, NY 10016-5997 (Revision of USA IEEE Std 802.3-2008)

    IEEE Std 802.3™-2012 New York, NY 10016-5997 (Revision of USA IEEE Std 802.3-2008)

    IEEE Standard for Ethernet IEEE Computer Society Sponsored by the LAN/MAN Standards Committee IEEE 3 Park Avenue IEEE Std 802.3™-2012 New York, NY 10016-5997 (Revision of USA IEEE Std 802.3-2008) 28 December 2012 IEEE Std 802.3™-2012 (Revision of IEEE Std 802.3-2008) IEEE Standard for Ethernet Sponsor LAN/MAN Standards Committee of the IEEE Computer Society Approved 30 August 2012 IEEE-SA Standard Board Abstract: Ethernet local area network operation is specified for selected speeds of operation from 1 Mb/s to 100 Gb/s using a common media access control (MAC) specification and management information base (MIB). The Carrier Sense Multiple Access with Collision Detection (CSMA/CD) MAC protocol specifies shared medium (half duplex) operation, as well as full duplex operation. Speed specific Media Independent Interfaces (MIIs) allow use of selected Physical Layer devices (PHY) for operation over coaxial, twisted-pair or fiber optic cables. System considerations for multisegment shared access networks describe the use of Repeaters that are defined for operational speeds up to 1000 Mb/s. Local Area Network (LAN) operation is supported at all speeds. Other specified capabilities include various PHY types for access networks, PHYs suitable for metropolitan area network applications, and the provision of power over selected twisted-pair PHY types. Keywords: 10BASE; 100BASE; 1000BASE; 10GBASE; 40GBASE; 100GBASE; 10 Gigabit Ethernet; 40 Gigabit Ethernet; 100 Gigabit Ethernet; attachment unit interface; AUI; Auto Negotiation; Backplane Ethernet; data processing; DTE Power via the MDI; EPON; Ethernet; Ethernet in the First Mile; Ethernet passive optical network; Fast Ethernet; Gigabit Ethernet; GMII; information exchange; IEEE 802.3; local area network; management; medium dependent interface; media independent interface; MDI; MIB; MII; PHY; physical coding sublayer; Physical Layer; physical medium attachment; PMA; Power over Ethernet; repeater; type field; VLAN TAG; XGMII The Institute of Electrical and Electronics Engineers, Inc.
  • Scott Kipp, Ethernet Alliance President

    Scott Kipp, Ethernet Alliance President

    AN ETHERNET ROADMAP Scott Kipp [email protected] March 2013 1 THE VIEWS EXPRESSED IN THIS PRESENTATION ARE BROCADE VIEWS AND SHOULD NOT BE CONSIDERED THE VIEWS OR POSITIONS OF THE ETHERNET ALLIANCE. This presentation is being given to work toward having a position for the Ethernet Alliance 2 Ethernet Roadmap • The IEEE defines Ethernet standards and does not release a roadmap for future standards • The industry does not have a good understanding of how Ethernet was developed or where it is headed • This presentation will look at past Ethernet developments to give a better understanding of where Ethernet will likely go in the future • The emphasis of this presentation is on high-speed optical interfaces • BASE-T and Backplane not covered 3 Gigabit Optical Modules and Speeds Key: Ethernet Speed 100G GBIC SFP 40G SC LC connector connector 10G Acronyms: 8GFC GBIC = GigaBit 4GFC Interface Converter SFP – Small Form 2GFC factor Pluggable Data Rate and Line Rate (b/s) and Line Rate Data Rate 1GFC GbE GFC – Gigabit Fiber 1G Channel GbE – Gigabit 1995 2000 2005 2010 2015 Ethernet Standard Completed 3/19/2013 4 Who Uses Gigabit Fiber in Data Centers? This is limited to Switching and not Routing Fibre Channel is >95% optics Ethernet is > 95% copper Gigabit Ethernet Switch Port Shimpents (000s) Source: Dell’Oro Ethernet Switch Layer 2+3 Report Five Year Forecast, 2013-2017 3/19/2013 5 Got Copper? 3/19/2013 6 3/19/2013 7 10-100 Gigabit Optical Modules and Speeds Key: Parallel Ethernet Speed QSFP+ Optics Fibre Channel 100G MPO Speed Connector InfiniBand
  • 1 Reference 10Gbe Implementation • XAUI/XGXS and XGMII Are Both

    1 Reference 10Gbe Implementation • XAUI/XGXS and XGMII Are Both

    Reference 10GbE Implementation Device A includes XGMII + XAUI , Device B includes XGMII Device PHY XGMII XAUI MDI A TXC X TXD P P P G MAC RS 36 XGXS C M M X RXC S A D S RXD 36 Transceiver Modules Initial 10 GbE Form Factor: Device PHY XGMII Daughter Card B TXC TXD P P P Medium MAC RS 36 C M M RXC S A D RXD 36 MDI • XAUI/XGXS and XGMII are both optional physical instantiations of the PCS Service Interface. • An Ethernet device implementation may contain either, neither, both, or multiple instances of either XAUI/XGXS and XGMII. • For purposes of data and code transport, Device A represents the case of either XAUI/XGXS + XGMII or XAUI alone since the XGMII does not perform code translation. • For purposes of data and code transport, Device B represents the case of either XGMII alone, neither XAUI/XGXS nor XGMII, or XAUI/XGXS with XGMII on both sides since the XGMII does not perform code translation. • It is assumed that the Reconciliation Sublayer is required to transport the following data and control information: • Start of Packet /S/ • Data /d/ • End of Packet /T/ • Idle /I/ • Error /E/ • Remote Fault /RF/ (used in Fast/Gigabit Ethernet) • Break Link /BL/ (used in Fast/Gigabit Ethernet) • Other /O/ (reserved or for other standards, OAM&P, etc.) 1 Serial PHY, 64B/66B PCS, XGXS never forwards /A/K/R/ /S/d/T/I/E/ /S/d/T/E/ /S/d/T/E/ /RF/BL/O/ /S/d/T/I/E/ /A/K/R/ /A/K/R/ /S/d/T/I/E/ /S/d/T/I/E/ /RF/BL/O/ /RF/BL/O/ /RF/BL/O/ /RF/BL/O/ /RF/BL/O/ Device PHY XGMII XAUI MDI A TXC X TXD P P P G MAC RS 36 XGXS C M M X RXC S A D S RXD 36 Device PHY XGMII B TXC TXD P P P Medium MAC RS 36 C M M RXC S A D RXD 36 MDI /S/d/T/I/E/ /S/d/T/I/E/ /S/d/T/I/E/ /RF/BL/O/ /RF/BL/O/ /RF/BL/O/ Device A to Device B data and control transport • XGXS adjacent to Device A XGMII translates Idle /I/ to XAUI Idle /A/K/R/.
  • 40 and 100 Gigabit Ethernet: an Imminent Reality

    40 and 100 Gigabit Ethernet: an Imminent Reality

    WHITE PAPER 40 and 100 Gigabit Ethernet: An Imminent Reality 40 and 100 Gigabit Ethernet: An Imminent Reality Many of today’s data centers are running 10 Gigabit Ethernet (GbE) over both optical fiber and balanced twisted-pair copper cabling in their backbone infrastructure where large numbers of gigabit links aggregate at core devices. As more edge devices; like servers and storage equipment, continue to move to 10 GbE, the next natural progression is for the network core to require even faster connections within the data center. Fortunately, there is a solution that is now an imminent reality. Standards have been in development since 2008, and the Institute of Electrical and Electronics Engineers (IEEE) will soon release the 802.3ba standard that will support data rates for 40 and 100 GbE over optical fiber cabling. Both cable and connectivity solutions capable of supporting these speeds already exist, and vendors are in the process of developing active equipment. Now is the time to migrate data center cabling infrastructures to support this imminent technology. 40 and 100 Gigabit Ethernet: An Imminent Reality Key Market Drivers 100 90 From storage and IP traffic growth to the advancement 35% CAGR in Storage Capacity of technology across many market sectors, the drivers 80 that moved data transmission speeds from 1 GbE to 68 10 GbE over the past decade are now expanding as 60 forecasted, creating the need for 40 and 100 GbE. 49 Petabytes 40 37 10 GbE Growth 28 20 20 While the global Ethernet switch market experienced overall decline in 2009, the migration from 1 to 10 0 GbE continued in data centers across the world.
  • Latticesc/M Broadcom XAUI/Higig 10 Gbps Lattice Semiconductor Physical Layer Interoperability Over CX-4

    Latticesc/M Broadcom XAUI/Higig 10 Gbps Lattice Semiconductor Physical Layer Interoperability Over CX-4

    LatticeSC/M Broadcom® XAUI/HiGig™ 10 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1155 Introduction This technical note describes a physical layer 10-Gigabit Ethernet and HiGig (10 Gbps) interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch. The test was limited to the physical layer (up to XGMII) of the 10-Gigabit Ethernet protocol stack. Specifically, the document discusses the following topics: • Overview of LatticeSC™ and LatticeSCM™ devices and Broadcom BCM56800 network switch • Physical layer interoperability setup and results Two significant aspects of the interoperability test need to be highlighted: • The BCM56800 uses a CX-4 HiGig port, whereas the LatticeSC Communications Platform Evaluation Board provides an SMA connector. A CX-4 to SMA conversion board was used as a physical medium interface to cre- ate a physical link between both boards. The SMA side of the CX-4 to SMA conversion board has four differential TX/RX channels (10 Gbps bandwidth total). All four SMA channels (Quad 360) were connected to the LatticeSC side. • The physical layer interoperability ran at a 10-Gbps data rate (12.5-Gbps aggregated rate). XAUI Interoperability XAUI is a high-speed interconnect that offers reduced pin count and the ability to drive up to 20” of PCB trace on standard FR-4 material. In order to connect a 10-Gigabit Ethernet MAC to an off-chip PHY device, an XGMII inter- face is used. The XGMII is a low-speed parallel interface for short range (approximately 2”) interconnects. XAUI interoperability is based on the 10-Gigabit Ethernet standard (IEEE Standard 802.3ae-2002).
  • Optic Modules Datasheet

    Optic Modules Datasheet

    Data Sheet Optic Modules Product Description Juniper Networks® has platforms ranging from the Juniper Networks CTP Series Circuit to datasheet is intended to guide the user through the various options available when choosing an Packet Platforms, BX Series Multi-Access Gateways, E Series Broadband Services Routers, M optic module for a given platform depending on the architecture. Series Multiservice Edge Routers, MX Series 3D Universal Edge Routers, to the T Series Core Features and Benefits Routers. These platforms support multiple interface types and technologies such as Ethernet, ATM, and SONET. Depending on the deployment scenario, they support different pluggable The following table lists the different pluggable optic modules and supported platforms, along optic modules that can be selected based on distance, form factor, and wavelength. This with the technical specifications for each. Table 1: Optic Modules Matrix Interface Form l (TX) l (RX) Max SKU Description Platforms Standard Media Cable Type Factor (nm) (nm) Reach CTP-SFP-1GE-LX Small form-factor pluggable (SFP) CTP2008, CTP2024, and GbE SFP 1000BASE-LX 1310 SMF 9/125 10 km 1000BASE-LX Gigabit Ethernet optic module. CTP2056 MMF 50/125 550 m 62.5/125 550 m CTP-SFP-1GE-SX SFP 1000BASE-SX Gigabit Ethernet optic CTP 2008, CTP2024, and GbE SFP 1000BASE-SX 850 MMF 50/125 550 m module. CTP2056 62.5/125 275 m CTP-SFP-1GE-T SFP 1000BASE-T Gigabit Ethernet module CTP 2008, CTP2024, and GbE SFP 1000BASE-T Copper 4 twisted 100 m (uses Cat 5 cable). CTP2056 pair, Category 5 shielded RX-10KM-SFP 1-port 10 km GbE SFP adapter: provides E120, E320, ERX310, GbE SFP 1000BASE-LX 1310 SMF 9/125 10 km (1) SFP Gigabit Ethernet single-mode (10 ERX705, ERX710, ERX1410, km) physical port with an LC full duplex ERX1440 connection.
  • Modern Ethernet

    Modern Ethernet

    Color profile: Generic CMYK printer profile Composite Default screen All-In-One / Network+ Certification All-in-One Exam Guide / Meyers / 225345-2 / Chapter 6 CHAPTER Modern Ethernet 6 The Network+ Certification exam expects you to know how to • 1.2 Specify the main features of 802.2 (Logical Link Control) [and] 802.3 (Ethernet): speed, access method, topology, media • 1.3 Specify the characteristics (for example: speed, length, topology, and cable type) of the following cable standards: 10BaseT and 10BaseFL; 100BaseTX and 100BaseFX; 1000BaseTX, 1000BaseCX, 1000BaseSX, and 1000BaseLX; 10GBaseSR, 10GBaseLR, and 10GBaseER • 1.4 Recognize the following media connectors and describe their uses: RJ-11, RJ-45, F-type, ST,SC, IEEE 1394, LC, MTRJ • 1.6 Identify the purposes, features, and functions of the following network components: hubs, switches • 2.3 Identify the OSI layers at which the following network components operate: hubs, switches To achieve these goals, you must be able to • Define the characteristics, cabling, and connectors used in 10BaseT and 10BaseFL • Explain how to connect multiple Ethernet segments • Define the characteristics, cabling, and connectors used with 100Base and Gigabit Ethernet Historical/Conceptual The first generation of Ethernet network technologies enjoyed substantial adoption in the networking world, but their bus topology continued to be their Achilles’ heel—a sin- gle break anywhere on the bus completely shut down an entire network. In the mid- 1980s, IBM unveiled a competing network technology called Token Ring. You’ll get the complete discussion of Token Ring in the next chapter, but it’s enough for now to say that Token Ring used a physical star topology.
  • 10G-EPON Standardization and Its Development Status

    10G-EPON Standardization and Its Development Status

    © 2009 OSA/OFC/NFOEC 2009 NThC4.pdf 10G-EPON Standardization and Its Development Status Keiji Tanaka KDDI R&D Laboratories Inc. [email protected] Outline 1. Background and motivation 2. IEEE 802.3av standardization 3. Research activities 4. Development status 5. Summary ᵐ K.Tanaka, OFC/NFOEC 2009, Mar. 23-26, 2009 All Rights Reserved © 2009 KDDI, Tokyo 978-1-55752-865-0/09/$25.00 ©2009 IEEE 1 Outline 1. Background and motivation (a) FTTH growth in Japan (b) FTTH systems (c) Why 10G-EPON necessary? (d) When 10G-EPON feasible? 2. IEEE 802.3av standardization 3. Research activities 4. Development status 5. Summary ᵑ K.Tanaka, OFC/NFOEC 2009, Mar. 23-26, 2009 All Rights Reserved © 2009 KDDI, Tokyo FTTH growth in Japan The number of FTTH lines, more than 13 million at the end of Sep. 2008, exceeded the number of DSL lines in 2Q/2008. 20 Shifted to decrease StatisticsStatistics asas ofof Sep.Sep. 20082008 DSL 15 $ Number of lines: FTTH: 13.8 M DSL: 12.0 M FTTH CATV: 4.0 M 10 (Mobile: 92.0 M) $ Number of operators: FTTH: 171 5 CATV DSL: 47 CATV: 381 Number of broadband users [Million] 0 ‘02 ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 Year Source: Ministry of Internal Affairs and Communications statistics database ᵒ K.Tanaka, OFC/NFOEC 2009, Mar. 23-26, 2009 All Rights Reserved © 2009 KDDI, Tokyo 2 Flavors of FTTH systems High WDM-PON Apartment Data rate SS (Bandwidth) TDM-PON VDSL Efficiency High DSLAM Optical access system VDSL CPE 100Mbit/s CO or Residential house SS 1Gbit/s Media converter Single star Media converter Media converter Power Power splitter splitter Optical fiber PON Passive double star PON-OLT Power splitter PON topology is suitable for accommodating a lot of users and distributing broadcasting video services.
  • Cisco Catalyst 6500 Series 10 Gigabit Ethernet Modules

    Cisco Catalyst 6500 Series 10 Gigabit Ethernet Modules

    Data Sheet Cisco Catalyst 6500 Series 10 Gigabit Ethernet Modules Cisco data center switching delivers relentless velocity: Architecture scalability supports growth in any direction; Operational manageability maximizes service velocity and IT staff productivity; Comprehensive resilience addresses many potential sources of downtime. Figure 1. Cisco Catalyst 6500 Series 4-Port 10 Gigabit Ethernet Module Figure 2. Cisco Catalyst 6500 Series 8-Port 10 Gigabit Ethernet Module PRODUCT OVERVIEW The Cisco Catalyst 6500 Series has an 8-port 10 Gigabit Ethernet module and a 4-port 10 Gigabit Ethernet module. These modules support pluggable optics to support distances up to 80km over single-mode fiber, 300m over multimode fiber, and 15m over copper. The 8-port 10 Gigabit Ethernet module provides up to 64 10 Gigabit Ethernet ports in a single Catalyst 6500 chassis, ideal for deployment in the aggregation layer of LAN campus and data centers. Both modules are interoperable with the Cisco Catalyst 6500 Series Supervisor Engine 720 and provide 40 Gbps connection to the switch fabric. Building upon the award-winning Catalyst 6500 Series, these 10 Gigabit Ethernet modules are backward compatible with all existing Catalyst 6500 line cards and services modules, enabling service providers and enterprises to offer new Layer 2 through 7 services and network capabilities to increase revenue and user productivity without complete equipment upgrades. The Cisco Catalyst 6500 Series 10 Gigabit Ethernet modules are designed for deployment in the distribution and core of campus and data center for traffic aggregation or for interbuilding, points of presence (POPs), WAN edge, and MAN connections. These modules support IEEE 802.3ad link aggregation and Cisco EtherChannel ® technology for fault-tolerant connectivity and bandwidth scalability of up to 80 Gbps per EtherChannel connection.