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Using Hardware Interrupts for Timing Visual Displays and Reaction-Time Key Interfacing on the Commodore 64

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Using Hardware Interrupts for Timing Visual Displays and Reaction-Time Key Interfacing on the Commodore 64 Behavior Research Methods, Instruments, & Computers 1988, 20 (/), 41-48 Using hardware interrupts for timing visual displays and reaction-time key interfacing on the Commodore 64 RICHARD D. WRIGHT The University of Western Ontario, London, Ontario, Canada and MICHAEL R. W. DAWSON York University, Toronto, Ontario, Canada The use of hardware interrupts for presenting and timing visual displays and for controlling reaction timing on the Commodore 64 is described. The three sources of interrupts discussed are reaction-time keys interfaced through the user port to on-board hardware timers, the alarm of the 60-Hz real-time clocks, and the video raster. In a demonstration program, these interrupts are used to measure display durations, to change screen displays, and to coordinate the onset of reaction timing with the onset of screen changes. In addition, an externally generated inter­ rupt caused by a keypress is used to control reaction timing independently of CPU operations. The Commodore 64 is an inexpensive machine, yet it point produces an interrupt that causes the response and has many features that make it an attractive choice as a the latency to be recorded. In addition, a keypress causes laboratory computer (see Kallman, 1986). One of these Field 2 to be replaced by a text screen. If a key is not is that the hardware interrupts can be programmed quite pressed before a particular time interval has elapsed easily for precise control over the presentation and tim­ (3 sec), the time-of-day clock sends an interrupt signal ing of visual displays. This is not the case with some other that ends the trial and turns off Field 2. Different parts microcomputers. For example, the Apple II requires a of this demonstration program are referred to in the fol­ clockcard and other hardware modificationsto the mother­ lowing discussion. board for the same type of flexibility (see Reed, 1979). This paper provides a discussion of the use of Com­ Programming Interrupt Routines modore 64 interrupts for synchronizing and timing visual Interrupts on the Commodore 64 interrupt the program displays and for controlling the on-board hardware timers. currently being carried out by the 6510 CPU and cause Also, an example program is described for using the Com­ it to execute an interrupt routine before returning to the modore 64 as a two-field tachistoscope. When the pro­ original program. Interrupts are signals generated by hard­ gram is running, a field containing a fixation cross ware devices and can occur at any time within a program. (Field 1) is displayed for a specified duration, and then One example is the system interrupt. Every 16.67 msec, an interrupt signal is generated. This signal causes Field 2 one of the 6526 complex interface adapters (CIAs) gener­ to replace Field 1, starts a millisecond reaction timer, and ates an interrupt signal that stops execution of the cur­ turns on a hardware alarm. The subject's task is to search rent program and starts the system "housekeeping" rou­ Field 2 for the presence or absence of a particular target tine. Among the operations carried out at this point are object. Pressing one of the two reaction-time keys at this a cursor flash, a scan of the keyboard buffer, and an incre­ ment of the jiffy clock counter. Execution of the inter­ rupted program then resumes until the next interrupt oc­ The writing of this report was supported by a Natural Sciences and Engineering Research Councilof Canada(NSERC) postgraduate scholar­ curs. Because the routines that are run when an interrupt ship awarded to the first author, a York University President's NSERC signal is detected typically takes less than a millisecond grant awarded to the secondauthor, and NSERCGrant A2600awarded to be carried out, they are essentially "invisible" to other to Zenon Pylyshyn. We are grateful to lim Clark for directing us to operations of the CPU (e.g., the running of a BASIC documentation on the Commodore 64, as well as for making helpful comments on this manuscript. We also thank Barbara Snyder for her program). comments on the manuscript and Dan Pulham for his assistance in the Two types of interrupt signals can be generated within design and construction of the reaction-time key mechanism. Michael the Commodore 64. One is a nonmaskable interrupt Dawson is now at the Centre for Advanced Study of Theoretical Psy­ (NMI) signal. This type of interrupt can be generated by chology at the University of Alberta. Requests for reprints should be the RESTORE key, the CIA #2 timers and time-of-day sent to Richard D. Wright, Centre for Cognitive Science, Department of Psychology,Universityof Western Ontario, London, ON N6A 5C2, clock, and an external device interfaced to the FLAG pin Canada. ofthe user port. The second type of interrupt is an inter- 41 Copyright 1988 Psychonomic Society, Inc. 42 WRIGHT AND DAWSON rupt request (IRQ) signal. This signal can be generated housekeeping, must restore the register values before a by the CIA #1 timers and time-of-day clock, and by the direct return to the background. This is done by pulling raster beam register, which keeps track of the location the Y register value offthe stack with the PLA command of the raster beam on the video screen. The difference and transferring it to this register with the TAY command. between an NMI signal and an IRQ signal is that the lat­ The X register value is then pulled off the stack with the ter can be ignored by setting the interrupt flag ofthe CPU, PLA command and transferred to this register with the whereas an NMI signal cannot be ignored. TAX command. Finally, the accumulator value is pulled When an interrupt signal is sent, the following occurs: offthe stack with the PLA command, and a return to the First, the current values of the program counter and the foreground program is made with the RTI command. A status flags are saved on the system stack. These values similar procedure is used in the NMITEST subroutine in are recalled at the end of the interrupt routine so that the the Appendix for restoring the Y register and accumula­ interrupted program can run normally. Second, control tor values (see lines $CI03 to $CI06). In the sections that of the CPU is passed to a specific program (the interrupt follow, we describe how IRQTEST and NMITEST are routine). This is accomplished by examining the contents used to control the timing of displays and the measure­ of two RAM addresses that contain the least significant ment of response latencies. and most significant bytes of the starting address of the interrupt routine. These addresses are referred to as an A Millisecond Reaction Timer interrupt vector. For example, when an IRQ signal is de­ The Commodore 64 uses two CIA chips to control its tected, program control is passed to the routine whose input/output operations, and both chips are available for starting location is contained at addresses $0314 and $0315 programming by the user. Each CIA chip contains two (note that the $ prefix denotes hexadecimal numbers). 16-bit, 1.022-MHz timers that can be cascaded for tim­ Usually the addresses contain the values $31 and $EA such ing short durations with millisecond accuracy or greater, that the IRQ interrupt vector points to the system inter­ and a 6O-Hz time-of-day clock for timing relatively long rupt housekeeping routine starting at $EA31. When an durations, but with less precision. Both types of clocks NMI signal is detected, program control is passed to the run independently ofthe CPU. We have found this to be NMI interrupt vector at addresses $0318 and $0319, very useful for measuring reaction times in tasks such as which usually points to the interrupt routine starting at the visual tracking of moving targets presented on a $FE47. cathode ray tube (Pylyshyn, 1988) because responses can Two steps are involved when programming interrupts. be timed independently ofthe CPU operations that move First, a machine code interrupt routine must be written the targets. that performs the operations that are to occur as a result Multiple sources ofhardware timing allow for the pre­ ofinterrupt signals. Second, the contents ofthe RAM lo­ cise control over durations of different aspects of an ex­ cations examined when interrupts occur must be changed periment. For instance, in the programs described in this to point to the new interrupt routine instead of to the paper, the 16-bit clocks are used to measure reaction default routine. The INITIALIZE routine listed in the Ap­ times, while the time-of-day clock is used to limit the pendix illustrates these steps. Part ofthis routine involves viewing time of Field 2 to 3 sec. changing the contents of locations $0314 and $0315 to In the remainder of this section, we describe how to point to the IRQTEST subroutine instead of to the nor­ set up a millisecond timer that is completely independent mal IRQ server. After this change has been made, an IRQ of the Commodore 64 CPU. In particular, the program­ signal causes IRQTEST to run. Similarly, the contents ming of the 16-bit clocks of CIA #2 for millisecond tim­ oflocations $0318 and $0319 are changed to point to the ing and the construction ofa response key mechanism that NMITEST subroutine instead of to the normal NMI produces NMI interrupt signals when its keys are pressed server. are described. Also, an NMI interrupt routine is given It should be pointed out that when an IRQ interrupt sig­ for interfacing these two devices so that a keypress stops nal is detected, the values of the accumulator, X, and Y the millisecond timer and causes data to be recorded.
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