THE RICE INSTITUTE
THE ©ESIGI? o? THE coimoh SECTION OP mn RICE INSTITUTE COHPBTBR
by Philip Eogcaa bock
& musts smmttm to tm PACIJS»TT SO PARTIAL P0&mt£!&t3? OP THE REOHIREMEOTS POR m DEGREE OP RASTER OP SCXEHCE
HOUSTON, TERAS
Rap i960 $<. • —
£; <2. mmmm the %H»tk described in this thesis has Cohen piece over the last too yearn end represents the efforts of sev¬ ere! people. the author in no uey wishes to claim credit for ail of this worlc* However# in order to describe the design and operation of the Else Institute Computer Control
Section9 a thorough understanding of the circuitry is re¬ quired. it is this understanding* along with soma of the actual designs that this thesis is mast to represent. She author is especially indebted to »r. Martin Graham# without whoa© guidance this thesis would not have been possible, the author is also indebted to the members of the project staff, the staff is c snail one and con¬ siderable cooperation has existed eaoag its members. they are fed achats# project engineers Joe BlghorsGj head tech¬ nicians die Peal# technicians . John Sliffe# head program¬ mers Jane Griffin, programmers Jo Kathryn naan, program¬ mer# and dun Beard# programmer. Special achnoolodgement is also given to Ken tlataon of the Oklahoma University Staff# who mas tilth the Pice group for IS months# and to Billie Konaeta# who has been invaluable In the preparation of this thesis. hast* but certainly not least# the author gives credit to his wife Carolyn, for her steadfast moral support. Table o£ Contents
Pag©
X* Introduction 1
Am General Description 1
B* Operating featores and Capabilities 2
1* Arithmetic Section 2
2* Heaory 2
3* Xnput«»OuSput 3
4* Control section 3
XX* The Control Section 4
A, General 4 !• Diagram 3
2« Basie Register Circuit 6
3. Blocking Oscillator 9
B* Address Arithmetic 18
1. SwRagisters 18
2* Special Purpose Registers 22
3* Address Adder 23
4. Gating Circuits 20
3* Other Registers 3?
C, instruction Decoding 40
1# instruction Register 4©
2m Controlled Circuit 43 3. symbolic Representation 48
4. Timing Considerations 30
1X1. Appendices 58
A* Appendix 2 » Constffuceioa 60 B, Appendin XI- Field X 68
<«) Biot of Figures Page Figure 1 Bluets Diagram of Computer 1
Figure 2 Diagram of Control Section 9 Figure 3 Basie Flip-Flop circuit ? Figure k Sasic Blocking oscillator Circuit 11
Figure 9 Blocking oscillator Waveforms Ik Figure 6 Cora Checker and Waveforms It Figure t B-Sorieo Register Circuit 20 Figure 8 Special purpose Register Circuit 2k
Figure 9 Address Adder Circuit 8?
Figure 10 Read Address Adder Circuit 29
Figure 11 Gate Address Adder out circuit 31 Figure 12 Connect to Address Adder Circuit 3k
Figure 13 Clear S Register circuit 36 Figure Ik Operation Counter Circuit 38
Figure 19 Word Counter Circuit 39 Figure 16 Instruction Register Decoding circuit kl
Figure 17 All Purpose ’’and" and/or ’’or” Circuit 45 Figure 18 Symbolic Representation k? & k?a
Figure 19 All purpose Buffer* inverter* Converter Circuit k9
Figure SO Primed Timing Circuit 93 Figure SI Timing Waveforms 3k Figure 22 Timing Circuit 56
(ill) Figure 23 ftmt VI&& oi Contml Scceion 6l Figaro 24 Roar Viet? o£ fcho Control Soeeian 62 Figaro 2^ Fii$j«»Flop CUaaai® «■ Sabo Side 63 Figaro 26 FHp«Flop Chaaoio • Printed circuit Comsoofcor Side 64 Figure Qf All Forposo frenoisear Inverter* Converter m££az Circuit Board and translator Flip-Flop Board 63 Figaro 28 Ail Forpos© nandM aad/ar “or** Cireelt Board and timed tnput ’'•and" and/or "or” Blocking ooei Hates? Board 66 Figaro 29 eoatrol Section Output Baa Stractate 6f Figaro 30 field 2 * logic Megram 69 Figaro 31 Field I* allowing £i£g»£lop chassis, docod* lag boards and blocking ©acillatere ?0 Figaro 32 Field i, Reverse aids shewing interuiriag FI
(iv) IHTRODUCTIOH
GENERAL PESCRlgTlOB
the purpose of (his paper is to describe the cir¬ cuitry cud operation of the control, section of the Rice Xn- dtitute Computer. A few preliminary remarUo will be made about the general characteristics of the machine, but the reader is referred to the operation manual of the computer for the details of parts of the machine other than the con¬ trol section# A basic knowledge of digital computers is assumed#
the Rice institute Computer ie a large# high speed# binary# parallel# and asynchronous digital computer# it has a 32#?68 word electrostatic main memory and an aus- iliary memory of four magnetic tape units# the word length ie bits# the machine operates with internally stored programs# the machine is designed as a scientific rather than a business machine and features a very versatile or¬ der code#
the basic sections of the machine are shown in
Figure I# the arrows indicate the flow of information among the various sections#
Figure 1 2
A portion of the oritonetic section* ceiled the Central Distributor* Is an intermediate in the flow of moat information*
0PBRATI1TG .gSAOTBBS ASP CAPABStlTSBS
■ Arithmetic Section the arithmetic section consists of an asynchro¬ nous adder* throe 5b bit shifting registers* font 5b bit fast temporary storage registers* the central distributor* the ficticious null (0) register* one 5b bit buffer regis¬ ter for‘memory communication* font *?k bit buffer registers for input-output* parity and chcqU bit circuits and dri¬ vers for these registers* The adder fees an end-of-carry detection circuit which reduces the average add time to about 1*^ microseconds* Humber representation for the arithmetic operations io ttoae;|a complement”* Horde con¬ sist of a 6 bit exponent and a b$ bit mantissa* including a sign bit for each* giving a total of 5b bits* The base of the deponent is 256* giving a number range of from approximately to lo”7**. The shifting registers have provisions for shifting right or left by 1 or 8 places*
Memory The main memory is electrostatic* It contains
32*768 words of 63 bits (3b information bits* 1 parity bit* 6 cheeh bits and 2 tag bits). There Is one visual display tube for each memory bank. The 52*768 words are divided into four banks* each of 8* If2 words* The parity and check bits enable the computer to detect and correct 3 errors of 1 bit per word that occur in memory, The main memory has random access and has an average access time of 6 microseconds for reading and 312 microseconds for writing. When not in use, the main memory regenerates itself every 6b milliseconds* The total o£ 32,768 words requires an ad¬ dress of 15 hits# Addresses come directly from the control section, and words enter and leave the main, memory via the buffer register#. where. parity and. attach - hits, are derived*, Input-Output Input-output facilities for the computer consist of a high*»speed lino printer, a solid state paper tape read¬ er, a paper tape punch, end a eensole typewriter* A FIQKO- writer is used for.the preparation.of paper tapes for in¬ put to the computes,. .The state of bits,in the special pur¬ pose registers f 15 bit control registers) may he set from the operators console by means of switches on the console panel as well as by programmed instructions. Visual dis¬ play of the ifaiveresl register (Arithmetic), Instruction register. (Control), Special purpose registers. .(Control) end Control Counter register (Control) is provided at the operator's console* Control Section The control section accepts internally stored instructions and causes the machine to perform the opera¬ tions specified by the instructions* The operations spec¬ ified by the various bit combinations of the.instruction word (5b bits) are quite complex* A complete listing will h
be found in else operation manual for the computer, There are two general groups of operational there is straight* forward instruction decoding, the result of which is com¬ mand pulses going to other parts of the machine, and there is address arithmetic, which involves arithmetic operations which are performed within the control section, and end with an address which is used for a memory fetch, Shore is considerable inter-play between these two groups, but the circuitry naturally divides into these two classes* St is
the purpose of this paper to present the engineering fea¬
tures of these two groups,
TEE CONTROL SECTION
GENERAL
The various parts of the control section are identified in figure 2, The two basic groups of circuitry, described above, are shown separated by a dashed line. 5
w 6
Tuo basic circuits arc used extensively throughout the computer in general and in the control section in parti¬ cular* Ihee© two circuits and their operation will now bo described* Sasic Register Circuit;' One of the basic circuits used throughout Cho c ota pa ter in the bistable £lip»£lop* Shis circuit io need as"a binary storage cleaenfc* She circuit diagram ior the vaeuota tube £lip«£lop used in the Rice Conputer is chotm in Figure ;,5» 1 7
NJ $ i ^ 1^o \
I VM 'VD \j I S> * u^ u. I< I u i& Vb k, fc I I I□
KN
V gk$5; s*'4 ■»c Vi %xii Figure 8
She operation of this circuit is aa sollaws. 22 the tabs ware removed# points 2 end 7 would be at 4-28 volts due to the resistance voltage dividers. When the tube is placed in the circuit, the positive grid voltages tend to cause both triodes to conduct. this Is an unstable condi¬ tion and# due to Slight'differences'in;the1triodea^ one triode will conduct heavily and due to the lowered plate voltage of the conducting triode and the resistive coupling of plate to grid# will cause the other triode grid to ba¬ cons negative# thus# beeping it cut off. Shis is a stable condition# and the flip-flop will remain this way until forced to change state. The grid of the conducting triode is caught on grid current at 0 Volte and its plate is bot¬ tomed at about *50 volts. Shis voltage couples to the non¬ conducting triode grid through the 39k and 79k resistance divider and causes the noneca ducting triode grid to be about -20 volts, the capacitors may be added to speed the switch¬ ing action, the neon light indicates the state of the flip- flop. If the tube to which the mm is attached is con¬ ducting# the plate voltage is at <-50 volts# which means
100 volts ia across the neon lamp and it will ionise, She 120k resistor limits the current through the neon lamp.
Since either triode may be in the conducting state# the flip-flop is arbitrarily said to be in the **XM state when the left hand triode is conducting and in the ”0n state when the right hand triode is conducting, inputs may be made to either grid# and outputs may be derived from a!Cher grid or plate, She type of input and output used varies according to the particular function for uhich the basic circuit is used, Shis mill be described for each specific circuit, She grid returns of the various. £ Up-Slop re®
Sisters ore he.pt separate and separately fused in order to facilitate testing. If either fuse is removed, all the flip®flops are forced into one state, Shea the fuse is re® placed, the flip-flop should remain in that state, Shoo, by removing and replacing first one fuse and then the other, ail the flip-flops can be cheeked at a glance to see if they are marking properly. This visual check mould be impossible if not for the neon indicator lamps at each stage,
. Slocking Oscillator
another basic circuit used in the computer is the blocking oscillator, She blocking oscillator has several features mhich recommend it for use as a basic building block in the design of the control section. It can furnish a sharp clean pulse from a deteriorated or sioely varying trigger pulse «* £,e«, the pulse shape is nearly independent of the trigger pulse, She pulse pouer is high and the out¬ put impedance is lou uhich means that load capacitance can be charged to the desired voltage quickly* The transformer output aHoms considerable flexibility, outputs of either polarity, various voltages and at various D. C« levels can be easily obtained and the large available pulse power en¬ ables flexible circuit interconnections. 10
For those reasons* the blocked or monoatable block- ins oscillator was chosen for the basic control circuit, the circuit configuration need is ehotm in figure k» 11 Figure 12
& description of the circuit: operation is as follows* In the quiescent state* Slits left head triode is conducting and is in 1 as* of grid"current* She place la well beseemed at about 50 voice* She right hand cube is cat off by the *15 volt supply through diodes "a” and °bn* tJhen the left hand triads grid is pulsed negative with respect to the cathode bias voltagea the ttiode onto off* She plate voltage rises rapidly toward +*50 and this change is coupled to the right hand'triads grid by means of the 51 |ap£d capacitor* She positive pulse drives the right hand triode into grid current causing the Srlode to conduct* The plate bottoms placing about £80 volts across the tr&ns* former primary* the 8*tuc» secondary' is so wound that it further'increased the'grid drive* fhe current supplied by the secondary is limited by the ?50 ohm resistor* the net fluK in the core does not change due to the opposing currents in the plate and grid windings* and the rise in output voltage is limited only by the leakage inductance and the equivalent series resistance of the winding* She plate current is initially the amount required to supply the grid current through the transformer. She plate cur* rent then undergoes a linear increase obeying the rein* tion di/de e» B/&* since E is constant at £80 volts and % is presumed constant* this linear increase continues until either the tube can supply no more current or the iron core saturates and the Inductance drops* In either case* a point is reached where the tube can supply no further In* 15 crease is current. Since the fins in the core to no longer increasing? Che voltage drops and Che clremit can no longer maintain the current which has been established. Hence? the current begins to decrease. Shis further decreases the vol¬ tage? and now the circuit becomes highly regenerative in turn¬ ing off the plate current, the current through the tube can not reverse? so it reaches aero and remains there, the vol¬ tage induced in the secondary has now reached such o value as to cause diode nbn to conduct, the remaining energy stored in the circuit is dissipated in the 730 ohm resis¬ tor. this resistor is chosen to critically damp the cir¬ cuit with diode ”bH conducting? as well as limiting the ini¬ tial grid drive. Have forms at various points of the second triode are shown in Figure 3. Ik
Blocking Oscillator Wave Forms
Output Voltage Output Voltage with Ringing due to Strays
Grid Voltage Plate Current Note Region of Linear Rise
Top: Under Damped Back-kick Erratic Multiple Firing Bottom: Properly Damped (top) due to Under Damped Back-kick Back-kick (bottom) Figure 5 15
The cores that ore used saturate at about 3000 lines per square cm* For 0 16 Cura primary end a 300 volt: supply, ring the linear increases
V r&di/4t 't S 'Wdt s 10"'® where # is the llt» la the core in ■lines,- .8 is the numberef turns, end V is the sp«* plied voltage, dd/dt is 1870 lines per microsecond* Since the"area o2 Che core is about 1 am®* It would saturate ^in
3000/1870 « 1*0 microseconds. fhe measured pulse width is about 0.5 microseconds indicating that the core does not saturate*
She coses used ore ferrite MEn cores* One half of the core can be rotated with respect to the other half, in such a manner m to reduce the effective core area* In this manner the inductance can be reduced, thus giving a narrower pulse* this method is used whenever pulses nor* rower than usual are needed* For the 0*5 microsecond pulse, the measured linear increase in current is I50 ©©/microsecond* Shis implies an inductance of % = E/di/dt a 2 millihenries* Shis inductance is very dependent on any air gaps in the core circuit* therefore, a procedure was devised for checking the final assembly of the two halves of the ”E" core* A piece of test equipment was built that conveniently allows the user to apply a 308 volt step voltage from 0 leu impedance source accuse the primaries of the blocking oscillator transformers while they are in place in the racks* She linear current rise is observed on an oscilloscope and the overall per* 16 foraance evaluated, shorted turns or crocked cores are easily detected by this test procedure* since either fault gives rise to a very sharp rise in current due to low in* ductanee, typical 'wave forms* observed in cheeking the pulse transformers* are shown in Figure 6. the. circuit used for checking is also shoun* 17 Transformer Checking Circuit
Voltage Applied to Transformer Effect of Cracked Core under Test
r 9 i—1 r*r f ! (; u\ ,. .... - -1 - r- ■ . A \
Resulting Linear Current Effect of Shorted Turn Rise of Good Transformer Figure 6 18
ADDRESS AMTimSTXC The portion of the machine which deals with ad» drees arithmetic was shown pre\»iouoly in the diagram of Figure 2* This portion of the control circuitry performs the function of taking various 15 bit control registers and adding them in a manner prescribed by the instruction word, The eventual result is the 15 hit address of a particular piece of information which is stored somewhere in the machine. This may be a net? instruction or some operand to be used in the arithmetic section. The registers involved in the address arithmetic trill not? be described after which the address adder and the gating circuits will be discussed. The "B Series” Registers There are eight I5*bit "8 Series" registers. They are addressable and their addresses are: Register Octal Address
CC 0 Bl 1 32 2 B3 34 l B5 B6 I PF 7 There are four registers which are identical to the "8 Series" registers and which era also addressable. They arei Register Octal Address P2 77770 X 77772 TT 77776 FT 77777 19
Hoses Octal addraeo 77777 has binary equivalent off imUUUmn. 7he schoiaaeie which applies to those twelve registoss is shown in Figure 7. 20
9 j o i a i* 5 iu
uJ 00 Z 0 N Z
1 DNTROL UNIT SISTER SCHEMATIC r s u uJ a < a 4_ CQ a:
B RICE INSTITUTE COMPUTER § a: I tsl+l | as o 5f ! s i/i r» S' r»
i - <*3 - * -
t
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s ^ -J Li. r> UJ z i- Figure
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Each of the registers is a 15 hit resistor; each hit is a standard flip-flop circuit.
Input to the reelstar is by means of single-aided diode gating. By •‘single-sided** is meant that the “set to
1“ and "act to 0” (clear) inputs are both at the same grid,
A negative input forces the right hand triode to be non¬ conducting whieh in turn* because of the plate coupling* causes the right hand triode to conduct* placing the stage
in the "l1* state. Similarly* a positive input causes the
stage to be in the ”0” state, the input clasp voltage
(*£ with respect to -150) and its diode have two functions*
It gives a lot? impedance path to any hash at the input* and
it heaps diode "a" bach baised so that the input grid is essentially disconnected from the input diodes, the clear
input is common to all 15 bits of the register, fits 5U
resistor raises the clear pulse impedance so the register
can be set to "l" even in the presence of a clear pulse*
She output of these registers is connected to the
address or B adder* The output of only one side of the
flip-flop is needed* the amount of current needed by the
adder input connection logic is not great enough to warrant
using cathode follower outputs from the register* However*
the output does hove to be at ground level and more cur¬
rent is needed than eh© grid circuit of the register can
supply* therefore* the reference level of the entire re¬
gister is made -150 volts rather than the normal ground
level, this places the plate at ground level and allows as the output to be taken at the plate circuit, The plate circuit can supply the needed current*
The operation of the output circuit is as follows* When the stage is in the "0" state* the left hand triode is cutoff and point ”p” tends to he at *23 volts* This causes the plate clamp diode to conduct and the output voltage is forced to he the clamp voltage which is +2 volts* When the register is read* point "c" goes to *3 volts which has no effect on the output since the read diode is hack biased* When the stage is in the “l” state* the left hand tube is conducting and point Mp" tends Co be at a negative potential since the left hand trlodo requires more current in the on state than the +100 volt 22K circuit can supply* Thus* the output is caught at +2 volts by the read diode* When point *’r” goes to *3 volts* the output follows-giving an output of -5 volts which indicates a "1” has been read.
The output is a straightforward current switch. A crossover or speed-up capacitor is added from the plate of the right hand triode to the grid of the left hand triads in order to speed up the changes of state of the flip-flop* Hone is needed from the plate of the left hand triode since the grid of the right hand triode is set directly by the input signal* Special Purpose Registers
There are four 13-bit special purpose registers*
They are the Sense, Uodc* Trapping and Indicator registers* and they are addressable* Their addresses are: 22
Register Address Sense mn Mode im 3 Trapping ?7?7b Indicator 77775 The schematic o£ these registers Is shotra in Figaro 8» 24
5? IN ;* - [b S s J yHh
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M r! jgj N N jij i»i W ;gj !ai w I* £5 ■She basic circuit is the standard flip-flop* these registers connect to the adder and in addition* their outputs oust sapply some logic circuits* which is not true of the ”B Series" registers* Therefore* the output of the special purpose registers is taken Irma cathode followers and the circuit reference level is ground* The output to the adder is a current switch as it was for the "B Series" registers escept that it is taken at the cathode follower output rather than from the plate circuit* additional out- puta are taken from the cathode follower that is connected to the left hand trlede* These outputs are used in the logic of the instruction decoding* The input configuration of these registers is slightly different from the *B Series" registers. Separate inputs are available to both grids. This enables the stages to be set to the ”1" or ”0" state independently. This is done in order to meet the require¬ ments of the order code for the machine. These registers can be set by the operator by means of snitches located on the operator's console. Crossover capacitors wests used between both plate- grid circuits since sometimes one grid is set directly and at other times the other grid is set directly. The ”11" or address portion of the instruction re¬ gister is very similar to the special purpose registers* The Address Adder The registers described so far are divided into two groups* Any one of one group may be connected to one digits input of the address adder and any one oS the other group ©ay he connected to the other digit input, The too inputs to the adder are labeled A and B. the registers are grouped as follousi B digit input A digit input Register/Oetal Address Register Octal Address CC« FS 77770 B1- Bouse 77771 B2« K 7777a B3- llode 77773 B4« Trapping 77774 B5« Indicator 77775 B6--—~«OOQ06 M portion of instruction pp****«**OOO07 Tf——77776 p^*.—«*7?777 Thus, the address arithmetic consists o£ various sequences of additions of an A input to a B input register. The schematic of fhe circuit that performs the additions is shown in Figure $« Figure 28 This adder is, in most respects, identical to the arithmetic adder and a detailed description of its opera* tien will he found in the operation manual description of the electronics of the arithmetic section, The schematic is included here for completeness. The odd and even option on the inputs is due to the fact that to save carry propagation time the carry is amplified only once per stage. Hence, it changes sense (i«c,, Is inverted) every stage. Therefore, the digit in* puts must he inverted every other stage. The basic addi* tion is performed by the current Quitches as indicated in the drawing (diode logic), A “I” is always indicated by aero volts at the output pentode grid and a ”0” is always represented by *15 volts, Cating Circuits The Address Adder is read and cleared olmultane* ously. It is cleared by disconnecting the inputs. Due to the delay line in the output circuit, the contents of the adder are available for 0.4 usee after the input has been disconnected. During this time the read address*adder blocking oscillator is pulsed. The read circuit is shown In Figure 10, 29 i.%xn Figure 10 X n 6 30 She e£2ect oS the Reed Blocking Oscillator is to pulse the supply voltages clous 15 volts. IS the stage had a "1” input, this uould taafce the grid 5 volts positive with respect to the cathode and the tube youId conduct* tS the stage had a u0" input, The grid reoalao at least 10 volts negative t?ith respect to the cathode, vhich t?ouid not pro«» duce an output* the outputs of the address adder are ahoua in the ochesaatic oi figure 9. Host outputs are 1 turn Bindings* Bhich output is utilised depends on the bias to uhicb the starting end ©£ the Binding is returned* The circuit uhiefa controls these biases is ahoun in figure 11* 31 k AZ074 MATERIAL i DRAWING NO. IS! i A/OA/f I Q 0. -I 3 -/$-£& a. DATE SCALE < <*) & tie X N (0 ID z6 - * | REVISIONS 1 V/) VO S'j \ 0 S ft »0 "U ^ 4 *> t * v V) * * ^>s S>» \ i Jo> ** £> V ^ * •Vixn Figure 11 i z N The circuit is a transistor Slip-Slop* IS it is in the ''l*' seats, the BA output pulse $000 bo lot? ground and sets a “l” into the register to which the winding ia physi¬ cally connected, if the transistor ia in the aero 0States, the register cannot ba act whether there ia a pulse or not since the transformer output never goes below ground* One of these Slip-Slops esista for each register to which there is a one turn input (output from B Adder}* An oneeption to this type of “!>**0 gating'* is the Adder output to the Hemory Address Blisses* this gating requires coincident pulses* Shore are two address busses for each stage (AB* and AS") since the memory address input is double sided* The reading the the B Adder and the gating to Address Bus must coincide to accomplish gating* She cir¬ cuitry is shown on the schematic of Figure 9* the gate pulses are achieved from the standard blocking oscillator circuit. Bating to the address busses charges the bus capacity, and the address remains on the bus until the memory te ready to accept an address (12 psee maximum}* When the memory has accepted the address* it pulses a blocking oscillator that clears the address input busses* She adder outputs to ”B Series” registers are referenced to -IpO volts and the other one turn outputs are referenced to ground* Thus* the circuit of Figure 11 is used an two chassis* one whose supply voltages are with respect to -15Q volts and one whose supply voltages are with respect to ground* 33 Inputs to the adder are also controlled by aeaas of transistor £llp*£iops* She schematic is shown la Figure 12* She ainus 5 volt signal connects the particular re» gister to the adder as described on page 22» dll of these circuits are referenced to ground* 3k -B'/ixn Figure 12 35 Dben gating a new number to a register £rom the 8 Adder* the register mast be cleared# 2£ the clear pulse is>shorter than the set to *’I” input pulse then both pulses can occur at Site same time, Tm DC Xe^el from the Iflip- flop (Figure 11) that controls where the Adder output is sent also controls which register gets cleared, She clr» cult is shown in figure £>• 3 6 ■ wxii Figure 13 37 If the register has been selected, che oelect level (cir¬ cuit of figure 11} trill be *2 and a positive pulse from Che Clear Blocking oscillator trill cause diode "a” to con* duet, creating a clear pulse at the selected register* A 0-6 shift in level is accomplished by the transformer* The clear pulse is very narrow* and if the stage is being set to a "l” by e new number, the clear pulse will be override den and a ”1° will be set* This circuit is used for clear* ing the ”B Series0 registers* The Sense, Mode, Trapping and Indicator registers are not cleared automatically, but must be cleared under program control* Other Eeglstero There are three additional registers whose inputs come from the B Adder* They are the operation counter and two word counters* Their schematics are shown in figures 14 and 15* They are binary scalars with provision for car* ry suppression so that new numbers may be set in* The operation counter has provisions for detecting when the counter is within 6 counts of being full and all three have provision for detecting when they are full* Their schema* tics are included here for completeness* D/OOS C///7S/S ST/?S£ d M//M 1 1 1 U ! s *< Q i l k * 38 5 $ OPERATION COUNTER i 3 i i! 3 *■ VI •0 1 ! £> 3 I •H P4 60 p u 0 39 *Al Figure 15 sj (tjvry ■is; k!V* i- *>! :u fg* ^b>‘> §S§Syii K. I 40 Xt?StRPCtSOfl DECOD1KC Instruction Register the instruction Register 4s 54 fries in length* Sash frit is represented fry a standard flip-flop circuit* According to the order sods (sec operation manual), the ia- struction word is decoded either 3t>ifco at a time, 2 frits at a time or singly* this decoding is accomplished fry diode "and** circuits* the typical instruction stage with cathode follower outputs, the diode decoding network and transistor buffet stages are shown in Figure 16 • the H£i!l, or address portion, of the Instruction Register, which consists of the last 15 frits, is very similar to the Special purpose Regis* tors (page 25)* Figure 16 Bote that the input to each buffer stage is a too input or three input "and" circuit as shown by the table at the right of Figure 16, Such buffer has too loreIs of output* the use of these two loreIs will be described in the next section* the operation of the buffer stage is as followsj each Stage of the flip-flop register has its grids either at aero volts due to grid current or at -15 due to the diode catch on one grid or the clear return on the other* The “l'1 state is defined arbitrarily as being equal to 0 volts and the M0M state is *19 volts; When all of the inputs to a-huffer stage are aero volts, point X tends to become eero volts* This forward biases the base emitter junction of the top transistor and it goes into conduction placing its output at approximately -5 volts; Point X be¬ comes -9 welts lose the voltage drop across the forward biased emitter base junction; The 990 ohm resistor in¬ creases this forward drop about a volt placing point X at about -4 volts which* after the drop across diode McM* leaves point "hn at a positive potential with respect to -5 volts, this leaves the bottom transistor cut off and its output voltage at -SO volts due to the catch diode* If any of the inputs is -19 volts* point X tends to become -19 volts* this bach biases the top transistor and its output becomes <#>10 volts due to the diode catch; the bottom transistor becomes forward biased and conducts* leaving its output at approximately -9 volts* Point "b” becomes -9 plus the base emitter diode drop or about -9*9v. 43 Shis back biases diode “e" and the bottom transistor has available 2 ma of base current* Here that s ma of base current are switched into whichever transistor is conduct* log. this allows the buffer stages to maintain their out* put levels with about 100 ma if necessary* to facilitate the checking of those buffers* the incandescent lamps were added (Figure 16)* they light if the decoded input Is a "1”* As can be seen from Figure 16 on page 41* it takes four boards to completely decade 3 bits* the flip*flop chassis are wired two triodea per chassis* the ©sera tubes are left available to be used for special functions as the need arises* thus* four printed circuit connectors are available for each three tubes* Controlled Circuit Host of the remaining circuits in the control sec* tion are blocking oscillators* described on pages 9 to 16* Some additions to the basic circuit will now be made* there are two convenient places to control the flow of pulses through a series of blocking oscillators* One of these is the input grid* Consider the input configu¬ ration in Figure 5* Any combination of "and" and/or “or** circuits that cause the input to go below *15 will cause the blocking oscillator to trigger* Available from the instruc¬ tion buffer decoder is a level named •'bogie0* which is *20 volts for the “1” condition and *9 volts for the **G” coadl* tion* Xt is this output that is used in various diode Mand° and/or "or'* circuits to control the input grids o£ con¬ trol blocking oscillators* &. printed circuit board was de¬ signed that allows a flexible verity of diode "and** and/or **or” circuits to be used* (See Figure It.) s £ fc 0 O-J 0 ^ IX MATERIAL g^ § i z:/ SCALE R 0 k, N 0*4 i* CHK’D TRACED >• a DATE o " N « * n z I REVISIONS X 1 A * U * si \ \ X >5 s^sc" . <3 X S> n -* ii ? vl ■\ > v ^ o u $ t \ \ -a Hv 0 c x N 1 I 11^ ! ft ft C> v , is II I j^t> k* K- ■$£>* ^N ^ "fc $ < ■ * '/4xn Figure 17 zi r»n 0 46 Another convenient control, point in at the output winding# fhe blocking oscillator provides about 15 volt pulses for a one turn output winding. X£ the pulse starts from a DC level of -5 volts* it will reach a negative peak value of -20 volts# This, if used alone or as one input to an “and" and/or ”orH input to another blocking oscillator* will cause the sent blocking oscillator to trigger (assua- ing that other “and” and/or "or” conditions are act)# Sim¬ ilarly* if the pulse starts from <*10 volts* it will reach a negative peak value of only -5 volts which is not enough to trigger the nest blocking oscillator in the series# $heaa two levels (-5 o 1 and *10 « 0) are the bias level outputs of the instruction decoded buffer circuits. (See Figure 16#) Symbolic Benresentation In synthesising the desired order code of the machine by means of the circuits described so far* a symbo¬ lic representation is useful# fho symbols used are shown in figure 18# a hi 3 y// to/J F/e-'c fho/itC fo-'J:/vV pvt D /&•■ ■, <./"/- : //ty. /,i0 / /-<-• ?/ ■.- o f/r?/? /z c/7 f v>.-.. B233S v 3 A'C O'/ /T'-V- O/tferns 4/ . 7/i-- Ou7<:/iS C{/ C cD7//;r:.! dC : / A B C D £ F G ’ > l St./fe 71 / O V -/f-y O ~/5v o v A 8 0 > C//iaC-:orJerJ 77co7//jf 77g//et'/r}f : 77/G /'e/- Ac/oe/tt.f <2 0u7/;?i-/>?o /./reviA C2u //■ ‘! 1-3 cii-r‘ /■;. „ 77 2 0 r‘ S~ Cr ZX? 3Xp on7' 2. 7a /I 3i. / 3D; Oecod//!'< 2D; &>'/,o (Jo/far, :• SU-/A'i-"r 7 teve/s. 7lcs* /v, k 2a / 7U W "07: 'J*J ■ * "Ot, "err, A 1,1 a.{-c of/Z? (Ysoc- 'e 7>/-':'. Sw/e JL £ ^2 ^ o/? tyf/cc/7 Co/t 7t O/Ddc /h;r- • Oh r 33/ To r OUTOf/ *3/ //HJfir'fo Of)/,' / S/t/lrj/r . T/ ' A /-/} ftr Cc/fcH/f c/iC/p: <■/?: / A- t B A /A C/?&'/-lt-} f;‘ J, (.//ycTB'"3'Zf ( tJ / Jp;.. 77- /St75/j to t- $u Yr (*t- Figure 18 oa Apif /j /o 3 S/C/* cJ /j, 47a S /ccfors 7e Coti/ffarpQ’t fs f/ocf'/m (^sc/My/oi-si Yc/s/c Y/ocYi/iy Oscs/Yc/fo* cfrcotY -‘5 *r4t>o>rt on $tVj. 82100 A 0/> /parcel/ . Sytrfa 7/c a /fan,- ts?irfr'c.Gf/ Aecf&ftC} 7e rcyressufs ■/-As . Yotfpsf n?s,ss 7o<-s vtiej fpet h S YiomtC ir p r / t-if of t-y OW*f . c/artypniG u>/i>d//tjy $. 77} e reeYo'nyfe Ye/Yeied L u>/fh7t) P/ip /cft-ps uei'Y't s' 7 rec/aryf reypesca 7s c/io^e /topuf Yo$/c am' sinY/or- "or" c/rcui'Y'?. . Y/JAUYS fofYtesc iec~7efet*jfes Mosf he ■> f 77e / fy.7Ae cith'i-l'ofiefs fr?ptesi?/}7~ / -fairn 7(rcm$ To*-met- O Using these symbols* the Ingin of the order coda was implemented, In synthesising the order code* most!: of the logic neadad can be located physically on the blocking oscillator diode boards* However* some “and0 and/or "or" circuits are quite involved and are located elsewhere. Al¬ so* voltage levels giving control information which origi¬ nate £com various parts of the machine are not always com* pa table with the levels needed for control. For these rea¬ sons there are several chassis in the control section which are ail purpose decoding and buffering circuits, fhe printed circuit boards are paired. One is for diode "and" and/or ••or1' circuits and the other contains sin all pur¬ pose transistor buffer* inverter* converter circuits, She diode "and” and/or "or" board is the same as that shown in Figure It on page 45* the all purpose transistor board is shown in Figure ! <* t DIAWINO NO. MATEtlAl S 1 gZ 1/?at// * Vi 2 8 > 09 N •C j a 2s7c//Y/ $ i 3* i J/fdJ/7 0 09 - $ 2/7 tffa'Jno S" 1 S i ’tS&2/?0 0^- Figure 19 50 gltalng Considerations SUcee are several places in Che execution of an instruction where a time* delay is seeded. For instance* If Che Address Adder is being used* tine oust be allowed for the adder carry to finish propagation before the cor- reet output is available. Bsuolly delay lines are need for this purpose$ however* as the machine is "tuned up” and various functions are node to perform more smoothly* the time they take is reduced. Shis usually means changing delay lines. Tim net result of this procedure is costly and inconvenient. In the Sice Computer a circuit has been devised that alloms a variable time delay and uses leas expensive components. Suppose it is deeired to perform a function A and* after a time delay t» perform another function B* Symbolically* One may to acheivo this is by using delay lines. Another way is as follows. At the time A is performed* a timer is set and the blocking oscillator that is to perform B is prim¬ ed. Uhan the required time has elapsed B is triggered. 531 extr The circuitry which performs this will now bo described* The operation of the primed circuit can best be understood by considering Figure 20 end Figure 2i« Before a timing sequence begins* both HT and ISf are held at aero volts and points E and F arc at -5 volts* When the sequence begins* H§ Is changed te **20 volts and point F becomes «*25 volts* When a priming pulse arrives* point E is discharged to **20 volts* After the correct time has elapsed* H? is changed to aero volts and 1ST is changed to «20 volts* Since the voltage across the capacitors 0 and 0 cannot change in* stantaaeously* point F returns So -9 volts and point E be* comes «*h9 volts*. When point S goes below *29 volts* the Zener diode breaks down end the timed input is applied to the amplifier tube of the blocking oscillator associated with this input circuit. Thus* two conditions must be sat* Isfied for the blocking oscillator to trigger* the primed circuit must have been primed and the HT and W flip-flops must have changed state* Thus* at time nss“ in Figure 21* 32 no output exists since this circuit waa not primed* She maximum allowed time delay la limited by 31 ppfd condensor, the 22 megohm resistor and diode leakage* Two capacitor circuits are used so that there ia no recovery time problem* Aa can be teen from Figure 21* only one capacitor is needed to do the timing* However* if a second priming pnloe follows in the interval before UT reverses state* the circuit would be Inoperative with only one capacitor* Thus* a second circuit ie used so that no matter what the sequence, ■ at least one capacitor is ready to accept a priming pulse* M4hdtt and/or "or** circuits may be used in con June* cion with the input to the primed circuit'ae well ao normal inputs directly on the blocking oscillator grid, which may also be Mand” and/or “or*1' Inputs* Tka primed'circuit and printed circuit board'which allows this■flexibility is shown in Figure 20. Timing wave forms are ■ shown in Figure 21* 53 Figure 20 54 TIMING WAVEFORMS Start Sequence Bad Sequence i 4 -20 O -20— Waveform at wMTn x -5* Input to be delayed -20 Waveform at "A” : J ir Delayed input Waveform at 4 Figure 21 55 The Set Tltset signal is a positive pulse iton £ blocking oscillator secondary* Those pulses ere sent to the circuits as shewn in Figure £2* 56 5? There may be any number of these circuits do* pending on the number of different delays required* For any one circuit each diode input; rap lace a a delay line* For one input# the circuit is more costly than a delay lino# but has the advantage of variable delay length. As the number of inputs increases# the circuit costa are almost unaffected and the ©atra “delay lines" are essentially free* In sumary# each circuit (shown inside dashed lino on Figure 22) represents a delay line of different length (which is adjustable) and each diode input represents a* nother delay line of that length* The circuit operation is as follows* The transis¬ tor A is normally conducting and its output is 45 volts# and the capacity C is charged to 45 volts less the forward biased emitter base diode drop* A set timer pulse appear¬ ing at any of the inputs forces point K to become 415 volts* This pulse is from a low-impedance source (biociting oscilla¬ tor). Pulses may vary slightly in height* Therefore# the input is connected through a resistor to raise the impe¬ dance so that a diode catch may limit the input amplitude to 410 volts* This input signal turns off the transistor by bach biasing the emitter base junction and causes the output to become 0 volts due to the emitter base Junction of transistor B. Transistor A remains cut off for a time dependent on E| and C^» The desired range of delays may be achieved using either a or C as the variable element* Variable capacitors are less expensive so they are employed* 38 Xhe nominal delay is see by putting the capacitor at aid** range and selecting of fixed a to give roughly the. desired delay* The capacitor can then be adjusted to achieve the desired delay. She output of transistor B is normally -SOvolto. Uhen any of the delay circuits are turned off, the output be¬ comes 0 volte, and it remains 0 volts until the delay time has clasped. %£ too or more delay circuits are turned off in the same time interval, the output remains 0 volts until the longest delay time- has clasped, and then the output"of transistor B becomes -20 volts. She output from transistor B is differentiated; the positive pulse is clipped, the negative pulse is used to trigger the US flip-flop mhich is a complementing flip-flop* the output of this flip-flop is sent to several Slave circuits - mhos o' outputs mahe BX and Hf available throughout the control section at lorn impedance, * APgsnozcss An idea of the physical construction of the com¬ puter is given by the photographs in Appendix 1* the var¬ ious registers and general construction are shove, the eventual result of operations in the control section is command pulses going to other parts of the com¬ puter* Command pulses leave the control section via one turn ulndlngo on various bloehiug oscillators, fheso pul¬ ses may have to travel a considerable distance* So reduce the ringing, resistance wire is used* the command pulses 5 9 cult through the control, section vie a bos structure undo? the false floor of she computer. This is shown in figure 29* Since command poises with the same destination nay o*» riginace several places in the control section, they enter the hoe structure via diodes at the hotton of the control racks* Thus* each has is essentially an "or" circuit for a partieslor function* Appaadia 21 includes a photograph of the cir** caitry and wiring of the first 6 hits of the instraction, called field 2* along with the symbolic diagram represent** ing the order code* (See instruction manual). Append!:! I Phonographs of Control Section 61 Front View of the Control Section 6 2 • - i I 1 !.v >•:i rji rI r iI / rI r fI r rI r rI r iJ V _ • 1.1 I ,1 I I I . I I ill I I I I I |\ c • • 111 J »■! ,*•» ui i li i m i' i«1114 • i I«^ f f i i r f r (f^. c *H _ 5 1.1 1 1 1 1 . S 1 3 1 1 1 3 "l 3 3 3 l\ w ' * 1 v 1 * i i :,<•» il» L«l - • i »' i % : i i fn H { It ( ( * (\, u a> 91111119 9 9999999199 to m‘> ’ vrn i W.W//WWwi'i t w o >4 4-t C o V iM (iUWukv u Qi Is I I a a a § JS » ^ " «,* ‘ .1 > * JfA ' * rf # u r[ ^ i ,i ,,, 44 Figure 24 O 9 >93 v 3 I- <0 Hi PS 65 ip-Flop Chassis - Tube Side 6 4 Flip-Flop Chassis - Printed Circuit Connector Side 65 Top: All Purpose Transistor Inverter, Converter Buffer Circuit Board Bottom: Transistor Flip-Flop Board Figure 27 66 Top: All Purpose "and ' and/or "or" Circuit Board Bottom: Timed Input "and" and/or "or" Blocking Oscillator Board Figure 28 67 Control Section Output Bus Structure Appendis %1 Field 1 Z^/'G/CZ Z Zoy/c Z)/crgr 69