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The Design of the Control Section of the Rice Institute Computer

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The Design of the Control Section of the Rice Institute Computer THE RICE INSTITUTE THE ©ESIGI? o? THE coimoh SECTION OP mn RICE INSTITUTE COHPBTBR by Philip Eogcaa bock & musts smmttm to tm PACIJS»TT SO PARTIAL P0&mt£!&t3? OP THE REOHIREMEOTS POR m DEGREE OP RASTER OP SCXEHCE HOUSTON, TERAS Rap i960 $<. • — £; <2. mmmm the %H»tk described in this thesis has Cohen piece over the last too yearn end represents the efforts of sev¬ ere! people. the author in no uey wishes to claim credit for ail of this worlc* However# in order to describe the design and operation of the Else Institute Computer Control Section9 a thorough understanding of the circuitry is re¬ quired. it is this understanding* along with soma of the actual designs that this thesis is mast to represent. She author is especially indebted to »r. Martin Graham# without whoa© guidance this thesis would not have been possible, the author is also indebted to the members of the project staff, the staff is c snail one and con¬ siderable cooperation has existed eaoag its members. they are fed achats# project engineers Joe BlghorsGj head tech¬ nicians die Peal# technicians . John Sliffe# head program¬ mers Jane Griffin, programmers Jo Kathryn naan, program¬ mer# and dun Beard# programmer. Special achnoolodgement is also given to Ken tlataon of the Oklahoma University Staff# who mas tilth the Pice group for IS months# and to Billie Konaeta# who has been invaluable In the preparation of this thesis. hast* but certainly not least# the author gives credit to his wife Carolyn, for her steadfast moral support. Table o£ Contents Pag© X* Introduction 1 Am General Description 1 B* Operating featores and Capabilities 2 1* Arithmetic Section 2 2* Heaory 2 3* Xnput«»OuSput 3 4* Control section 3 XX* The Control Section 4 A, General 4 !• Diagram 3 2« Basie Register Circuit 6 3. Blocking Oscillator 9 B* Address Arithmetic 18 1. SwRagisters 18 2* Special Purpose Registers 22 3* Address Adder 23 4. Gating Circuits 20 3* Other Registers 3? C, instruction Decoding 40 1# instruction Register 4© 2m Controlled Circuit 43 3. symbolic Representation 48 4. Timing Considerations 30 1X1. Appendices 58 <i> A* Appendix 2 » Constffuceioa 60 B, Appendin XI- Field X 68 <«) Biot of Figures Page Figure 1 Bluets Diagram of Computer 1 Figure 2 Diagram of Control Section 9 Figure 3 Basie Flip-Flop circuit ? Figure k Sasic Blocking oscillator Circuit 11 Figure 9 Blocking oscillator Waveforms Ik Figure 6 Cora Checker and Waveforms It Figure t B-Sorieo Register Circuit 20 Figure 8 Special purpose Register Circuit 2k Figure 9 Address Adder Circuit 8? Figure 10 Read Address Adder Circuit 29 Figure 11 Gate Address Adder out circuit 31 Figure 12 Connect to Address Adder Circuit 3k Figure 13 Clear S Register circuit 36 Figure Ik Operation Counter Circuit 38 Figure 19 Word Counter Circuit 39 Figure 16 Instruction Register Decoding circuit kl Figure 17 All Purpose ’’and" and/or ’’or” Circuit 45 Figure 18 Symbolic Representation k? & k?a Figure 19 All purpose Buffer* inverter* Converter Circuit k9 Figure SO Primed Timing Circuit 93 Figure SI Timing Waveforms 3k Figure 22 Timing Circuit 56 (ill) Figure 23 ftmt VI&& oi Contml Scceion 6l Figaro 24 Roar Viet? o£ fcho Control Soeeian 62 Figaro 2^ Fii$j«»Flop CUaaai® «■ Sabo Side 63 Figaro 26 FHp«Flop Chaaoio • Printed circuit Comsoofcor Side 64 Figure Qf All Forposo frenoisear Inverter* Converter m££az Circuit Board and translator Flip-Flop Board 63 Figaro 28 Ail Forpos© nandM aad/ar “or** Cireelt Board and timed tnput ’'•and" and/or "or” Blocking ooei Hates? Board 66 Figaro 29 eoatrol Section Output Baa Stractate 6f Figaro 30 field 2 * logic Megram 69 Figaro 31 Field I* allowing £i£g»£lop chassis, docod* lag boards and blocking ©acillatere ?0 Figaro 32 Field i, Reverse aids shewing interuiriag FI (iv) IHTRODUCTIOH GENERAL PESCRlgTlOB the purpose of (his paper is to describe the cir¬ cuitry cud operation of the control, section of the Rice Xn- dtitute Computer. A few preliminary remarUo will be made about the general characteristics of the machine, but the reader is referred to the operation manual of the computer for the details of parts of the machine other than the con¬ trol section# A basic knowledge of digital computers is assumed# the Rice institute Computer ie a large# high speed# binary# parallel# and asynchronous digital computer# it has a 32#?68 word electrostatic main memory and an aus- iliary memory of four magnetic tape units# the word length ie bits# the machine operates with internally stored programs# the machine is designed as a scientific rather than a business machine and features a very versatile or¬ der code# the basic sections of the machine are shown in Figure I# the arrows indicate the flow of information among the various sections# Figure 1 2 A portion of the oritonetic section* ceiled the Central Distributor* Is an intermediate in the flow of moat information* 0PBRATI1TG .gSAOTBBS ASP CAPABStlTSBS ■ Arithmetic Section the arithmetic section consists of an asynchro¬ nous adder* throe 5b bit shifting registers* font 5b bit fast temporary storage registers* the central distributor* the ficticious null (0) register* one 5b bit buffer regis¬ ter for‘memory communication* font *?k bit buffer registers for input-output* parity and chcqU bit circuits and dri¬ vers for these registers* The adder fees an end-of-carry detection circuit which reduces the average add time to about 1*^ microseconds* Humber representation for the arithmetic operations io ttoae;|a complement”* Horde con¬ sist of a 6 bit exponent and a b$ bit mantissa* including a sign bit for each* giving a total of 5b bits* The base of the deponent is 256* giving a number range of from approximately to lo”7**. The shifting registers have provisions for shifting right or left by 1 or 8 places* Memory The main memory is electrostatic* It contains 32*768 words of 63 bits (3b information bits* 1 parity bit* 6 cheeh bits and 2 tag bits). There Is one visual display tube for each memory bank. The 52*768 words are divided into four banks* each of 8* If2 words* The parity and check bits enable the computer to detect and correct 3 errors of 1 bit per word that occur in memory, The main memory has random access and has an average access time of 6 microseconds for reading and 312 microseconds for writing. When not in use, the main memory regenerates itself every 6b milliseconds* The total o£ 32,768 words requires an ad¬ dress of 15 hits# Addresses come directly from the control section, and words enter and leave the main, memory via the buffer register#. where. parity and. attach - hits, are derived*, Input-Output Input-output facilities for the computer consist of a high*»speed lino printer, a solid state paper tape read¬ er, a paper tape punch, end a eensole typewriter* A FIQKO- writer is used for.the preparation.of paper tapes for in¬ put to the computes,. .The state of bits,in the special pur¬ pose registers f 15 bit control registers) may he set from the operators console by means of switches on the console panel as well as by programmed instructions. Visual dis¬ play of the ifaiveresl register (Arithmetic), Instruction register. (Control), Special purpose registers. .(Control) end Control Counter register (Control) is provided at the operator's console* Control Section The control section accepts internally stored instructions and causes the machine to perform the opera¬ tions specified by the instructions* The operations spec¬ ified by the various bit combinations of the.instruction word (5b bits) are quite complex* A complete listing will h be found in else operation manual for the computer, There are two general groups of operational there is straight* forward instruction decoding, the result of which is com¬ mand pulses going to other parts of the machine, and there is address arithmetic, which involves arithmetic operations which are performed within the control section, and end with an address which is used for a memory fetch, Shore is considerable inter-play between these two groups, but the circuitry naturally divides into these two classes* St is the purpose of this paper to present the engineering fea¬ tures of these two groups, TEE CONTROL SECTION GENERAL The various parts of the control section are identified in figure 2, The two basic groups of circuitry, described above, are shown separated by a dashed line. 5 w 6 Tuo basic circuits arc used extensively throughout the computer in general and in the control section in parti¬ cular* Ihee© two circuits and their operation will now bo described* Sasic Register Circuit;' One of the basic circuits used throughout Cho c ota pa ter in the bistable £lip»£lop* Shis circuit io need as"a binary storage cleaenfc* She circuit diagram ior the vaeuota tube £lip«£lop used in the Rice Conputer is chotm in Figure ;,5» 1 7 NJ $ i ^ 1^o \ I VM 'VD \j I S> * u^ u. I< I u i& Vb k, fc I I I□ KN V gk$5; s*'4 ■»c Vi Figure %xii 8 She operation of this circuit is aa sollaws. 22 the tabs ware removed# points 2 end 7 would be at 4-28 volts due to the resistance voltage dividers. When the tube is placed in the circuit, the positive grid voltages tend to cause both triodes to conduct. this Is an unstable condi¬ tion and# due to Slight'differences'in;the1triodea^ one triode will conduct heavily and due to the lowered plate voltage of the conducting triode and the resistive coupling of plate to grid# will cause the other triode grid to ba¬ cons negative# thus# beeping it cut off.
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