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INTERCONNECT-CENTRIC DESIGN for ADVANCED SOC and NOC Interconnect-Centric Design for Advanced Soc and Noc INTERCONNECT-CENTRIC DESIGN FOR ADVANCED SOC AND NOC Interconnect-Centric Design for Advanced SoC and NoC Edited by Jari Nurmi Tampere University of Technology, Finland Hannu Tenhunen Royal Institute of Technology, Sweden Jouni Isoaho University of Turku, Finland and Axel Jantsch Royal Institute of Technology, Sweden KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBook ISBN: 1-4020-7836-6 Print ISBN: 1-4020-7835-8 ©2005 Springer Science + Business Media, Inc. Print ©2004 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Springer's eBookstore at: http://ebooks.kluweronline.com and the Springer Global Website Online at: http://www.springeronline.com Contents Preface vii Part I PHYSICAL AND ELECTRICAL ISSUES 1 Communication-based Design for Network-on-Chip 3 Jan Rabaey 2 Wires as Interconnects 25 Li-Rong Zheng and Hannu Tenhunen 3 Global Interconnect Analysis 55 Tero Nurmi, Li-Rong Zheng, Jian Liu, Tapani Ahonen, Dinesh Pamunuwa, Jouni Isoaho and Hannu Tenhunen 4 Design Methodologies for On-Chip Inductive Interconnect 85 Magdy Ali El-Moursy and Eby Friedman 5 Clock Distribution for High-Performance Designs 125 Stefan Rusu Part II LOGICAL AND ARCHITECTURAL ISSUES 6 Error-Tolerant Interconnect Schemes 155 Heiko Zimmer and Axel Jantsch 7 Power Reduction Coding for Buses 177 Paul P. Sotiriadis 8 Bus Structures in Networks-on-Chip 207 Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna and Timo D. Hämäläinen vi 9 From Buses to Networks 231 David Sigüenza Tortosa and Jari Nurmi 10 Arbitration and Routing Schemes for On-Chip Packet Networks 253 Heikki Kariniemi and Jari Nurmi Part III DESIGN METHODOLOGY AND TOOLS 11 Self-Timed Approach for Noise Reduction in NoC 285 Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila and Jouni Isoaho 12 Formal Communication Modelling and Refinement 315 Juha Plosila, Tiberius Seceleanu and Kaisa Sere 13 Network Centric System-Level Model for Multiprocessor System- 341 on-Chip Simulation Jan Madsen, Shankar Mahadevan and Kashif Virk 14 Socket-based Design Techniques using Decoupled Interconnects 367 Drew Wingard Part IV APPLICATION CASES 15 Interconnect and Memory Organization in SOCs for Advanced Set- 399 Top Boxes and TV Kees Goossens, Om Prakash Gangwal, Jens Röver and A.P. Niranjan 16 A Brunch from the Coffee Table - Case Study in NOC Platform 425 Design Tapani Ahonen, Seppo Virtanen, Juha Kylliäinen, Dragos Truscan, Tuukka Kasanko, David Sigüenza-Tortosa, Tapio Ristimäki, Jani Paakkulainen, Tero Nurmi, Ilkka Saastamoinen, Hannu Isännäinen, Johan Lilius, Jari Nurmi and Jouni Isoaho Preface This book was mainly catalyzed by the SoC-Mobinet EU-project (IST 2000- 30094), where the editors have acted in 2001 - 2004 to create the European System-on-Chip infrastructure for joint research and education. The topic was seen very important especially after writing the previous book (Networks on Chip) where the higher-level on-chip communication issues were tackled. In this book, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design. We owe very much to the authors of this book, who represent the expertise on different aspects of interconnects, communication and system-on-chip and network-on-chip development worldwide. One major contributing project was also the Complain (Communication platform architectures for gigascale inte- gration) project in the Finnish-Swedish EXSITE research programme, mainly supported by TEKES, Vinnova, Nokia and Ericsson. We were happy to have such a good crew to assist us in creating the book for the interested readers in this field. We hope that you enjoy the book and, even more, wish that it will be of professional benefit to you! Tampere, Stockholm, Turku JARI NURMI January 2004 HANNU TENHUNEN JOUNI ISOAHO AXEL JANTSCH Chapter 1 SYSTEM-ON-CHIP-CHALLENGES IN THE DEEP-SUB-MICRON ERA A case for the network-on-a-Chip Jan M. Rabaey EECS Dept., University of California at Berkeley [email protected] Abstract: Continued scaling of semiconductor technology has created hopes for true sys- tem-on-a-chip integration; that is, the integration of a complete system on a single die of silicon. Yet, this prospect is seriously challenged by cost consider- ations. Solutions that maximize flexibility and re-use may be the only way to address the cost concerns, but necessitate offsetting the energy and perfor- mance penalty that comes with software solutions through an aggressive use of concurrency. A truly network-based solution is the only option to resolve the many issues that come with massive parallelism such as reliability, robustness, synchronization, and power management. This chapter presents an insight in some of the approaches and methodologies that are currently under develop- ment at the Gigascale Systems Research Center [GSRC]. Keywords: Platform-based Design, Network-on-a-Chip, Deep Sub-micron. 1 INTRODUCTION It is commonly believed today that from a pure technological perspective there are no reasons for Moore’s law to come to a screeching halt in the next decade. The continued scaling of the semiconductor technology creates the potential of true system-on-a-chip (SoC) integration; that is, the integration of a complete electronic system including all its periphery and its interfaces to the outside world on a single die. The reduction in size and cost that would come with this high level of integration opens to the door to truly ubiquitous electronics, and enables the realization of usage scenarios that were deemed to belong to the realm of science fiction not so long ago. An example of such is the “ambient intelligence” application [Boekhorst02, Rabaey03] that relies on wide-spread networks of embedded sensor, control, and actuation nodes, 3 4 embedded in the daily environment, to enhance a number of daily activities and/or our living environment. Yet, the enthusiastic embrace of the system-on-a-chip vision has cooled down considerably over the last one or two years, as the approach has run into some major roadblocks and hurdles. While these challenges were already speculated on in the mid 90’s, they have come into full bearing today. The combination of deep-submicron effects, manufacturing cost, and complexity have caused a major shift in the economics of IC design, and have marked the beginning of the end of the era of the Application Specific Integrated Circuit (ASIC). The importance of ASICs in shaping the semiconductor success story cannot be overemphasized. Very successful products were brought to market using integrated circuits that were specific to the application, and that were generated using a well understood design flow combining logic synthesis and automatic place and route. In response to these challenges, a new design methodology called “plat- form-based design” was proposed, promoting reuse at higher levels of granularity and relying heavily on flexibility and programmability to amortize the NRE costs of complex IC design over a number of designs [Keutzer00]. A summary of the main principles of platform-based design, as developed at the Gigascale Systems Research Center or GSRC, is given in Section III of this paper. For the approach to be ultimately successful in the realization of sys- tems-on-a-chip and to address the challenges raised by further scaling of the semiconductor technology, platform-based design has to come to grips with some major roadblocks which are enumerated in the Section II of the paper. One of the most important ones is the management of concurrency. While solutions that maximize flexibility and programmability may be the only way to address the cost concerns of design, they come with a major penalty in per- formance and energy efficiency. Offsetting this penalty is only possible through an aggressive use of concurrency. A truly network-based solution is the only option to resolve the many issues that come with massive parallelism such as reliability, robustness, synchronization, and power management. In Section IV of the paper, we explore the advantages of a “network-on-a-chip” (NoC) approach [Sgroi01] and discuss how it helps to address a number of the concerns that were raised in Section II. The paper will be concluded with some future perspectives. Challenges in the Deep-Submicron Era 5 10000 9000 8000 7000 6000 5000 ASSP 4000 ASSP IC Designs 3000 2000 ASIC 1000 ASIC 0 7 8 1 2 4 5 7 9 9 0 0 0 0 995 999 003 00 1 1996 19 19 1 2000 20 20 2 2 20 2006 20 Year Figure 2.1.Number of successful IC design starts per year (Source: Handel Jones, IBS - September 2002). ASIC and ASSP stand for Application-Specific Integrated Circuit and Application-Specific Standard Product, respectively. 2 CHALLENGING THE SOC PROSPECTS 2.1 The Demise of ASIC While the ASIC design methodology has very successful in bringing cheap electronics into a wide range of applications, economic considerations have dealt it a major blow. This is best illustrated in Figure 2.1., which plots the number of (successful) design starts over the last decade, extrapolating towards the future. The number of ASIC starts dropped by more than half in the period from 1995 to 2002. The reasons for this major decline are manifold: The NRE cost of IC manufacturing. The cost of mask making alone for sub-micron design is approaching $1 M for the 0.13 µm CMOS technology node, and it has been predicted to range between $2 M and $5 M in 2 to 3 years from now. (See Figure 2.2.).
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