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Formal Model-Based Development of Network-On-Chip Systems

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Formal Model-Based Development of Network-On-Chip Systems Formal Model-Based Development of Network-on-Chip Systems Leonidas Tsiopoulos Åbo Akademi University Department of Information Technologies Joukahaisenkatu 3-5 A, 20520 Turku, Finland 2010 Supervised by Professor Kaisa Sere Department of Information Technologies Åbo Akademi University Joukahaisenkatu 3-5 A, FI-20520 Turku Finland Reviewed by Professor Jüri Vain Department of Computer Science Tallinn University of Technology Raja 15, 12618 Tallinn Estonia Senior Researcher, Ph.D. Pasi Liljeberg Department of Information Technology University of Turku FI-20014, Turku Finland Opponent Professor Jüri Vain Department of Computer Science Tallinn University of Technology Raja 15, 12618 Tallinn Estonia ISBN 978-952-12-2438-6 Painosalama Oy – Turku, Finland 2010 Abstract Advances in technology allow us to have thousands of computational and storage modules communicating with each other on a single electronic chip. Well defined intercommunication schemes for such Systems–on–Chip are fundamental for handling the increasing complexity. So called bus–based and bus matrix–based communication frameworks for Systems–on–Chip face immense pressure of the increasing size and complexity, unable to offer the scalability required. The Network–on–Chip communication paradigm for Systems–on–Chip has been introduced to answer the given challenges offering very high communication bandwidth and network scalability through its generally regular structure. The communication between the modules of a System–on–Chip is generally categorised as synchronous or asynchronous, with a recent shift towards Globally Asynchronous Locally Synchronous Systems–on–Chip. In such systems each module can be synchronised to a private local clock but their intercommunication is established asynchronously, relying on request and acknowledgement communication handshakes. This arrangement results in lower power consumption eliminating the need for a global clock distribution network with its undesirably long interconnect wires. The application domain of Systems–on–Chip spans from home use electronics to large safety critical control and data transfer systems. One of the appropriate approaches for specifying reliable Systems–on–Chip, modelling the on–chip communication, as well as verifying their design is provided by formal methods. These methods are often accompanied by adequate tool support and are important for the development of complex Systems–on–Chip, from initial abstract specifications to implementations, because they help to avoid costly errors in the design and, thus, contribute to the reliability of such systems. This thesis presents a formal model–based development framework, based on the B Action Systems formalism, to facilitate the use of formal methods for correct-by-construction Systems–on–Chip design. The framework consists of tool assisted methods for specification, instantiation and automatic verification of asynchronous Network–on–Chip routing schemes, automatic model–based testing of implementations of these routing schemes and model–based mapping of applications to Network–on–Chip platforms. i ii Sammandrag Teknologiska framsteg möjliggör oss att ha tusentals beräknings- och lagringsmoduler som kommunicerar med varandra på en enda elektronisk krets. Väldefinierade interna kommunikationsscheman för sådana Sytems-on-Chip är fundamentala för hanteringen av den ökade komplexiteten. Så kallade bussbaserade och buss-matrisbaserade kommunikationsstrukturer för Systems- on-Chip möter enorm press av den ökande storleken och komplexiteten och är oförmögna att erbjuda den skalbarhet som krävs. Network-on-Chip kommunikationsparadigmen för Systems-on-Chip har introducerats som svar på de givna utmaningarna och erbjuder väldigt hög kommunikationsbandbredd och nätverksskalbarhet genom sin allmänt regelbundna struktur. Kommunikationen mellan modulerna i ett System-on-Chip är i allmänhet kategoriserat som synkront eller asynkront, med den senaste utvecklingen mot Globalt Asynkrona Lokalt Synkrona Systems-on-Chip. I sådana system kan varje modul vara synkroniserad med en privat lokal klocka men deras interkommunikation etableras asynkront. Denna förlitar sig på förfrågan- och bekräftelsehandskakningar för kommunikation. Detta arrangemang resulterar i lägre strömförbrukning samt eliminerar behovet för ett globalt klock- distributionsnätverk med dess oönskat långa sammankopplande ledningar. Tillämpningsområdet för Systems-on-Chip sträcker sig från hemelektronik till stora säkerhetskritiska kontroll- och dataöverföringssystem. Ett av de ändamålsenliga tillvägagångssätten att specificera tillförlitliga Systems-on-Chip, modellera kommunikationen i kretsen samt verifiera dess design, erbjuds av formella metoder. Dessa metoder åtföljs ofta av adekvata verktygsstöd och är viktiga för utvecklingen av komplexa Systems-on-Chip, från initiala abstrakta specifikationer till implementationer, eftersom de hjälper till att undvika kostsamma fel i designen och således bidrar till pålitligheten av sådana system. Denna avhandling presenterar ett formellt modellbaserat utvecklingsramverk, baserat på B Action Systems formalism, för att underlätta användandet av formella metoder för korrekt-genom-konstruktion uppbyggnad av Systems-on-Chip. Ramverket består av redskapsassisterade metoder för specifikation, instansering och automatisk verifiering av asynkrona Network-on- Chip ruttningsscheman, automatisk modellbaserad testning av implementationer av dessa ruttningsscheman och modellbaserad överföring av applikationer till Network-on-Chip plattformer. iii iv Acknowledgements It is a pleasure to be able to express my deepest gratitude to those who made this thesis possible. First of all, I would like to thank my supervisor Kaisa Sere for her guidance, support and belief on the importance of this work. I especially wish to thank Marina Waldén for introducing me to the formal methods world, for always having the time for discussions and for the continuous encouragement. I also wish to thank Juha Plosila for his never ending encouragement and for always having the time for discussions during critical periods of my doctoral studies. I also wish to thank Professor Jüri Vain from Tallinn University of Technology and Ph.D. Pasi Liljeberg from University of Turku for reviewing the manuscript of my thesis and for providing valuable comments and suggestions for improvement. I am especially grateful to Jüri Vain for also agreeing to be my opponent at the public defence of the thesis. I gratefully acknowledge the financial support that made my Ph.D. thesis possible. The work on the thesis has been funded by the Centre for Reliable Software Technology (CREST) and the Academy of Finland project DIJON (Distributed Jointly Operating Networks). I would also like to thank the administrative staff at the Department of Information Technologies for organising funding matters so that I never had to worry about them. I wish to express my gratitude towards colleagues, administrative personnel, and technical staff in the Department of Information Technologies for providing technical and administrative support and meaningful discussions during all these years. Especially I would like to thank colleagues from the department for creating an inspiring working environment. In particular, I wish to thank Pontus Boström for always having the time for discussions, especially on details of the B Method. I would like to thank Professors Ralph-Johan Back and Johan Lilius for valuable discussions on invariants and composition. I wish to thank Luigia Petre for the good cooperation during the last years of my studies. I also wish to thank Mats Neovius, Marta Pląska, Mikoáaj Olszewski, Qaisar Malik, Dubravka Ilic, Linas Laibinis, Patrick Sibelius, Ion Petre, Ivan Porres, Fredrik Degerlund, Anton Tarasyak, Johannes Eriksson and Torbjörn Lundkvist for the fruitful discussions on formal methods, life and everything in between them during these years. I would then like to thank all my co-authors Kaisa Sere, Marina Waldén, Juha Plosila, Manoranjan Satpathy and Luigia Petre. I have really learnt a lot from working with them. There is a large number of people outside the academic world, in Greece and in Finland, who I am forever thankful to for their support and encouragement. Thanks to my parents-in-law, Reijo and Eija Tiensuu, as well as to all my relatives and friends, who have supported me and given their love. My parents, Katerina and Thomas Tsiopoulos – thank you for all your love, support and for letting me choose my own paths in life. Your encouragement to leave and study abroad at a young age opened up new horizons in my life and v offered me the opportunity to finally achieve something special. I owe you more than words can ever describe. My brother, Vagelis Tsiopoulos – you have been a greater support than you might ever think and you have been always in my mind. Above all, I want to thank my wife Mervi whose endless love and support during all these years gave me the strength to make this work an actual thesis, and my son Tomas for bringing great happiness to my life. Turku, May 2010 Leonidas Tsiopoulos vi List of Original Publications This thesis is based on the following five publications. Paper 1 Leonidas Tsiopoulos, Kaisa Sere and Juha Plosila. Modeling Communication in Multi–Processor Systems–on–Chip using Modular Connectors. Special issue on Formal Modeling, Development, and Analysis of Communication Intensive Embedded Systems. International Journal of Embedded and Real-Time Communication Systems, April-June 2010, Vol.
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