2016 Esweek Program October 2-7, 2016 | Pittsburgh, Pa | Usa
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Network Processors the Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology
Network Processors The Morgan Kaufmann Series in Systems on Silicon Series Editor: Wayne Wolf, Georgia Institute of Technology The Designer’s Guide to VHDL, Second Edition Peter J. Ashenden The System Designer’s Guide to VHDL-AMS Peter J. Ashenden, Gregory D. Peterson, and Darrell A. Teegarden Modeling Embedded Systems and SoCs Axel Jantsch ASIC and FPGA Verification: A Guide to Component Modeling Richard Munden Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne Wolf Functional Verification Bruce Wile, John Goss, and Wolfgang Roesner Customizable and Configurable Embedded Processors Edited by Paolo Ienne and Rainer Leupers Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Configured Processors Steve Leibson ESL Design and Verification Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon System-on-Chip Test Architectures Edited by Laung-Terng Wang, Charles Stroud, and Nur Touba Verification Techniques for System-Level Design Masahiro Fujita, Indradeep Ghosh, and Mukul Prasad VHDL-2008: Just the New Stuff Peter J. Ashenden and Jim Lewis On-Chip Communication Architectures: System on Chip Interconnect Sudeep Pasricha and Nikil Dutt Embedded DSP Processor Design: Application Specific Instruction Set Processors Dake Liu Processor Description Languages: Applications and Methodologies Edited by Prabhat Mishra and Nikil Dutt Network Processors Architecture, Programming, and Implementation Ran Giladi Ben-Gurion University of the Negev and EZchip Technologies Ltd. -
About the Editors
About the Editors Prabhat Mishra is an assistant professor in the Department of Computer and Information Science and Engineering at the University of Florida. He received his B.E. from Jadavpur University, Kolkata, India, in 1994, M.Tech. from the Indian Insti¬ tute of Technology, Kharagpur, India, in 1996, and Ph.D. from the University of California, Irvine, in 2004—all in computer science. Prior to his current position, he spent several years in industry working in the areas of design and verification of microprocessors and embedded systems. His research interests are in the area ofVLSI CAD, functional verification, and design automation of embedded and nanosystems. He is a coauthor of the book Functional Verification of Programmable Embed¬ ded Architectures, Springer, 2005. He has published more than 40 research articles in premier journals and conferences. His research has been recognized by several awards including the NSF CAREERAward from National Science Foundation in 2008, CODES+ISSS Best Paper Award in 2003, and EDAA Outstanding Dissertation Award from the European DesignAutomationAssociation in 2005. He has also received the International Educator of the Year Award from the College of Engineering for his significant international research and teaching contributions. He currently serves as information director of ACM Transactions on Design Automation of Electronic Systems (TODAES), as a technical program committee member of various reputed conferences (DATE, CODES+ISSS, ISCAS, VLSI Design, I-SPAN, and EUC), and as a reviewer for many ACM/IEEE journals, conferences, and workshops. Dr. Mishra is a member ofACM and IEEE. Nikil Dutt is a chancellor's professor at the University of California, Irvine, with academic appointments in the CS and EECS departments. -
Underdesigned and Opportunistic Computing in Presence Of
8 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 1, JANUARY 2013 Underdesigned and Opportunistic Computing in Presence of Hardware Variability Puneet Gupta, Member, IEEE, Yuvraj Agarwal, Member, IEEE, Lara Dolecek, Member, IEEE, Nikil Dutt, Fellow, IEEE, Rajesh K. Gupta, Fellow, IEEE, Rakesh Kumar, Member, IEEE, Subhasish Mitra, Member, IEEE, Alexandru Nicolau, Member, IEEE, Tajana Simunic Rosing, Member, IEEE, Mani B. Srivastava, Fellow, IEEE, Steven Swanson, Member, IEEE, and Dennis Sylvester, Fellow, IEEE Abstract—Microelectronic circuits exhibit increasing variations print circuits and build systems at exponentially growing ca- in performance, power consumption, and reliability parameters pacities for the last three decades. After reaping the benefits of across the manufactured parts and across use of these parts the Moore’s law driven cost reductions, we are now beginning over time in the field. These variations have led to increasing use of overdesign and guardbands in design and test to ensure to experience dramatically deteriorating effects of material yield and reliability with respect to a rigid set of datasheet properties on (active and leakage) power, and die yields. So far, specifications. This paper explores the possibility of constructing the problem has been confined to the hardware manufacturers computing machines that purposely expose hardware variations who have responded with increasing guardbands applied to to various layers of the system stack including software. This microelectronic chip designs. However, the problem continues leads to the vision of underdesigned hardware that utilizes a software stack that opportunistically adapts to a sensed or mod- to worsen with critical dimensions shrinking to atomic scale. -
On-Chip Communication Architectures the Morgan Kaufmann Series in Systems on Silicon Series Editor,Wayne Wolf, Georgia Institute of Technology
On-Chip Communication Architectures The Morgan Kaufmann Series in Systems on Silicon Series Editor,Wayne Wolf, Georgia Institute of Technology The Designer ’s Guide to VHDL, Second System-on-Chip Test Architectures Edition Edited by Laung-Terng Wang, Charles Stroud, Peter J. Ashenden and Nur Touba The System Designer ’s Guide to Verifi cation Techniques for System- VHDL-AMS Level Design Peter J. Ashenden, Gregory D. Peterson, and Masahiro Fujita, Indradeep Ghosh, and Mukul Darrell A. Teegarden Prasad Modeling Embedded Systems and VHDL-2008: Just the New Stuff SoCs Peter J. Ashenden and Jim Lewis Axel Jantsch On-Chip Communication ASIC and FPGA Verifi cation: A Guide Architectures: System on Chip to Component Modeling Interconnect Richard Munden Sudeep Pasricha and Nikil Dutt Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne To Come Wolf Embedded DSP Processor Design: Functional Verifi cation Application Specifi c Instruction Set Bruce Wile, John Goss, and Wolfgang Roesner Processors Customizable and Confi gurable Dake Liu Embedded Processors Processor Description Languages Edited by Paolo Ienne and Rainer Leupers Prabhat Mishra Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Confi gured Processors Steve Leibson ESL Design and Verifi cation Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfi gurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon On-Chip Communication Architectures System on Chip Interconnect Sudeep Pasricha – Nikil Dutt AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Morgan Kaufmann is an imprint of Elsevier Senior Acquisitions Editor: Charles B. -
NIKIL DUTT Professor of CS and EECS University of California, Irvine
-NIKIL DUTT Professor of CS and EECS University of California, Irvine Office Address Home Address Department of Computer Science, 444 CS 5 McClintock Court University of California, Irvine, CA 92697-3425, USA Irvine, CA 92612-4046, USA Tel: +1 (949) 824-7219 Tel: +1 (949) 856-2473 Fax: +1 (949) 824-7219 Alternate Fax: +1 (949) 824-8019 Email: [email protected] URL: http://www.ics.uci.edu/~dutt PERSONAL DATA Date of Birth: November 9, 1958 Place of Birth: Hubli, India Citizenship: U.S.A. AREAS OF RESEARCH Computer systems design automation, embedded systems CAD, compilation techniques for novel architectures, high-level synthesis and high-level design languages, low-power design, distributed embedded systems. EDUCATION 1989: Ph.D. in Computer Science, University of Illinois at Urbana-Champaign. 1983: M.S. in Computer Science, The Pennsylvania State University, University Park, PA. 1981: B.E. (Honors) with Distinction in Mechanical Engineering, Birla Institute of Technical & Science, (BITS) Pilani, India. ACADEMIC APPOINTMENTS July 2003 – June 2004 : Vice-Chair, Division of Computer Systems, Department of Computer Science, U.C. Irvine. January 2003 - : Professor, Department of Computer Science and Department of Electrical Engineering and Computer Science, and Director, ACES Laboratory, Center for Embedded Computer Systems, U.C. Irvine July 1998 – December 2002: Professor, Department of Information and Computer Science and Department of Electrical and Computer Engineering and Director, ACES Laboratory, Center for Embedded Computer Systems, U.C. Irvine. July 1997 - June 1998, and July 1999 - June 2000: Associate Chair of Graduate Studies, Department of Information and Computer Science, U.C. Irvine. July 1994 - June 1998: Associate Professor, Department of Information and Computer Science and Department of Electrical and Computer Engineering, U.C. -
Memory Hierarchy Hardware-Software Co-Design in Embedded Systems
1 Memory Hierarchy Hardware-Software Co-design in Embedded Systems Zhiguo Ge1, H. B. Lim2, W. F. Wong1;2 1 Department of Computer Science, 2 Singapore-MIT Alliance, National University of Singapore Abstract— The memory hierarchy is the main bottleneck in All these diverse constraints on embedded systems including modern computer systems as the gap between the speed of the area, performance and power consumption result in enormous processor and the memory continues to grow larger. The situation issues and concerns during the design process. Among them, in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are memory hierarchy design is of great importance. The mem- precious resources in embedded systems. Moreover, embedded ory bottleneck in a modern computer system is a widely systems have multiple design objectives such as performance, known problem: the memory speed cannot keep up with the energy consumption, and area, etc. processor speed. This problem becomes even worse in an Customizing the memory hierarchy for specific applications is embedded system, where designers not only need to consider a very important way to take full advantage of limited resources the performance, but also the energy consumption. In an to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They embedded system, memory hierarchy takes a huge portion of separate the application optimization from the memory hierarchy both the chip area and power consumption. Thus, optimizing architecture design, which tend to result in local-optimal solu- the memory hierarchy to reduce hardware usage and energy tions. -
On-Chip Communication Architectures
On-Chip Communication Architectures pprelims-p373892.inddrelims-p373892.indd i 33/18/2008/18/2008 22:25:41:25:41 PPMM The Morgan Kaufmann Series in Systems on Silicon Series Editor , Wayne Wolf, Georgia Institute of Technology The Designer ’ s Guide to VHDL, Second System-on-Chip Test Architectures Edition Edited by Laung-Terng Wang, Charles Stroud, Peter J. Ashenden and Nur Touba The System Designer ’ s Guide to Verifi cation Techniques for System- VHDL-AMS Level Design Peter J. Ashenden, Gregory D. Peterson, and Masahiro Fujita, Indradeep Ghosh, and Mukul Darrell A. Teegarden Prasad Modeling Embedded Systems and VHDL-2008: Just the New Stuff SoCs Peter J. Ashenden and Jim Lewis Axel Jantsch On-Chip Communication ASIC and FPGA Verifi cation: A Guide Architectures: System on Chip to Component Modeling Interconnect Richard Munden Sudeep Pasricha and Nikil Dutt Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne To Come Wolf Embedded DSP Processor Design: Functional Verifi cation Application Specifi c Instruction Set Bruce Wile, John Goss, and Wolfgang Roesner Processors Dake Liu Customizable and Confi gurable Embedded Processors Processor Description Languages Edited by Paolo Ienne and Rainer Leupers Prabhat Mishra Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Confi gured Processors Steve Leibson ESL Design and Verifi cation Grant Martin, Andrew Piziali, and Brian Bailey