On-Chip Communication Architectures the Morgan Kaufmann Series in Systems on Silicon Series Editor,Wayne Wolf, Georgia Institute of Technology

On-Chip Communication Architectures The Morgan Kaufmann Series in Systems on Silicon Series Editor,Wayne Wolf, Georgia Institute of Technology

The Designer ’s Guide to VHDL, Second System-on-Chip Test Architectures Edition Edited by Laung-Terng Wang, Charles Stroud, Peter J. Ashenden and Nur Touba The System Designer ’s Guide to Verifi cation Techniques for System- VHDL-AMS Level Design Peter J. Ashenden, Gregory D. Peterson, and Masahiro Fujita, Indradeep Ghosh, and Mukul Darrell A. Teegarden Prasad Modeling Embedded Systems and VHDL-2008: Just the New Stuff SoCs Peter J. Ashenden and Jim Lewis Axel Jantsch On-Chip Communication ASIC and FPGA Verifi cation: A Guide Architectures: System on Chip to Component Modeling Interconnect Richard Munden Sudeep Pasricha and Nikil Dutt Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne To Come Wolf Embedded DSP Processor Design: Functional Verifi cation Application Specifi c Instruction Set Bruce Wile, John Goss, and Wolfgang Roesner Processors Customizable and Confi gurable Dake Liu Embedded Processors Processor Description Languages Edited by Paolo Ienne and Rainer Leupers Prabhat Mishra Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Confi gured Processors Steve Leibson ESL Design and Verifi cation Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfi gurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon On-Chip Communication Architectures System on Chip Interconnect

Sudeep Pasricha – Nikil Dutt

AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO

Morgan Kaufmann is an imprint of Elsevier Senior Acquisitions Editor: Charles B. Glaser Publishing Services Manager: George Morrison Project Manager: Mónica González de Mendoza Assistant Editor: Greg Chalson Cover Design: Dennis Schaefer Morgan Kaufmann Publishers is an imprint of Elsevier. 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA This book is printed on acid-free paper. © 2008 Elsevier, Inc. All rights reserved. Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means – electronic, mechanical, photocopying, scanning, or otherwise – without prior written permission of the publisher. Permissions may be sought directly from Elsevier’s Science & Technology Rights Department in Oxford, UK: phone: (44) 1865 843830, fax: (44) 1865 853333, E-mail: [email protected]. You may also complete your request online via the Elsevier homepage (http://elsevier.com ), by selecting“Support & Contact ” then “Copyright and Permission ” and then “Obtaining Permissions. ”

Library of Congress Cataloging-in-Publication Data Pasricha, Sudeep.. On-chip communication architectures: system on chip interconnect/Sudeep Pasricha, Nikil Dutt. p. cm. Includes bibliographical references and index. ISBN-13: 978-0-12-373892-9 (hardback: alk. paper) 1. Systems on a chip. 2. Microcomputers—Buses 3. Computer architecture. 4. Interconnects (Integrated circuit technology) I. Dutt, Nikil. II. Title. TK7895.E42P4 2008 621.3815—dc22 2008004691 ISBN: 978-0-12-373892-9 For information on all Morgan Kaufmann publications, visit our Web site at www.mkp.com or www.books.elsevier.com

08 09 10 11 12 13 10 9 8 7 6 5 4 3 2 1 Printed in the United States of America Contents

Preface ix About the Authors xiii Acknowledgments xv List of Contributors xvii

CHAPTER 1 Introduction ...... 1 1.1 Trends in System-On-Chip Design ...... 1 1.2 Coping with Soc Design Complexity ...... 3 1.3 ESL Design Flow ...... 4 1.4 On-Chip Communication Architectures: A Quick Look ...... 6 1.5 Book Outline ...... 12

CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures ...... 17 2.1 Terminology ...... 18 2.2 Characteristics of Bus-Based Communication Architectures ...... 19 2.3 Data Transfer Modes ...... 28 2.4 Bus Topology Types ...... 33 2.5 Physical Implementation of Bus Wires ...... 37 2.6 Discussion: Buses in the DSM Era ...... 38 2.7 Summary ...... 39

CHAPTER 3 On-Chip Communication Architecture Standards ...... 43 3.1 Standard On-Chip Bus-Based Communication Architectures ...... 44 3.2 Socket-Based On-Chip Bus Interface Standards ...... 88 3.3 Discussion: Off-Chip Bus Architecture Standards ...... 96 3.4 Summary ...... 97

CHAPTER 4 Models for Performance Exploration ...... 101 4.1 Static Performance Estimation Models ...... 102 4.2 Dynamic (Simulation-Based) Performance Estimation Models ...... 111 4.3 Hybrid Communication Architecture Performance Estimation Approaches ...... 132 4.4 Summary ...... 138

CHAPTER 5 Models for Power and Thermal Estimation ...... 143 5.1 Bus Wire Power Models ...... 145 5.2 Comprehensive Bus Architecture Power Models ...... 153 5.3 Bus Wire Thermal Models ...... 167 vi Contents

5.4 Discussion: PVT Variation-Aware Power Estimation ...... 174 5.5 Summary ...... 179

CHAPTER 6 Synthesis of On-Chip Communication Architectures ...... 185 6.1 Bus Topology Synthesis ...... 187 6.2 Bus Protocol Parameter Synthesis ...... 196 6.3 Bus Topology and Protocol Parameter Synthesis ...... 205 6.4 Physical Implementation Aware Synthesis ...... 216 6.5 Memory–Communication Architecture Co-synthesis ...... 230 6.6 Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures ...... 240 6.7 Summary ...... 243

CHAPTER 7 Encoding Techniques for On-Chip Communication Architectures ...... 253 7.1 Techniques for Power Reduction ...... 255 7.2 Techniques for Reducing Capacitive Crosstalk Delay ...... 278 7.3 Techniques for Reducing Power and Capacitive Crosstalk Effects ...... 282 7.4 Techniques for Reducing Inductive Crosstalk Effects ...... 284 7.5 Techniques for Fault Tolerance and Reliability ...... 287 7.6 Summary ...... 292

CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design ...... 301 8.1 Split Bus Architectures ...... 301 8.2 Serial Bus Architectures ...... 309 8.3 CDMA-Based Bus Architectures ...... 310 8.4 Asynchronous Bus Architectures ...... 313 8.5 Dynamically Reconﬁ gurable Bus Architectures ...... 318 8.6 Summary ...... 336

CHAPTER 9 On-Chip Communication Architecture Reﬁ nement and Interface Synthesis...... 341 9.1 On-Chip Communication Architecture Reﬁ nement ...... 343 9.2 Interface Synthesis ...... 346 9.3 Discussion: Interface Synthesis ...... 361 9.4 Summary ...... 361

CHAPTER 10 Verifi cation and Security Issues in On-Chip Communication Architecture Design ...... 367 10.1 Verifi cation of On-Chip Communication Protocols ...... 369 10.2 Compliance Verifi cation for IP Block Integration ...... 376 10.3 Basic Concepts of SoC Security ...... 388 Contents vii

10.4 Security Support in Standard Bus Protocols ...... 391 10.5 Communication Architecture Enhancements for Improving SoC Security ...... 391 10.6 Summary ...... 395

CHAPTER 11 Physical Design Trends for Interconnects ...... 403 11.1 DSM Interconnect Design ...... 405 11.2 Low Power, High Speed Circuit Design Techniques ...... 408 11.3 Global Power Distribution Networks ...... 417 11.4 Clock Distribution Networks ...... 421 11.5 3-D Interconnects ...... 427 11.6 Summary and Concluding Remarks ...... 429

CHAPTER 12 Networks-On-Chip ...... 439 12.1 Network Topology ...... 443 12.2 Switching Strategies ...... 448 12.3 Routing Algorithms ...... 451 12.4 Flow Control ...... 454 12.5 Clocking Schemes ...... 458 12.6 Quality of Service ...... 459 12.7 NoC Architectures ...... 459 12.8 NoC Status and Open Problems ...... 464 12.9 Summary ...... 466

CHAPTER 13 Emerging On-Chip Interconnect Technologies ...... 473 13.1 Optical Interconnects ...... 474 13.2 RF/Wireless Interconnects ...... 483 13.3 CNT Interconnects ...... 490 13.4 Summary ...... 501

Index...... 509 This page intentionally left blank Preface

Digital electronic devices such as mobile phones, video game consoles, and network routers typically contain one or more electronic (integrated circuit) chips that are composed of several components such as processors, dedicated hardware engines and memory, and are referred to as system-on-chip (SoC). These SoC designs are rapidly becoming more complex, in order to handle the ever increas- ing complexity of applications, fueled by the onset of the digital convergence era. Continuing improvements in process technology have allowed the integration of components previously connected at the board level onto a single chip, which further adds to the complexity. The components on a SoC are connected together by an on-chip communication architecture backbone that supports all inter-component data communication, both within the chip as well as with external devices (e.g., external fl ash drives). These SoC communication architectures have been shown to have a sig- nifi cant impact on the performance, power consumption, cost, and design time of SoCs. Indeed, modern SoC design processes are increasingly becoming communication-centric, since reusable components (e.g., processors, memories, etc.), as well as custom hardware blocks and interfaces, need to be connected via a communication architecture fabric, with the goal of meeting various design con- straints such as cost, performance, power/energy, and reliability. The move toward higher levels of abstraction have led to the notion of electronic system level (ESL) design, where system architects and application designers are able to capture system functionality and map desired system functionality onto a range of software and hardware confi gurations that exhibit differing performance, cost, power/ energy, reliability, and other design metrics. A key step within an ESL design fl ow is the effi cient use of an on-chip communication architecture fabric. Consequently, there has been a large body of work on modeling abstractions, communication protocols and standards, as well as active research on communication architecture design and exploration. This book aims to serve as a comprehensive reference on the concepts, research, and trends in on-chip communication architecture design. We describe the basic concepts and attributes of on-chip communication architectures, to familiarize the reader with intricate details of on-chip communication architecture design and the problems facing designers. This is followed by an expansive sur- vey of research efforts in this area, spanning the past several years, and addressing some of the major issues in on-chip communication architecture design. Finally, we present some of the trends that will shape future research in the area of on- chip communication architecture design. ix x Preface

AUDIENCE FOR THIS BOOK This book is designed for a number of different audiences. Graduate and undergraduate students, as well as design engineers working in the area of SoC design should fi nd this book useful as an introduction to the fi eld of on-chip communication architectures. Faculty members can use this book as a textbook for a graduate or senior undergraduate course on ESL and communication-centric design. Furthermore, chip and hardware engineers who currently design at the logic or register-transfer level will fi nd this book useful to understand the transition to higher levels of abstraction (ESL) and get insights into the key principles of communication-centric design. Finally, the book should serve as a useful reference for managers, technologists, and industry analysts who need to track trends in SoC design, ESL methodologies, and communication-centric SoC design fl ows.

HOW TO USE THIS BOOK Although each chapter in this book is self-contained (with an extensive set of references at the end of each chapter), the fi rst three chapters of this book contain the introductory material that set the stage for the design methodology of communication-centric design (Chapter 1), basic concepts of on-chip communication (Chapter 2), and contemporary/commonly used on-chip bus communication standards (Chapter 3). We recommend that these three chapters be covered for all audiences before embarking on different trajectories, based on the audience and goals. In the remainder of this section, we present two possible fl ows for covering the material in the book. Figure 1 shows the suggested chapter trajectory for use of this book in a one semester/quarter graduate or upper-division undergraduate course. The fi rst big box (Chapters 1–6 and 9) covers a snapshot of the entire communication architecture modeling, analysis, and synthesis process. After the fi rst three introductory chapters, Chapters 4 and 5 introduce models that allow evaluation of performance and power/energy. Chapters 6 and 9 cover on-chip communication architecture synthesis and interface synthesis, respectively. Each of these chapters starts with an introductory (or generic) fl ow, and then surveys recent research efforts in a comprehensive manner. Next, the instructor or student has a number of choices for traversing topics, based on the focus/interest of the course and the amount of time. In conjunction with a traditional CAD course that covers physical design, logic, and register-transfer level design, the next logical step would be to cover Chapter 11. On the other hand, a course focused on synthesis and methodology issues may benefi t from the chapter on encoding techniques (Chapter 7) as well as verifi cation and security (Chapter 10). Finally, the topics of emerging architectures will round out any course by covering material on custom architectures (Chapter 8), Networks-on-Chip (Chapter 12) and emerging technologies (Chapter 13). Figure 2 outlines a suggested fl ow for design engineers, practitioners, managers, technologists, industry analysts, etc. We recommend that you begin with the fi rst three chapters to set the stage with basic terminology and concepts, before Preface xi

1. SoC overview 4. Performance Models 2. Basic Concepts 1 Quarter / 1 Semester 5. Power/Thermal Graduate / Upper Division 3. Standards Models Undergraduate (AMBA) 6. Synthesis Methodologies

9. Refinement/ Interface Synthesis

Encoding Physical design issues 7. Encoding 11. Physical Design Techniques Trends

Emerging architectures Verification and security 12. Networks on 10. Verification/ Chips 8. Custom Security Architectures 13. Emerging Technologies

FIGURE 1 Suggested flow for a graduate/undergraduate course

1. SoC Overview

2. Basic Concepts

3. Standards

Modeling Verification and Security 4. Performance Synthesis Techniques Models 10. Verification/ 6. Synthesis Security Methodologies 5. Power/Thermal Models 9. Refinement/ Interface Synthesis

Future Trends 12. Networks on Optimization Chips 7. Encoding Techniques 11. Physical Design Trends 13. Emerging 8. Custom Technologies Architectures

FIGURE 2 Suggested flow for a practitioners, designers, managers, technologists, etc. xii Preface

embarking onto more advanced concepts. Since the goals and needs of the reader may be quite diverse for this audience, we have grouped the relevant chapters into high level topics that can be traversed in any order: modeling (Chapters 4 and 5); synthesis techniques (Chapters 6 and 9); optimization (Chapters 7 and 8); veriﬁ cation and security (Chapter 10); and future trends (Chapters 11–13). Finally, the material in this book is being used for a UC Irvine Spring Quarter 2008 graduate course (CS 295) titled On-Chip Communicatio