Hardware/Software Co-Design: VHDL and Ada 95 Code Migration And

Hardware/Software Co-design: VHDL and Ada 95 Code Migration and Integrated Analysis Mike Mills and Greg Peterson Air Force Research Lab Information Technology Division Wright-Patterson AFB OH (937)-255-6653 x3591

1. ABSTRACT 2. INTRODUCTION

Optimizing the design of complex The electronics design industry enjoys dramatic weapons systems constitutes an improvements in circuit capabilities, with the important task in efficiently number of transistors on a chip doubling every eighteen months as noted by Moore's Law [1]. developing and deploying effective This explosive growth represents tremendous complex weapons systems. Often potential for military and commercial electronics architectural tradeoffs between systems and components, while at the same time presenting designers with the seemingly hardware and software insurmountable task of exploiting this growth implementation must be performed effectively and economically. As a corollary to early in the design cycle, resulting in Moore's Law, the electronic systems design process demands an exponential increase in potentially inefficient systems or design productivity to keep pace with subsystems. As technologies and improvements in device density and speed. costs in hardware and software When developing electronic systems, the implementation change over time, designer typically develops models of the the best partitioning of system hardware components by starting with abstract behavioral VHSIC Hardware Description functionality into hardware and Language (VHDL) models of functionality and software components will also refining these models into register transfer level change. Currently, recasting a and eventually gate level models. Software design using high level languages such as Ada component from hardware to software often follows a similar development path in (or vice-versa) is a difficult and error- parallel to the hardware development. This top- prone activity. This paper explores a down design methodology is appealing due to its effectiveness in handling complexity, but new approach to ease the hardware often results in sub-optimal implementations due software co-design and repartitioning to the need to partition functionality into hardware and software too early in the design activities by providing a mechanism cycle. In addition, the hardware and software to exchange software written in Ada domains use different representations (languages) 95 with behavioral VHDL. which are challenging to make inter-operate. Bringing the hardware and software components into a consistent framework could help provide an effective means of co-executing hardware models with software code.

Design methodologies and tools must account for these issues to ensure correct, efficient implementations of designs. Simply exploiting these improvements in designing and manufacturing electronics hardware solves only

1 half the problem: we need efficient and reliable By exploiting state of the art software methods to develop and maintain both the engineering tools and formats, a bridge between hardware and software. With advances in hardware models and software code can be reconfigurable computing, the delineation constructed. This bridge has great potential for between these two domains continues to blur. enhancing the systems design effort by Effective language support, tools, and supporting relatively effortless migration between methodologies addressing these issues will help the hardware and software domains in addition to enable the future deployment of sophisticated enabling an integrated analysis tool suite. systems and the affordable, effective maintenance of existing weapons systems. In response to a perceived need for additional support of abstract system design and As a result of research projects funded by the Air specification, a system-level design language Force Research Lab and DARPA and commercial development effort sponsored by the Industry tool development projects, an emerging, Council continues to investigate needs in this extensible intermediate format for VHDL area in preparation for extensions to VHDL or the promises high performance and space efficiency possible development a new system description for analyzed (compiled) VHDL models. The language [3]. Advanced Intermediate Representation with Extensibility (AIRE) structures VHDL models in Significant related research is in progress which abstract syntax trees with additional information could be exploited in developing the system provided as the models are analyzed, elaborated, level design language. There is a wealth of work and simulated. Standardization of AIRE for going on with VHDL and hardware design, VHDL, VHDL-AMS, and Verilog support synthesis, and test. The same can be said of continues, and a number of AIRE-compliant work for software engineering with Ada and with implementations near completion. process improvements. Complex systems include both hardware and software components. Abstract syntax trees serve a common role as a Significant recent attention focuses on how to standard representation of software code during specify, design, and verify the hardware and compilation. In order to develop a common software together. Current standardization efforts AST representation for multiple software related to codesign focus on co-simulation languages such as Ada, JOVIAL, and C++, the approaches in the short term [4] and general Arcadia group developed IRIS. By using IRIS codesign/systems design support in the long as a common foundation, a number of software term. The goal of this effort is to bring together engineering projects have been able to exploit a research results from both communities to common front end and support multiple improve systems design capabilities. languages. One Air Force Research Lab software maintenance project exploits this approach to Long-term software engineering experience port older JOVIAL code into Ada 95 [2]. proves Ada to be effective for cost-effectively managing large program development and This paper addresses efforts to provide an maintenance efforts, particularly when compared interface between VHDL models and Ada to languages such as C [5,6]. Ada is software via a common abstract syntax tree by syntactically similar to VHDL, which makes it exploiting AIRE and IRIS. We discuss this attractive as a basis for the software domain. interface, language construct limitations, and the Despite the end of the DoD Ada mandate, Ada potential for solidifying the hardware/software remains a powerful language often chosen for interface. A number of very interesting weapons systems development [7]. Ada applications exist for such an interface between provides strong typing, encapsulation via the VHDL hardware models and software written in package mechanism, and supports generics languages such as Ada. Models in hardware can among other features. Ada 95’s object oriented be ported to software for implementation, and programming, real time, and programming in the vice-versa. In addition, some of the Arcadia large features makes Ada highly competitive. software engineering tools built upon IRIS Yet, opposition to Ada has hindered general provide analysis capabilities that could prove adoption by industry. VHDL enjoys significant quite useful for VHDL. The potential for greatly use in the design automation industry. improving the state of the art in hardware modeling via these tools is discussed. 3. OVERVIEW OF VHDL

2 VHDL provides the best current capability for supporting the development and ongoing The VHDL-AMS (Analog Mixed Signal) maintenance of large, complex digital systems. extensions to VHDL provide a capability for Developed by the DoD in the 1980s to support modeling analog and mixed signal designs. The the documentation of electronic systems, VHDL VHDL-AMS standard provides a single language derives much of its syntax and semantics from in which both digital and analog circuitry effects Ada. A major difference in the languages comes can be modeled, thus giving us an integrated from the notion of concurrent processes that tool for considering analog effects for advanced permeates VHDL. Because the language is digital design. intended to model hardware components which are "always executing," VHDL is a highly 4. OVERVIEW OF AIRE concurrent language built upon a simulation cycle-based timing model. Interactions between The Advanced Intermediate Representation with VHDL processes occur over signals and include Extensibility/Common Environment (AIRE/CE) data and temporal aspects. VHDL is a Turing is currently being developed by a number of complete language and capable of representing electronic design automation tool vendors and very low level device models on up to system users and is being standardized through the models by employing appropriate abstraction. Electronic Industries Association and the IEC. Data encapsulation is part of VHDL. Although Before the design and implementation of developed initially for documentation and AIRE/CE, integration of tool components from simulation, synthesis tools now transform more distinct applications to form an entire system abstract VHDL models into detailed gate-level was severely limited by proprietary, inflexible, implementations, resulting in a dramatic low-functionality and low-performance interfaces. productivity improvement. The cost and time required to integrate best-of- breed tool components generally lead to Several past and current research and pragmatic compromises intended to reduce cost standardization efforts focus on ways to extend rather than increase application capability. the capabilities of VHDL to better support Rising interest in the exchange of hardware and systems design and, in particular, to provide an system components, often referred to as design integrated mechanism for modeling, simulation, re-use or intellectual property commerce, and synthesis of software components. Although emphasizes the value of being able to transport VHDL has some characteristics which design components from one usage to another. differentiate it from software programming languages, system and hardware design tools and AIRE/CE solves both the tool component methodologies can potentially benefit by integration and information exchange problems. exploiting practices in software engineering. One AIRE/CE supports information exchange both effort to transition software engineering standard within a single address space and via the host practices into hardware description languages is computer file system. The in-memory the work focused on creating object-oriented communication protocol, the Internal VHDL extensions [8,9]. In essence, the Intermediate Representation (IIR) facilitates proposal extends VHDL with object orientation integration of the most suitable tool components using similar mechanisms to those of Ada 95. within a single operating system process. The File Intermediate Representation (FIR) provides Other extensions and enhancements to VHDL for the integration of self-contained, AIRE/CE- include support for formal methods. VSPEC compliant tool components and the exchange of [10] is a Larch interface language for VHDL that partially compiled designs (intellectual property). allows a designer to specify non-functional performance constraints. VSPEC extends to Efforts to build previous generations of VHDL VHDL to allow a designer to declaratively tools on a standard intermediate format did not describe the data transformation a digital system converge or achieve the support of multiple should perform and performance constraints the vendors due to competing commercial concerns system must meet. The designer axiomatically and technical problems. Earlier approaches no specifies the transformation by defining predicates longer meet the requirements of today’s advanced over entity ports and system state describing tool developers. input precondition and output postconditions. A constraints section allows the user to specify AIRE’s in-memory intermediate representation, timing, power, heat, clock speed and layout area the IIR, is defined in terms of a class hierarchy. constraints.

3 An IIR class forms the top level. Classes One or more extension classes may be introduced derived from IIR include: just before any derived class in order for · IIR_DesignFile, applications to add data or functionality to the · IIR_Literal, predefined IIR specification. In order to preserve · IIR_Tuple, binary tool compatibility, data may only be · IIR_TypeDefinition, added within the extension classes immediately · IIR_Declaration, preceding terminal classes from which objects · IIR_Name, may be created. · IIR_Expression, · IIR_SequentialStatement, While the current version of the file format is · IIR_ConcurrentStatement, believed to represent the full VHDL language, · IIR_SimultaneousStatement, and the class hierarchy is not intended to map one to · IIR_List. one with a language reference manual. Source code analysis and transformations readily map Information associated with classes is accessible arbitrary source code into a canonical subset of via class methods. Basic data types, introduced VHDL in order to facilitate optimization or other in the previous section, appear within the type uses. signature of these methods, however the IIR does not define the organization of data within an IIR 5. OVERVIEW OF ARCADIA/IRIS object (enabling many cost/performance tradeoffs). IRIS [11] is a language-independent abstract syntax tree representation of software programs. Design file classes represent the information This representation is produced when a software contained in a single HDL source file. Such engineer uses an analyzer (compiler) to transform information includes a list of comments, a list of the input high order language source code into design units / modules present in the design file, the IRIS abstract syntax tree representation. The and information required for tools to cross- IRIS AST can then be transformed into any of a reference from the IIR representation back to the number of other internal representations, designer’s original files. including control flow graphs, dataflow graphs, reachability graphs, and dependence graphs. Literal classes represent design elements such as text literals (strings), identifiers, integer literals, The Arcadia language processing tools can floating point literals, bit vector literals, and construct, manipulate, store, and retrieve IRIS enumeration vector literals. graphs. Analysis can be performed on the control flow graph and the rendezvous call graph Tuple classes represent collections of design to analyze concurrent programs. The language information with a small, fixed number of processing toolset is built upon the PLEIADES elements. Examples include associations object management system and provides a between formals and actuals, the value and delay number of application program interfaces to of a waveform element, or the association of a support analysis tasks. choice and action within a case statement. Some of the Arcadia tools built upon IRIS Type definition classes represent a range of data include the control flow graph (CFG) toolset, the values and associated operators. Reflecting a task interaction graph (TIG) toolset, the TIG- broad view of language design, types include not based Petri Net toolset, and the rendezvous call only “traditional” types such as integers and graph toolset. arrays, but also signatures, attribute types, and group types. Interfaces into the IRIS abstract syntax tree representations exist or are under development for Declaration classes generally represent named Ada, JOVIAL, and C++. Employing the instances of types. Examples include VHDL’s mapping into IRIS combined with a mapping variable declarations, constants, and signal back into Ada, the Advanced Avionics interface items. Verificaion and Validation program [2] provides a capability to transform legacy JOVIAL code Name classes generally refer to implicit or into Ada. explicit declarations. Examples include VHDL’s selected names and attributes. 6. MAPPING VHDL TO Ada

4 In order to show how VHDL could be mapped to B&F representation of a VHDL signal Ada, examples of Ada source code follow assignment: selected VHDL B&F descriptions. Signals are key objects in the VHDL language and provide a Signal_assignment ::= challenge for Ada to model. Therefore, an [label:] target <= [delay_mechanism] example shows how signal declarations and waveform; signal assignments could be represented by Ada. In order to model VHDL signal attributes, an Suggestions for transforming to Ada code: Ada record, called a signal description record, keeps track of signal status. Separate records target - is the name of the Ada variable could represent waveform elements making up representing the signal. each signal. delay_mechanism - is implemented with a B&F representation of a VHDL signal function call that adds a delay value to the declaration: variable representing time when the signal is activated. This is represented as a signal VHDL signal_declaration ::= attribute by changing the corresponding value in signal identifier_list subtype_indication the signal description record implemented by [signal_kind] [:= expression] Ada. subtype indication ::= waveform - is implemented with a series of [resolution_function_name] type_mark subroutine calls to waveform_element to set the [constant] activation time, period of persistance, and signal value (implemented by an Ada variable). signal kind ::= register | bus waveform_element (t1, value, period); register means that the target signal is not assigned a changed value until the next clock These values are stored in the signal data type signal (or simulated cycle time occures). representing the signal. When the model is Therefore, the time (or duration) corresponding executed, the signal description record triggers to the signal value should be incremented. the signal behavior during the Ada model simulation. bus means that the target signal remains unchanged if there are no driver signals present More B&F description of a signal: on the bus (or they all have ‘0’ value). target ::= name | aggregate Suggestions for transforming to Ada code: aggregate ::= [choices => ] expression resolution_function_name could correspond to a delay_mechanism ::= transport | [reject resolution function written in Ada-95 but would time_expression] inertial have to be hand coded for each resolution function. delay_mechanism - is implemented by a function call which adds a delay to the total signal. This type_mark can be directly translated to an delay can be a transport delay which adds a clock equivalent Ada type except for floating, physical, delay to the signal activation time stored in the or file types which have no corresponding Ada signal description record. equivalents. Physical type could be handled by converting units such as 80 ms to 80 * ms. Transport means delay of the first waveform is a Femto-seconds would have to be converted to transport delay from hardware devices with 0.001 * ns. Ada types common to VHDL are infinite frequency response. access, enumeration, integer, array, and record Inertial means there is a built in delay (from signal_kind - is implemented by a function to set switching circuits). signal kind in the data structure representing the signal. Reject means that a pulse shorter than the switching time or whose duration is shorter than expression - is an initial Ada value the rejection limit will not be transmitted.

5 B&F for two kinds of signal assignment: unaffected is only for concurrent signals (or agregate of guarded signals) concurrent_signal_assignment ::= [label:] [postponed] Evaluation of waveform elements produces conditional_signal_assignment transactions that determine future behavior of | [label:] [postponed] drivers for a target. The result is a sequence of selected_signal_assignment transactions in ascending order with respect to time. postponed - is implemented by a subroutine call which adds a delay triggered by an event. waveform_element ::= value_expression [after time_expression] | null [after time_expression] conditional_signal_assignment ::= target <= options {waveform when conition interface_signal_declaration ::= else} waveform [when condition]; [signal] identifier_list : [mode] subtype_indication [bus] [:= static_expression]; Ada implementation can use an “if” or a “case” statement: interface_signal_declaration - is used in signal parameters of function or procedure calls or ports if condition_1 then waveform_1; (or generics) of hardware structures called elseif condition_2 entities. then waveform_2; else waveform_3; mode ::= in | out | inout | buffer | linkage end if; mode - has the same in, out, and in out as Ada. case condition is Modes. Buffer and linkage are handled in Ada when condition_1 => by setting these attributes in the signal waveform_1; description record. when condition_2 => waveform_2; when others => An Ada-95 representation of a waveform waveform_3; element could look like the following: end case; For digital signals (which encompasses all of Selected_signal_assignment ::= VHDL signals), the only values a waveform at a with expression select target <= options given instant of time are either true or false (or {waveform when choices,} bit ‘1’ or ‘0’). Therefore, the Ada waveform when choices; implementation for modeling a VHDL waveform could include a set of boolean drivers opearated Ada implementation is similar to the above: on by logic or’s. case choices … Ada_waveform ::= driver (expression_1, time_1) end case; or driver (expression_2,time_2) or … or driver (expression_n, time_n); options ::= [guarded] [delay_mechanism] function driver (expression, time) return value Ada implementation could use a protected type is with a guard, or just represent the guard as a begin signal attribute in the signal description record. … end driver; waveform ::= waveform_element {, waveform_element} | unaffected The above drivers correspond to functions that are active for given simulated time periods. Each waveform_element represents a signal The start and stop time (or time duration) that a driver. A driver assigns a value to the target at a driver is active could be passed as a parameter in specified time. When a driver is turned off, it a function. has no contribution to the target value.

6 An Ada 95 implementation could treat time as a global variable and increment it periodically at package System is -- (includes the following): every tick. pragma Preelaborate(System); Tick : constant := implementation-defined; Time, T : variable; -- (real time interval that Calendar.clock R := S when T >= Current_Time + remains constant.) Tick; -- or something similar package Ada.Calendar is – (includes the Signals declared within a parameter list exist in following): the form of an interface signal declaration: type Time is private; function Clock return time; Representing VHDL Signal Attributes in function Seconds (Date : Time) return Ada: Day_Duration;

VHDL signals could be represented in Ada using VHDL model execution includes a kernel process record types that contain the signal value (in that accomplishes the following: Boolean) at the represented duration of time and 1. Causes prapagation of signal values, the signal attributes (which are mostly Boolean 2. Updates values of implicit signals and could be implemented in bit, thus (S’stable(T)), minimizing storage requirements). 3. Detects events, and Some Ada types to represent VHDL language 4. Causes processes to execute in response to defined types: events. type Boolean is (False, True); The Kernel process contains a: type Bit_vector is array (Integer range <>) of 1. Variable representing current signal value Boolean; and updates variable based on source values. -- VHDL mode as an Ada enumeration type: 2. Variable representing current value of any type mode is (in, out, inout, buffer, linkage); implicitly declared guard signal (resulting from a guard expression of a block Signal description block implemented as an statement. Ada record to store VHDL signal attributes plus 3. Driver and variable to represent the current any other values to help model VHDL in Ada: value of any signal (S’Stable (T) and Time T, S’Quiet (T), and S’Transaction). type signal is record The VHDL Simulation Cycle: value: Boolean; -- for digital VHDL (integer for Analog VHDL) Model execution: start_time: Time; end_time: Time; Initialization phase: Tc = 0; -- current -- attributes: (8 Boolean, 1 Bit, 2 Time time types) Compute driving and effective value delayed, stable, quiet, transaction, (or current value of signal). event, active, last_value, driving : Boolean; Execute process statements repetitively: Last_event : Time; Simulation Cycle (each repetition) -- added for Ada modeling: compute all signal values io : mode; Result: -- other variables added for model: Event on a signal … Resume process statements end record; that are sensitive to the signal. Execute as part of the simulation cycle. 7. VHDL SIMULATION MODEL Initialize : Ada-95 contains the following data types from 1. At Tc = 0 (Current time) language defined packages:

7 2. Compute driving value and effective A driver of a scalar signal is represented by a value of signals. projected output waveform. (Set current value to effective A driver consist of trasactions ordered with value.) respect to time. “Transaction (value, time)” 3. Set value of implicit signals A driver’s initial value is the default value of a S’Stable (T) = True; signal. S’Quiet (T) = True; Past values of a driver get deleted as time S’Delayed (T) = initial value progresses. of signal S. Previous efforts focused on transforming high 4. Implicit guard signal = expression level languages such as Ada and C into VHDL 5. Execute each non-postponed and [12]. These efforts restricted the programming postponed process until it style of the software engineers to preclude suspends. constructs such as pointers and dynamic memory 6. Tn = Time of next simulation usage. The mapping from Ada to VHDL is not cycle the primary focus of this effort, but will be revisited in more detail later. Simulation Cycle Steps: 1. Tc = Tn (Simulation complete 8. ANALYZING VHDL when Tn = TIME’HIGH and no active drivers or process resumption at Tn) Several existing validation and verification 2. Update each explicit and implicit techniques can be used to reduce the effort signal (events on signals may involved in maintaining Ada or VHDL. occur). Automated dependence analysis [13] traces the interactions between parts of a program and 3. Each process P resumes if event occurs on signal that P is sensitive indicates the impact that modifications of a to. section of code can have on the rest of a program. 4. Execute each non-postponed Dependence analysis is a static approximation of process (that has resumed in the control and data interactions throughout a current cycle until it suspends). program [14]. Dependence analysis can detect 5. Tn (time of next cycle) = earliest of potential errors introduced by migrating software (TIME’HIGH, time driver into hardware or vice-versa. becomes active, or next time a process resumes). Coverage analysis automatically traces the parts of a program exercised by test cases during 6. Execute any postponed processes testing. Coverage analysis can indicate that resume. insufficient test sets and unexpected model behaviors, e.g., errors with control signals in VHDL Process is a concurrent statement made state machines. Although several VHDL up of one or more sequential statements. A coverage tools exist on the market, this process is passive if it contains a signal capability with IRIS/AIRE may enable coverage assignment statement. A process is executed analysis of the integrated hardware and software repetitively. system. process ::= We are currently developing a prototype [label:] [postponed] process implementation of the AIRE/IRIS integrated [(sensitivity_list)] [is] declarations -- such as variables analysis to provide insight into the potential for begin this approach. We plan to explore interfacing statements with the Arcadia analysis tools and VHDL -- wait on sensitivity list analysis and synthesis tools end block [label]; 9. CONCLUSIONS Signal assignment in a process statement defines a set of drivers for certain scalar signals. With the increasing complexity of electronic systems, better integration of the design and

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