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Hardware/Software Co-Design: VHDL and Ada 95 Code Migration And

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Hardware/Software Co-Design: VHDL and Ada 95 Code Migration And Hardware/Software Co-design: VHDL and Ada 95 Code Migration and Integrated Analysis Mike Mills and Greg Peterson Air Force Research Lab Information Technology Division Wright-Patterson AFB OH (937)-255-6653 x3591 1. ABSTRACT 2. INTRODUCTION Optimizing the design of complex The electronics design industry enjoys dramatic weapons systems constitutes an improvements in circuit capabilities, with the important task in efficiently number of transistors on a chip doubling every eighteen months as noted by Moore's Law [1]. developing and deploying effective This explosive growth represents tremendous complex weapons systems. Often potential for military and commercial electronics architectural tradeoffs between systems and components, while at the same time presenting designers with the seemingly hardware and software insurmountable task of exploiting this growth implementation must be performed effectively and economically. As a corollary to early in the design cycle, resulting in Moore's Law, the electronic systems design process demands an exponential increase in potentially inefficient systems or design productivity to keep pace with subsystems. As technologies and improvements in device density and speed. costs in hardware and software When developing electronic systems, the implementation change over time, designer typically develops models of the the best partitioning of system hardware components by starting with abstract behavioral VHSIC Hardware Description functionality into hardware and Language (VHDL) models of functionality and software components will also refining these models into register transfer level change. Currently, recasting a and eventually gate level models. Software design using high level languages such as Ada component from hardware to software often follows a similar development path in (or vice-versa) is a difficult and error- parallel to the hardware development. This top- prone activity. This paper explores a down design methodology is appealing due to its effectiveness in handling complexity, but new approach to ease the hardware often results in sub-optimal implementations due software co-design and repartitioning to the need to partition functionality into hardware and software too early in the design activities by providing a mechanism cycle. In addition, the hardware and software to exchange software written in Ada domains use different representations (languages) 95 with behavioral VHDL. which are challenging to make inter-operate. Bringing the hardware and software components into a consistent framework could help provide an effective means of co-executing hardware models with software code. Design methodologies and tools must account for these issues to ensure correct, efficient implementations of designs. Simply exploiting these improvements in designing and manufacturing electronics hardware solves only 1 half the problem: we need efficient and reliable By exploiting state of the art software methods to develop and maintain both the engineering tools and formats, a bridge between hardware and software. With advances in hardware models and software code can be reconfigurable computing, the delineation constructed. This bridge has great potential for between these two domains continues to blur. enhancing the systems design effort by Effective language support, tools, and supporting relatively effortless migration between methodologies addressing these issues will help the hardware and software domains in addition to enable the future deployment of sophisticated enabling an integrated analysis tool suite. systems and the affordable, effective maintenance of existing weapons systems. In response to a perceived need for additional support of abstract system design and As a result of research projects funded by the Air specification, a system-level design language Force Research Lab and DARPA and commercial development effort sponsored by the Industry tool development projects, an emerging, Council continues to investigate needs in this extensible intermediate format for VHDL area in preparation for extensions to VHDL or the promises high performance and space efficiency possible development a new system description for analyzed (compiled) VHDL models. The language [3]. Advanced Intermediate Representation with Extensibility (AIRE) structures VHDL models in Significant related research is in progress which abstract syntax trees with additional information could be exploited in developing the system provided as the models are analyzed, elaborated, level design language. There is a wealth of work and simulated. Standardization of AIRE for going on with VHDL and hardware design, VHDL, VHDL-AMS, and Verilog support synthesis, and test. The same can be said of continues, and a number of AIRE-compliant work for software engineering with Ada and with implementations near completion. process improvements. Complex systems include both hardware and software components. Abstract syntax trees serve a common role as a Significant recent attention focuses on how to standard representation of software code during specify, design, and verify the hardware and compilation. In order to develop a common software together. Current standardization efforts AST representation for multiple software related to codesign focus on co-simulation languages such as Ada, JOVIAL, and C++, the approaches in the short term [4] and general Arcadia group developed IRIS. By using IRIS codesign/systems design support in the long as a common foundation, a number of software term. The goal of this effort is to bring together engineering projects have been able to exploit a research results from both communities to common front end and support multiple improve systems design capabilities. languages. One Air Force Research Lab software maintenance project exploits this approach to Long-term software engineering experience port older JOVIAL code into Ada 95 [2]. proves Ada to be effective for cost-effectively managing large program development and This paper addresses efforts to provide an maintenance efforts, particularly when compared interface between VHDL models and Ada to languages such as C [5,6]. Ada is software via a common abstract syntax tree by syntactically similar to VHDL, which makes it exploiting AIRE and IRIS. We discuss this attractive as a basis for the software domain. interface, language construct limitations, and the Despite the end of the DoD Ada mandate, Ada potential for solidifying the hardware/software remains a powerful language often chosen for interface. A number of very interesting weapons systems development [7]. Ada applications exist for such an interface between provides strong typing, encapsulation via the VHDL hardware models and software written in package mechanism, and supports generics languages such as Ada. Models in hardware can among other features. Ada 95’s object oriented be ported to software for implementation, and programming, real time, and programming in the vice-versa. In addition, some of the Arcadia large features makes Ada highly competitive. software engineering tools built upon IRIS Yet, opposition to Ada has hindered general provide analysis capabilities that could prove adoption by industry. VHDL enjoys significant quite useful for VHDL. The potential for greatly use in the design automation industry. improving the state of the art in hardware modeling via these tools is discussed. 3. OVERVIEW OF VHDL 2 VHDL provides the best current capability for supporting the development and ongoing The VHDL-AMS (Analog Mixed Signal) maintenance of large, complex digital systems. extensions to VHDL provide a capability for Developed by the DoD in the 1980s to support modeling analog and mixed signal designs. The the documentation of electronic systems, VHDL VHDL-AMS standard provides a single language derives much of its syntax and semantics from in which both digital and analog circuitry effects Ada. A major difference in the languages comes can be modeled, thus giving us an integrated from the notion of concurrent processes that tool for considering analog effects for advanced permeates VHDL. Because the language is digital design. intended to model hardware components which are "always executing," VHDL is a highly 4. OVERVIEW OF AIRE concurrent language built upon a simulation cycle-based timing model. Interactions between The Advanced Intermediate Representation with VHDL processes occur over signals and include Extensibility/Common Environment (AIRE/CE) data and temporal aspects. VHDL is a Turing is currently being developed by a number of complete language and capable of representing electronic design automation tool vendors and very low level device models on up to system users and is being standardized through the models by employing appropriate abstraction. Electronic Industries Association and the IEC. Data encapsulation is part of VHDL. Although Before the design and implementation of developed initially for documentation and AIRE/CE, integration of tool components from simulation, synthesis tools now transform more distinct applications to form an entire system abstract VHDL models into detailed gate-level was severely limited by proprietary, inflexible, implementations, resulting in a dramatic low-functionality and low-performance interfaces. productivity improvement. The cost and time required to integrate best-of- breed tool components generally lead to Several past and current research and pragmatic compromises intended to reduce cost standardization efforts focus on ways
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