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US 2019 / 0042757 A1 HO Et Al US 20190042757A1 ( 19) United States (12 ) Patent Application Publication ( 10) Pub . No. : US 2019 / 0042757 A1 HO et al. ( 43 ) Pub . Date : Feb . 7 , 2019 ( 54 ) MECHANISMS FOR BOOTING A (52 ) U .S . CI. COMPUTING DEVICE AND CPC . .. .. .. G06F 21 /575 ( 2013 .01 ) ; G06F 9 /4406 PROGRAMMABLE CIRCUIT ( 2013. 01 ) ; G06F 21/ 572 ( 2013 .01 ) ( 71 ) Applicant: Intel Corporation , Santa Clara , CA (US ) (57 ) ABSTRACT (72 ) Inventors : Yah Wen HO , Butterworth (MY ) ; Tung Lun LOO , Bayan Lepas (MY ) ; Yan Apparatus, systems, or methods for a programmable circuit Fei LEE , Gelugor (MY ) to facilitate a processor to boot a computing device having ( 21 ) Appl. No .: 15 /934 , 760 the processor. A programmable circuit may include non volatile storage and firmware stored in the non -volatile ( 22 ) Filed : Mar . 23 , 2018 storage . The firmware may configure the programmable circuit as a memory controller of a memory device coupled Publication Classification to the programmable circuit, to facilitate the processor to (51 ) Int . Cl. boot the computing device having the processor, the pro G06F 21/ 57 ( 2006 .01 ) grammable circuit , and the memory device, into operation . G06F 9 /4401 (2006 .01 ) Other embodiments may also be described and claimed . 100 105 Memory device 101 Programmable circuit 113 103 Non -voltatile 111 storage 115 Memory Processor controller Firmware 131 Computing device Patent Application Publication Feb . 7 , 2019 Sheet 1 of 6 US 2019 /0042757 A1 103 Computingdevice 131 105 Memory device Processor Figure1 Memory 111 controller Programmable circuit nware Non-voltatile storage 115 101 113 100_ Patent Application Publication Feb . 7 , 2019 Sheet 2 of 6 US 2019 /0042757 A1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 233 - - - - Computingdevice - - - - Mainmemorydevice - - - - - - - - - - - - - - - - - - - - - - - - - - - - 231 - - Processor OS - 203 - - 207 - - - - - - - - - - - - 253 - - - - - - Non-volatilememorydevice - - - - - Figure2 - - - - - - - - - - - - - - - - - - - - - - Bootcode - - - - - - - - memorydevice - Non-volatile - - - Peripheraldevice - - - 251 - - - Mainmemory controller - - 205 - - - - 217 - 211 219 - - controller controller - - - - - - - - - 202 - - - - - - - - - - - - - Bootcode - - - - - - - - - - - - Non-voltatile - - Firmware - - Datastorage - - storage 214 - - Package204 Programmable 215 - - 212 - - circuit - - - - 213 201 - - - - Computingdevice - - - - - - - - - - - - - - 200 Patent Application Publication Feb . 7 , 2019 Sheet 3 of 6 US 2019 /0042757 A1 Configuringaprogrammablecircuit asaperipheraldevicetoprocessorof acomputingdevice 321 Configuringaprogrammablecircuitas volatilememorydeviceintodatastorageof Configuringtheprogrammablecircuitasa hardwareacceleratorofanapplication,afterthe memorycontrollerforanon-volatile memorydeviceorbootcodestoredin Providingthebootcodestoredin processorhasbootedthecomputingdeviceinto Authenticatingthenon-volatile Copyingthebootcodefromnon datastorageoftheprogrammablecircuit totheprocessorbootcomputing thenon-volatilememorydevice circuitprogrammablethe Figure3 memorydevice device operation. 3111 mannende 31 315 319 Configuringaprogrammablecircuitas memorydeviceofacomputing Initializingthemainmemorydeviceby Notifyingaprocessorofthecomputing deviceafterthemainmemoryhas amemorycontrollerformain theprogrammablecircuit beeninitializedbytheprogrammable 300 301 circuit 303 305 Patent Application Publication Feb . 7 , 2019 Sheet 4 of 6 US 2019 /0042757 A1 Receivinganotificationfrom programmablecircuitafterthemaininitializedbybeen hasmemorydevice circuitprogrammablethe 415 Configuringtheprogrammablecircuitas ahardwareacceleratorofanapplication 417 Accessingbootcodeinanon-volatilememorydevicethrough Enteringapoweronstateorreset Performingsiliconandplatforminitializationforthecomputingdevicebasedonbootcode Determiningamainmemorydevicecoupled Performingmorebootoperationsusingthe Loadinganoperatingsystem Figure4 circuitprogrammable totheprocessorhasbeeninitialized fromthenon-volatilememory mainmemorydevice 411 device 405- 401 403 407 409 Transferringcontroltoan operatingsystemloadedfrom thenon-volatilememorydevice 413 400_ Patent Application Publication Feb . 7 , 2019 Sheet 5 of 6 US 2019 / 0042757 A1 Displayscreen 514Sensors 513 *521Inputdevice 500 512 NIC 511 Figure5 circuitry TX interface/OI 517Receiver 505Communication 518 523 Transmitter KA 516 531 535 539 537 532 Processor(s)502 Hardwareaccelerator503 MainMemorydevice504 circuit506Programmable Storage Mainmemorycontroller Peripheraldevicecontroller Non-volatilememorydevice 508 controller Hardwareaccelerator Firmware Patent Application Publication Feb . 7 , 2019 Sheet 6 of 6 US 2019 / 0042757 A1 602 Programminginstructions604 programminginstructions,topractice(aspectsof)embodimentsthe Non-TransitoryComputerReadableStorageMedium configuredtocauseadevice,inresponseexecutionofthe Figure6 methodsdescribedherein 600 US 2019 / 0042757 A1 Feb . 7 , 2019 MECHANISMS FOR BOOTING A perform some early silicon initialization , e . g . , setting up COMPUTING DEVICE AND cache , main memory initialization , etc . , and then proceed to PROGRAMMABLE CIRCUIT execute the bootloader for other memory devices to load the operating system from other memory devices . Afterwards , FIELD the operating system may control and load a separate kernel driver for handling the memory devices . Hence , the com [ 0001 ] Embodiments of the present disclosure relate gen puting device may be booted by using ROM and other erally to the technical fields of computing , and more par memory devices in two separated steps . Such a two steps ticularly to the employment of a programmable circuit in boot process may be slow , and with increased security risk facilitating booting a computing device into operation . posted by separated storage devices — a ROM and other BACKGROUND memory devices . [0002 ] The background description provided herein is for [ 0012 ] Unlike an application specific integrated circuit the purpose of generally presenting the context of the having a fixed function after the silicon is formed , a pro disclosure. Unless otherwise indicated herein , the materials grammable circuit may have an undefined function at the described in this section are not prior art to the claims in this time ofmanufacture , which may be configured (and later on , application and are not admitted to be prior art by inclusion reconfigured ) after being manufactured to perform various in this section . functions . For example , a programmable circuit may be a 10003 ] A computing device may be a device capable of field programmable gate array (FPGA ) device , and may automatically carrying out a sequence of arithmetic or have intended functions for applications in areas such as logical operations. A computing device may include many artificial intelligence , deep learning , computer vision and components , e . g . , a processor, a memory device , or other I / O extensions . In addition to the intended functions, a components . A programmable circuit may be used in com FPGA device may be configured for other purposes , e . g . , bination with a processor in a computing device to offload facilitating a booting process of a computing device . processing tasks from the processor to the programmable [0013 ] Embodiments herein may present a computing circuit to speed up some processing tasks. For example , device that may include a programmable circuit . A program there has been increasing use of programmable circuits , such mable circuit may facilitate a processor of a computing as field programmable gate arrays (FPGA ) to perform arti device to boot the computing device into operation . For ficial intelligence ( neural networking ) related processing. example , a programmable circuit may be configured as a non - volatile memory device controller to boot the comput BRIEF DESCRIPTION OF THE DRAWINGS ing device with boot code stored in the non - volatile memory device . After the processor has booted the computing device [0004 ] Embodiments will be readily understood by the into operation , the programmable circuit may be reconfig following detailed description in conjunction with the ured to another function , e . g . , as a hardware accelerator of accompanying drawings . To facilitate this description , like an application . Accordingly , embodiments herein may boot reference numerals designate like structural elements . a computing device using one single non - volatile memory Embodiments are illustrated by way of example and not by device , e . g . , a raw NAND flash memory. Hence, the com way of limitation in the figures of the accompanying draw puting device may have increased security and improved ings. speed in the boot process . Initialization of a main memory [ 0005 ] FIG . 1 illustrates an example apparatus including a device of the computing device may be facilitated by a programmable circuit to facilitate booting a computing programmable circuit and performed in parallel with other device into operation , in accordance with various embodi ments . some early silicon initializations of the computing device . [ 0006 ] FIG . 2 illustrates another example apparatus [ 0014 ] In embodiments , a programmable circuit may including a programmable circuit to facilitate booting a include non - volatile storage and firmware stored in the computing device into operation , in accordance with various non - volatile storage . The firmware may configure the pro embodiments . grammable circuit
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