DOCSLIB.ORG

Microprocessor Architecture

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Microprocessor Architecture OPROCESSOR TODAY Michael Safer mrom their humble beginnings 25 years communication tasks in multimedia PCs. ago, microprocessors have proliferat- Although the desktop computer market MicroDesign Resources r ed into an astounding range of chips, tends to discard old processors in just a few powering devices ranging from telephones years, many processors survive for an amaz- to supercomputers. Today, microprocessors ingly long time in the embedded market. for personal computers get widespread Personal computers have moved from 8- to attention-and have enabled Intel to 16-bit and now to 32-bit processors, and become the world’s largest semiconductor many workstations and servers are already maker. In addition, embedded micro- using 64-bit microprocessors. In the embed- processors are at the heart of a diverse range ded market, however, even 4-bit micro- of devices that have become staples of con- processors continue to sell well, and E-bit sumers worldwide. devices lead in volume. Microprocessors have become specialized Figure 1 shows the changes in market in many ways. Those for desktop computers share for 32- and 64-bit microprocessors over fall into classes based on their instruction set the past five years. Driven by the success of architectures: either x86, the primary sur- the PC, the x86 architecture has dominated. viving complex instruction set computing Motorola’s 68000 has held a strong second- (CISC) architecture, or one of the five major place position in units (though not in dollars), reduced instruction set computing (RISC) with the embedded market as its stronghold. architectures-PA-RISC, Mips, Spare, Alpha, Hitachi’s SuperH has come from nowhere to and PowerPC. Such chips typically integrate take third place, while other architectures few functions other than cache memory and have much more modest positions. As the bus interfaces with the processor but usual- dramatic changes during this period show, ly include a floating-point unit and memory market share’can be quite turbulent among management unit. these second-tier embedded processors. Embedded microprocessors, on the other There are far more microprocessors avail- hand, typically do not have floating-point or able for sale today than it would be possible memory management units but often inte- to describe, even briefly, in an article such as grate various peripheral functions with the this. The current market includes more than 50 processor to reduce system cost. This makes surviving instruction set architectures, hun- them more application specific, leading to a dreds of different implementations, and thou- Microprocessor massive proliferation of devices character- sands of minor variations. Rather than ized not only by their processor’s instruction attempting to be comprehensive, I will focus Report’s publisher set and core CPU performance but also by on a selection of the leading-edge micro- their on-chip peripherals. processors and issues in each market segment. outlines technology Digital signal processors (DSPs) are the most specialized embedded microprocessors. Dividing up the market and businessissues in Designed for real-time processing of digitized Microprocessors for personal computers analog signals, these processors have unique get the most public attention because the today’s instruction sets and other architectural features performance and compatibility of PCs that give them high performance for a rela- depend on the microprocessors at their microprocessor tively narrow range of tasks. Recently, a new cores. In recent years, PC microprocessors class of DSPs, called media processors, has have become so high profile that a bug of industry. emerged to handle audio, video, graphics, and minor significance in Intel’s Pentium proces- 32 IEEE Micro 0272-1732/96/$5.00 0 1996 IEEE sor captured headlines in the mainstream press for months. 70 Microprocessor commercials even appear on prime-time tele- vision. Embedded applications, on the other hand, have a 60 fixed complement of software, so the microprocessor inside is of relatively little interest to the consumer. PC microprocessors are also a major profit area in the micro- 50 processor business. PCs are the only application so far that 9 uses expensive microprocessors-typically costing $75 to =s E 40 $5OC-in volumes of tens of millions per year Embedded appli- cations use far more processor+literally billions per year-but $ most of them are very low cost devices, selling for under $5, g 30 with thin profit margins. Some embedded applications use (0 < In processors in the same price range as PCs, but they are very .E low volume-often only thousands of units per year. Today, 3 20 I even among 32-bit embedded processors, more than 60 chips sell for less than $40 and some for less than $10. 10 Microprocessors for PCs generate far more profit than embedded processors for two reasons. First, because the PC is the most expensive device to use a microprocessor in high volume, PC makers can afford more expensive processors. 0’ When coupled with large amounts of DRAM, disk drives, 1991 1992 1993 1994 1995 and CRT displays that cost hundreds of dollars each, even a Year relatively expensive microprocessor does not dominate sys- tem cost. Second, the overwhelming importance of software Figure 1. Unit shipments of leading 32- and 64.bit archi- compatibility in the PC market has enabled Intel to achieve tectures. tremendous control over the PC microprocessor market. With no close competitors, Intel can enforce much higher profit margins than makers of embedded microprocessors, which designed for workstations. Because they are built in much must compete in a field where instruction set compatibility lower volumes than PC microprocessors, their amortized commands less value. design cost per unit is much greater. Such processors have Unix workstations constitute the high-performance segment survived primarily because they enable system businesses of the desktop computer market. (I use the term desktop com- that produce far more revenue (and profit) than would the puter as a shorthand for a single-user, general-purpose com- sale of a comparable number of microprocessors. This eco- puter; in this context, it includes deskside and portable systems nomic reality has led to large workstation makers designing as well as true desktops, workstations as well as PCs, and even nearly all of today’s workstation-specific microprocessors, many servers.) The workstation market has some of the same with chip companies playing little more than a foundry role. attributes as the PC market, in that application software com- As microprocessors for PCs have increased in speed, they patibility with previous-generation systems is of great impor- have reached a performance level that makes them suitable tance. There are two big differences, however. First, the total for much of the workstation market. This factor, combined Unix workstation market, in units, is less than 1% of the PC with the emergence of Microsoft’s Windows NT as a viable market, and second, performance is more important than alternative to Unix as a workstation operating system, is lead- price. As a result, microprocessors for workstations are typi- ing to a convergence of the technology for PCs with that for cally designed with performance as a higher priority than workstations. Ultimately, this convergence will threaten the price. survival of some of the workstation processor architectures. This digression into business issues is necessary for any com- prehensive discussion of the microprocessor industry, because The battle for the desktop these issues have a pervasive effect on microprocessor design Two operating systems account for the vast majority of desk- and manufacturing. Companies such as Intel and Motorola top computer use today: Microsoft Windows (in its various ver- fund leading-edge manufacturing plants for logic devices with sions) and Macintosh. IBM’s OS/2 is in third place, and Unix the high profits they make (or hope to make) supplying micro- is a distant fourth. Windows’ popularity has given Intel’s x86 processors for desktop computers. In contrast, makers of architecture a preeminent position, while the Macintosh has embedded processors generally get by with lower cost manu- established PowerPC as the only RISC architecture with a sig- facturing processes and depreciated fabrication plants. The nificant share of the desktop market. Even so, the Mac’s share divergent characters of the embedded and PC microprocessor is modest-around @&--and shows no signs of increasing. markets also drives the evolution of instruction set architec- Nearly every maker of RISC microprocessors has dreamed tures: New architectures find relatively easy entry into the of capturing part of the x86 architecture’s high-volume mar- embedded market, while desktop processor makers go to great ket. The first to try was Sun, which hoped to repeat the PC lengths to stick with dominant architectures. industry phenomenon by making its Spare-based worksta- Economics have had a huge effect on microprocessors tions, running Sun’s version of Unix, an openly licensed stan- December 1996 33 Digital plans to begin moving down into high-end PCs, setting the stage for an eventual attack on the mainstream PC market. It is a long shot for Alpha to capture a significant mainstream role, but at least it can’t be counted out yet. It is in this light that PowerPC’s position in the Windows NT Digital Semiconductor Mitsubishi, Samsung market appears so weak. PowerPC processors are not nearly Mips Technologies IDT, NEC, Toshiba as fast as the Alpha chips and don’t offer a significant perfor- Hewlett-Packard Hitachi, Samsung mance advantage over Intel processors, leaving them between Apple, IBM, Motorola Groupe Bull, Exponential a rock and a hard place. Customers looking for safety and com- Sun Microelectronics Fujitsu (includes HaL, patibility choose Intel; those seeking maximum performance on a small set of applications are drawn to Alpha. This leaves few for whom PowerPC would be a compelling choice.
Load more

Recommended publications
  • Intel® Strongarm® SA-1110 High- Performance, Low-Power Processor for Portable Applied Computing Devices
    Advance Copy Intel® StrongARM® SA-1110 High- Performance, Low-Power Processor For Portable Applied Computing Devices PRODUCT HIGHLIGHTS ■ Innovative Application Specific Standard Product (ASSP) delivers leadership performance, integration and low power for palm-size devices, PC companions, smart phones and other emerging portable applied computing devices As businesses and individuals rely increasingly on portable applied ■ High-speed 100 MHz memory bus and a computing devices to simplify their lives and boost their productivity, flexible memory these devices have to perform more complex functions quickly and controller that adds efficiently. To satisfy ever-increasing customer demands to support for SDRAM, communicate and access information ‘anytime, anywhere’, SMROM, and variable- manufacturers need technologies that deliver high-performance, robust latency I/O devices — provides design functionality and versatility while meeting the small-size and low-power flexibility, scalability and restrictions of portable, battery-operated products. Intel designed the high memory bandwidth SA-1110 processor with all of these requirements in mind. ■ Rich development The Intel® SA-1110 is a highly integrated 32-bit StrongARM® environment enables processor that incorporates Intel design and process technology along leading edge products with the power efficiency of the ARM* architecture. The SA-1110 is while reducing time- to-market software compatible with the ARM V4 architecture while utilizing a high-performance micro-architecture that is optimized to take advantage of Intel process technology. The Intel SA-1110 provides the performance, low power, integration and cost benefits of the Intel SA-1100 processor plus a high speed memory bus, flexible memory controller and the ability to handle variable-latency I/O devices.
    [Show full text]
  • MIPS Architecture
    Introduction to the MIPS Architecture January 14–16, 2013 1 / 24 Unofficial textbook MIPS Assembly Language Programming by Robert Britton A beta version of this book (2003) is available free online 2 / 24 Exercise 1 clarification This is a question about converting between bases • bit – base-2 (states: 0 and 1) • flash cell – base-4 (states: 0–3) • hex digit – base-16 (states: 0–9, A–F) • Each hex digit represents 4 bits of information: 0xE ) 1110 • It takes two hex digits to represent one byte: 1010 0111 ) 0xA7 3 / 24 Outline Overview of the MIPS architecture What is a computer architecture? Fetch-decode-execute cycle Datapath and control unit Components of the MIPS architecture Memory Other components of the datapath Control unit 4 / 24 What is a computer architecture? One view: The machine language the CPU implements Instruction set architecture (ISA) • Built in data types (integers, floating point numbers) • Fixed set of instructions • Fixed set of on-processor variables (registers) • Interface for reading/writing memory • Mechanisms to do input/output 5 / 24 What is a computer architecture? Another view: How the ISA is implemented Microarchitecture 6 / 24 How a computer executes a program Fetch-decode-execute cycle (FDX) 1. fetch the next instruction from memory 2. decode the instruction 3. execute the instruction Decode determines: • operation to execute • arguments to use • where the result will be stored Execute: • performs the operation • determines next instruction to fetch (by default, next one) 7 / 24 Datapath and control unit
    [Show full text]
  • Comparison of Contemporary Real Time Operating Systems
    ISSN (Online) 2278-1021 IJARCCE ISSN (Print) 2319 5940 International Journal of Advanced Research in Computer and Communication Engineering Vol. 4, Issue 11, November 2015 Comparison of Contemporary Real Time Operating Systems Mr. Sagar Jape1, Mr. Mihir Kulkarni2, Prof.Dipti Pawade3 Student, Bachelors of Engineering, Department of Information Technology, K J Somaiya College of Engineering, Mumbai1,2 Assistant Professor, Department of Information Technology, K J Somaiya College of Engineering, Mumbai3 Abstract: With the advancement in embedded area, importance of real time operating system (RTOS) has been increased to greater extent. Now days for every embedded application low latency, efficient memory utilization and effective scheduling techniques are the basic requirements. Thus in this paper we have attempted to compare some of the real time operating systems. The systems (viz. VxWorks, QNX, Ecos, RTLinux, Windows CE and FreeRTOS) have been selected according to the highest user base criterion. We enlist the peculiar features of the systems with respect to the parameters like scheduling policies, licensing, memory management techniques, etc. and further, compare the selected systems over these parameters. Our effort to formulate the often confused, complex and contradictory pieces of information on contemporary RTOSs into simple, analytical organized structure will provide decisive insights to the reader on the selection process of an RTOS as per his requirements. Keywords:RTOS, VxWorks, QNX, eCOS, RTLinux,Windows CE, FreeRTOS I. INTRODUCTION An operating system (OS) is a set of software that handles designed known as Real Time Operating System (RTOS). computer hardware. Basically it acts as an interface The motive behind RTOS development is to process data between user program and computer hardware.
    [Show full text]
  • ARM Architecture
    ARM Architecture Comppgzuter Organization and Assembly ygg Languages Yung-Yu Chuang with slides by Peng-Sheng Chen, Ville Pietikainen ARM history • 1983 developed by Acorn computers – To replace 6502 in BBC computers – 4-man VLSI design team – Its simp lic ity comes from the inexper ience team – Match the needs for generalized SoC for reasonable power, performance and die size – The first commercial RISC implemenation • 1990 ARM (Advanced RISC Mac hine ), owned by Acorn, Apple and VLSI ARM Ltd Design and license ARM core design but not fabricate Why ARM? • One of the most licensed and thus widespread processor cores in the world – Used in PDA, cell phones, multimedia players, handheld game console, digital TV and cameras – ARM7: GBA, iPod – ARM9: NDS, PSP, Sony Ericsson, BenQ – ARM11: Apple iPhone, Nokia N93, N800 – 90% of 32-bit embedded RISC processors till 2009 • Used especially in portable devices due to its low power consumption and reasonable performance ARM powered products ARM processors • A simple but powerful design • A whlhole filfamily of didesigns shiharing siilimilar didesign principles and a common instruction set Naming ARM •ARMxyzTDMIEJFS – x: series – y: MMU – z: cache – T: Thumb – D: debugger – M: Multiplier – I: EmbeddedICE (built-in debugger hardware) – E: Enhanced instruction – J: Jazell e (JVM) – F: Floating-point – S: SthiiblSynthesizible version (source code version for EDA tools) Popular ARM architectures •ARM7TDMI – 3 pipe line stages (ft(fetc h/deco de /execu te ) – High code density/low power consumption – One of the most used ARM-version (for low-end systems) – All ARM cores after ARM7TDMI include TDMI even if they do not include TDMI in their labels • ARM9TDMI – Compatible with ARM7 – 5 stages (fe tc h/deco de /execu te /memory /wr ite ) – Separate instruction and data cache •ARM11 ARM family comparison year 1995 1997 1999 2003 ARM is a RISC • RISC: simple but powerful instructions that execute within a single cycle at high clock speed.
    [Show full text]
  • The Von Neumann Computer Model 5/30/17, 10:03 PM
    The von Neumann Computer Model 5/30/17, 10:03 PM CIS-77 Home http://www.c-jump.com/CIS77/CIS77syllabus.htm The von Neumann Computer Model 1. The von Neumann Computer Model 2. Components of the Von Neumann Model 3. Communication Between Memory and Processing Unit 4. CPU data-path 5. Memory Operations 6. Understanding the MAR and the MDR 7. Understanding the MAR and the MDR, Cont. 8. ALU, the Processing Unit 9. ALU and the Word Length 10. Control Unit 11. Control Unit, Cont. 12. Input/Output 13. Input/Output Ports 14. Input/Output Address Space 15. Console Input/Output in Protected Memory Mode 16. Instruction Processing 17. Instruction Components 18. Why Learn Intel x86 ISA ? 19. Design of the x86 CPU Instruction Set 20. CPU Instruction Set 21. History of IBM PC 22. Early x86 Processor Family 23. 8086 and 8088 CPU 24. 80186 CPU 25. 80286 CPU 26. 80386 CPU 27. 80386 CPU, Cont. 28. 80486 CPU 29. Pentium (Intel 80586) 30. Pentium Pro 31. Pentium II 32. Itanium processor 1. The von Neumann Computer Model Von Neumann computer systems contain three main building blocks: The following block diagram shows major relationship between CPU components: the central processing unit (CPU), memory, and input/output devices (I/O). These three components are connected together using the system bus. The most prominent items within the CPU are the registers: they can be manipulated directly by a computer program. http://www.c-jump.com/CIS77/CPU/VonNeumann/lecture.html Page 1 of 15 IPR2017-01532 FanDuel, et al.
    [Show full text]
  • MIPS IV Instruction Set
    MIPS IV Instruction Set Revision 3.2 September, 1995 Charles Price MIPS Technologies, Inc. All Right Reserved RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and / or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor / manufacturer is MIPS Technologies, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. R2000, R3000, R6000, R4000, R4400, R4200, R8000, R4300 and R10000 are trademarks of MIPS Technologies, Inc. MIPS and R3000 are registered trademarks of MIPS Technologies, Inc. The information in this document is preliminary and subject to change without notice. MIPS Technologies, Inc. (MTI) reserves the right to change any portion of the product described herein to improve function or design. MTI does not assume liability arising out of the application or use of any product or circuit described herein. Information on MIPS products is available electronically: (a) Through the World Wide Web. Point your WWW client to: http://www.mips.com (b) Through ftp from the internet site “sgigate.sgi.com”. Login as “ftp” or “anonymous” and then cd to the directory “pub/doc”. (c) Through an automated FAX service: Inside the USA toll free: (800) 446-6477 (800-IGO-MIPS) Outside the USA: (415) 688-4321 (call from a FAX machine) MIPS Technologies, Inc.
    [Show full text]
  • P6 Underscores Intel's Lead: 2/16/95
    MICROPROCESSOR REPORT MICROPROCESSOR REPORT THE INSIDERS’ GUIDE TO MICROPROCESSOR HARDWARE VOLUME 9 NUMBER 2 FEBRUARY 16, 1995 P6 Underscores Intel’s Lead Sets New x86 Performance Standard, Thrusts into Server Market by Linley Gwennap Accelerating the Generational Pace While its competitors struggle to complete their The P6 is the first fruit of Intel’s effort to double its Pentium-class chips, Intel is well on the way to deliver- pace of processor generations. In the past, new x86 pro- ing its next-generation P6 processor. Looking under the cessor cores have rolled out every four years or so from hood (see page 9), we see that the microarchitecture of what was essentially a single design team at Intel’s main the P6 is not that different from the design of AMD’s K5 facility in Santa Clara (California). The P6 is the first or even NexGen’s 586. From the user’s perspective, x86 processor core from the company’s Hillsboro (Ore- though, the difference is clear: the first P6 should out- gon) team, which had previously focused on i960 chips. perform its competitors by about 50% on typical applica- The P6 project began in late 1991, several months before tions, based on initial performance estimates. the first tape out of the Pentium processor. Intel estimates that the P6 will deliver 200 SPEC- The decision to start a second x86 design center int92 at 133 MHz, the target frequency of the initial im- shows excellent foresight. Without the P6, Intel’s high plementation, although it has not yet announced any end throughout 1996 would have been limited to 150- specific P6 products.
    [Show full text]
  • Lecture Notes
    Lecture #4-5: Computer Hardware (Overview and CPUs) CS106E Spring 2018, Young In these lectures, we begin our three-lecture exploration of Computer Hardware. We start by looking at the different types of computer components and how they interact during basic computer operations. Next, we focus specifically on the CPU (Central Processing Unit). We take a look at the Machine Language of the CPU and discover it’s really quite primitive. We explore how Compilers and Interpreters allow us to go from the High-Level Languages we are used to programming to the Low-Level machine language actually used by the CPU. Most modern CPUs are multicore. We take a look at when multicore provides big advantages and when it doesn’t. We also take a short look at Graphics Processing Units (GPUs) and what they might be used for. We end by taking a look at Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC). Stanford President John Hennessy won the Turing Award (Computer Science’s equivalent of the Nobel Prize) for his work on RISC computing. Hardware and Software: Hardware refers to the physical components of a computer. Software refers to the programs or instructions that run on the physical computer. - We can entirely change the software on a computer, without changing the hardware and it will transform how the computer works. I can take an Apple MacBook for example, remove the Apple Software and install Microsoft Windows, and I now have a Window’s computer. - In the next two lectures we will focus entirely on Hardware.
    [Show full text]
  • SH-1/SH-2/SH-DSP Programming Manual
    Hitachi SuperH™ RISC Engine SH-1/SH-2/SH-DSP Programming Manual ADE-602-063C Rev. 4.0 5/13/99 Hitachi ,Ltd Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
    [Show full text]
  • Superh RISC Engine SH-1/SH-2
    SuperH RISC Engine SH-1/SH-2 Programming Manual September 3, 1996 Hitachi America Ltd. Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Introduction The SuperH RISC engine family incorporates a RISC (Reduced Instruction Set Computer) type CPU. A basic instruction can be executed in one clock cycle, realizing high performance operation. A built-in multiplier can execute multiplication and addition as quickly as DSP.
    [Show full text]
  • Design and VHDL Implementation of an Application-Specific Instruction Set Processor
    Design and VHDL Implementation of an Application-Specific Instruction Set Processor Lauri Isola School of Electrical Engineering Thesis submitted for examination for the degree of Master of Science in Technology. Espoo 19.12.2019 Supervisor Prof. Jussi Ryynänen Advisor D.Sc. (Tech.) Marko Kosunen Copyright © 2019 Lauri Isola Aalto University, P.O. BOX 11000, 00076 AALTO www.aalto.fi Abstract of the master’s thesis Author Lauri Isola Title Design and VHDL Implementation of an Application-Specific Instruction Set Processor Degree programme Computer, Communication and Information Sciences Major Signal, Speech and Language Processing Code of major ELEC3031 Supervisor Prof. Jussi Ryynänen Advisor D.Sc. (Tech.) Marko Kosunen Date 19.12.2019 Number of pages 66+45 Language English Abstract Open source processors are becoming more popular. They are a cost-effective option in hardware designs, because using the processor does not require an expensive license. However, a limited number of open source processors are still available. This is especially true for Application-Specific Instruction Set Processors (ASIPs). In this work, an ASIP processor was designed and implemented in VHDL hardware description language. The design was based on goals that make the processor easily customizable, and to have a low resource consumption in a System- on-Chip (SoC) design. Finally, the processor was implemented on an FPGA circuit, where it was tested with a specially designed VGA graphics controller. Necessary software tools, such as an assembler were also implemented for the processor. The assembler was used to write comprehensive test programs for testing and verifying the functionality of the processor. This work also examined some future upgrades of the designed processor.
    [Show full text]
  • 486 COMMON SOCKET IMPLEMENTATION by J
    486 COMMON SOCKET IMPLEMENTATION by J. Lombard, M. Lerman 1. Overview For additional information, please contact This document provides detailed information SGS-Thomson Microelectronics. Information in this document is subject to change without regarding the differences in pinouts between notification. The following documents were used SGS-THOMSON Microelectronics(ST) and Intel as references: Intel486 Microprocessor Family, 486 PGA devices and specifies electrical connections that allow a single motherboard AM486 Microprocessor Family System Design Consideration. Any functions not disclosed in the design to support all of the listed devices. This referenced documents are NOT covered by the implementation is intended to be a guideline to scope of this specification. eliminate conflicts due to pinout differences only. 2. CPU Features This common socket specification is intended to support the following devices: Each of the CPUs supported in this common socket specification is 486 bus compatible yet SGS-THOMSON ST486 DX2 CYRIX Cx486 DX2 has a unique set of features that impacts the device pinout. Table 2-1 lists the differences in SGS-THOMSON ST486 DX2V the CPU feature sets. SGS-THOMSON ST486 DX4V SGS-THOMSON ST5x86 CYRIX Cx5x86 INTEL i486 DX2 SL & WB Enhanced INTEL i486 DX4 AMD AM486 DX2 (Future SL & WB Enhanced) AMD AM486 DX4 (Future SL & WB Enhanced) Table 2-1. CPU Enhanced Features CPU VOLTAGE WRITE- SMM & POWER CORE CLOCK BACK MANAGEMENT CONTROL JTAG ST486DX2 5 V yes yes no no Cx486DX2 ST486DX2V 3.45V, 5V I/O yes yes no no Future AM486DX2 ST486DX4V 3.45V, 5V I/O yes yes 2x, 3x no Future AM486DX2 ST5x86 3.45V, 5V I/O yes yes 0.5x, 1x, 2x, 3x yes Cx5x86 Intel i486DX/DX2 SL & WB 5 V yes yes no yes Enh.
    [Show full text]