COTS PEM BOOT SECTOR FLASH AS29LV016

16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS PERFORMANCE CHARACTERISTICS

Commercial Off The Shelf, up-screened device High performance Single power supply operation — Access times as fast as 70 ns @ Enhanced — Full voltage range: 2.7 to 3.6 volt read and write Temp [/ET] operations for battery-powered applications — Extended temp range available [/XT] (-55°C to Manufactured on 200nm process technology +125°C) Flexible sector architecture Ultra low power consumption (typical values at 5 MHz) — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and — 200 nA Automatic Sleep mode current thirty-one 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and — 200 nA standby mode current thirty-one 32 Kword sectors (word mode) — 9 mA read current Sector Protection features — 20 mA program/erase current — A hardware method of locking a sector to Cycling endurance: 1,000,000 cycles per sector prevent any program or erase operations within typical that sector Data retention: 20 years typical — Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code SOFTWARE FEATURES changes in previously locked sectors CFI (Common Flash Interface) compliant Unlock Bypass Program Command — Provides device-specifi c information to the — Reduces overall programming time when issuing system, allowing host software to easily multiple program command sequences reconfi gure for different Flash devices Top or bottom boot block confi gurations Erase Suspend/Erase Resume available — Suspends an erase operation to read data from, Compatibility with JEDEC standards or program data to, a sector that is not being — Pinout and software compatible with single- erased, then resumes the erase operation power supply Flash Data# Polling and toggle bits — Superior inadvertent write protection — Provides a software method of detecting program or erase operation completion

PACKAGE OPTIONS HARDWARE FEATURES 48-pin TSOP1 Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#)

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 1 COTS PEM BOOT SECTOR FLASH AS29LV016

GENERAL DESCRIPTION The AS29LV016 is a 16 Mbit, 3.0 Volt-only already programmed) before executing the erase Flash memory organized as 2,097,152 bytes operation. During erase, the device automatically or 1,048,576 words. The word-wide data (x16) times the erase pulse widths and verifi es proper appears on DQ15–DQ0; the byte-wide (x8) data cell margin. appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard The host system can detect whether a program or system 3.0 volt VCC supply. A 12.0 V VPP or 5.0 erase operation is complete by observing the RY/

VCC are not required for write or erase operations. BY# pin, or by reading the DQ7 (Data# Polling) The device can also be programmed in standard and DQ6 (toggle) status bits. After a program EPROM programmers. or erase cycle has been completed, the device is ready to read array data or accept another The device offers access times of 70 ns, 90 ns command. and 100 ns allowing high speed microprocessors to operate without wait states. To eliminate bus The sector erase architecture allows memory contention the device has separate chip enable sectors to be erased and reprogrammed without (CE#), write enable (WE#) and output enable affecting the data contents of other sectors. The (OE#) controls. device is fully erased when shipped from the factory. The device requires only a single 3.0 volt power supply for both read and write functions. Hardware data protection measures include

Internally generated and regulated voltages are a low VCC detector that automatically inhibits provided for the program and erase operations. write operations during power transitions. The hardware sector protection feature disables The AS29LV016 is entirely command set compatible both program and erase operations in any with the JEDEC single-power-supply Flash combination of the sectors of memory. This standard. Commands are written to the can be achieved in-system or via programming command register using standard microprocessor equipment. write timings. Register contents serve as input to an internal state-machine that controls the erase The Erase Suspend/Erase Resume feature and programming circuitry. Write cycles also enables the user to put erase on hold for any internally latch addresses and data needed for period of time to read data from, or program data the programming and erase operations. Reading to, any sector that is not selected for erasure. True data out of the device is similar to reading from background erase can thus be achieved. other Flash or EPROM devices. The hardware RESET# pin terminates any Device programming occurs by executing the operation in progress and resets the internal state program command sequence. This initiates the machine to reading array data. The RESET# pin Embedded Program algorithm—an internal may be tied to the system reset circuitry. A system algorithm that automatically times the program reset would thus also reset the device, enabling pulse widths and verifi es proper cell margin. the system microprocessor to read the boot-up The Unlock Bypass mode facilitates faster fi rmware from the Flash memory. programming times by requiring only two write cycles to program data instead of four. The device offers two power-saving features. When addresses have been stable for a specifi ed Device erasure occurs by executing the erase amount of time, the device enters the automatic command sequence. This initiates the Embedded sleep mode. The system can also place the device Erase algorithm—an internal algorithm that into the standby mode. Power consumption is automatically preprograms the array (if it is not

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 2 COTS PEM BOOT SECTOR FLASH AS29LV016

PRODUCT SELECTOR GUIDE

Family Part Number AS29LV016 Speed Option Voltage Range: Vcc = 2.7-3.6V 70 90 100

Max access time, ns (tACC ) 70 90 100

Max CE# access time, ns (tCE ) 70 90 100

Max OE# access time, nc (tOE ) 30 35 40 Note: See AC Characteristics on page 29 for full specifications

BLOCK DIAGRAMg

RY/BY# DQ0–DQ15 (A-1) VCC Sector Switches VSS

Erase Voltage Input/Output RESET# Generator Buffers

WE# State Control BYTE# Command Register PGM Voltage Generator

Chip Enable Data STB Latch CE# Output Enable Logic OE#

Y-Decoder Y-Gating STB

VCC Detector Timer

X-Decoder Cell Matrix

A0–A19 Latch Address

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 3 COTS PEM BOOT SECTOR FLASH AS29LV016

PIN CONFIGURATION LOGIC SYMBOL

A0–A19 = 20 addresses DQ0–DQ14 = 15 data inputs/outputs 20 DQ15/A-1 = DQ15 (data input/output, word mode), A0–A19 16 or 8 A-1 (LSB address input, byte mode) DQ0–DQ15 BYTE# = Selects 8-bit or 16-bit mode (A-1) CE# = Chip enable OE# = Output enable CE# WE# = Write enable OE# RESET# = Hardware reset pin RY/BY# = Ready/Busy output WE#

VCC = 3.0 volt-only single power supply (see RESET# Product Selector Guide for speed BYTE# RY/BY# options and voltage supply tolerances)

VSS = Device ground NC = Pin not connected internally

CONNECTION DIAGRAMS

44 WE# A15 1 48 A16 A14 2 47 BYTE# A13 3 46 VSS A12 4 45 DQ15/A-1 A11 5 44 DQ7 A10 6 43 DQ14 A9 7 42 DQ6 A8 8 41 DQ13 A19 9 40 DQ5 NC 10 39 DQ12 WE# 11 38 DQ4 RESET# 12 Standard TSOP 37 VCC NC 13 36 DQ11 NC 14 35 DQ3 RY/BY# 15 34 DQ10 A18 16 33 DQ2 A17 17 32 DQ9 A7 18 31 DQ1 A6 19 30 DQ8 A5 20 29 DQ0 A4 21 28 OE# A3 22 27 VSS A2 23 26 CE# A1 24 25 A0

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 4 COTS PEM BOOT SECTOR FLASH AS29LV016

ORDERING INFORMATION AS29LV016TRG-70/ET TOP BOOT TSOP1-48 ENHANCED AS29LV016BRG-70/ET BOTTOM BOOT TSOP1-48 ENHANCED AS29LV016TRG-90/ET TOP BOOT TSOP1-48 ENHANCED AS29LV016BRG-90/ET BOTTOM BOOT TSOP1-48 ENHANCED AS29LV016TRG-90/XT TOP BOOT TSOP1-48 EXTENDED AS29LV016BRG-90/XT BOTTOM BOOT TSOP1-48 EXTENDED AS29LV016TRG-100/ET TOP BOOT TSOP1-48 ENHANCED AS29LV016BRG-100/ET BOTTOM BOOT TSOP1-48 ENHANCED AS29LV016TRG-100/XT TOP BOOT TSOP1-48 EXTENDED AS29LV016BRG-100/XT BOTTOM BOOT TSOP1-48 EXTENDED

PB-FREE OPTION (WHERE AVAILABLE) AS29LV016TRGR-70/ET TOP BOOT TSOP1-48 ENHANCED AS29LV016TRGR-70/ET BOTTOM BOOT TSOP1-48 ENHANCED

TAPE / REEL OPTION (WHERE AVAILABLE) .14-14” Reel (32mm TAPE) .7-7” Reel (32mm TAPE)

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 5 COTS PEM BOOT SECTOR FLASH AS29LV016

DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com-posed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.

Table 1: AS29LV016 Device Bus Operations

DQ8-DQ15 DQ0- BYTE# BYTE# 1 Operation CE# OE# WE# RESET# Address DQ7 =VIH =VIL

Read LLHH AIN DOUT DOUT DQ8-DQ14= High Z,

Write L H L H AIN DIN DIN DQ15=A-1 Standby Vcc ± 0.3V X X Vcc ± 0.3V X High-Z High-Z High-Z Output Disable LHHH X High-Z High-Z High-Z Reset XXXL X High-Z High-Z High-Z

2 Sector Protect LHLVID Sector Address, DIN XX A6=L, A1=H, A0=L

2 Sector Unprotect LHLVID Sector Address, DIN XX A6=H, A1=H, A0=L

Temporary Sector Unprotect X X X VID AIN DIN DIN High-Z

Legend:

L= Logic Low = V IL , H=Logic High=V IH , V ID =12.0±0.5V, X=Don't Care, A IN =Address In, D IN = Data In, D OUT =Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V IH ), A19:A-1 in byte mode (BYTE# = V IL ) 2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection / Unprotection on page 11.

WORD / BYTE CONFIGURATION

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word confi guration. If the BYTE# pin is set at logic 1, the device is in word confi guration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte confi guration, and only data I/O pins DQ0– DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 6 COTS PEM BOOT SECTOR FLASH AS29LV016

REQUIREMENTS FOR READING An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 on page 9 and ARRAY DATA Table 3 on page 10 indicate the address space that To read array data from the outputs, the system must each sector occupies. A “sector address” consists of the drive the CE# and OE# pins to VIL. CE# is the power address bits required to uniquely select a sector. The control and selects the device. OE# is the output control Command Defi nitions on page 17 has details on erasing and gates array data to the output pins. WE# should a sector or the entire chip, or suspending/resuming the remain at VIH. The BYTE# pin determines whether the erase operation. device outputs array data in words or bytes. After the system writes the autoselect command The internal state machine is set for reading array data sequence, the device enters the autoselect mode. upon device power-up, or after a hardware reset. This The system can then read autoselect codes from the ensures that no spurious alteration of the memory content internal register (which is separate from the memory occurs during the power transition. No command is array) on DQ7–DQ0. Standard read cycle timings apply necessary in this mode to obtain array data. Standard in this mode. Refer to Autoselect Mode on page 11 and microprocessor read cycles that assert valid addresses Autoselect Command Sequence on page 17 for more on the device address inputs produce valid data on the information. device data outputs. The device remains enabled for read access until the command register contents are ICC2 in the DC Characteristics table represents the altered. active current specification for the write mode. AC Characteristics on page 29 contains timing specifi cation See Reading Array Data on page 17 for more information. tables and timing diagrams for write operations. Refer to the AC Read Operations on page 29 for timing specifi cations and to Figure 12, on page 29 for the timing diagram. ICC1 in the DC Characteristics table represents PROGRAM AND ERASE the active current specifi cation for reading array data. OPERATION STATUS During an erase or program operation, the system may WRITING COMMANDS / COMMAND check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC SEQUENCES read specifi cations apply. Refer to Write Operation Status To write a command or command sequence (which on page 22 for more information, and to AC Characteristics includes programming data to the device and erasing on page 29 for timing diagrams. sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word Byte Confi guration on page 6 for more information.

The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word Byte Program Command Sequence on page 18 has details on programming data to the device using both standard and Unlock Bypass command sequences.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 7 COTS PEM BOOT SECTOR FLASH AS29LV016

STANDBY MODE RESET#: HARDWARE RESET PIN When the system is not reading or writing to the device, it The RESET# pin provides a hardware method of can place the device in the standby mode. In this mode, resetting the device to reading array data. When the current consumption is greatly reduced, and the outputs system drives the RESET# pin to VIL for at least a period are placed in the high impedance state, independent of of tRP, the device immediately terminates any operation the OE# input. in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# The device enters the CMOS standby mode when the pulse. The device also resets the internal state machine

CE# and RESET# pins are both held at VCC ± 0.3 V. to reading array data. The operation that was interrupted (Note that this is a more restricted voltage range than should be reinitiated once the device is ready to accept

VIH.) If CE# and RESET# are held at VIH, but not within another command sequence, to ensure data integrity.

VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires Current is reduced for the duration of the RESET# standard access time (tCE) for read access when the pulse. When RESET# is held at VSS±0.3 V, the device device is in either of these standby modes, before it is draws CMOS standby current (ICC4). If RESET# is held ready to read data. at VIL but not within VSS±0.3 V, the standby current will be greater. If the device is deselected during erasure or programming, the device draws active current until the operation is The RESET# pin may be tied to the system reset circuitry. completed. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up fi rmware from

ICC3 and ICC4 represents the standby current specifi cation the Flash memory. shown in the table in DC Characteristics on page 27. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the AUTOMATIC SLEEP MODE internal reset operation is complete, which requires a

time of tREADY (during Embedded Algorithms). The system The automatic sleep mode minimizes Flash device can thus monitor RY/BY# to determine whether the reset energy consumption. The device automatically enables operation is complete. If RESET# is asserted when a this mode when addresses remain stable for tACC + 30 ns. program or erase operation is not executing (RY/BY# The automatic sleep mode is independent of the CE#, pin is 1), the reset operation is completed within a time WE#, and OE# control signals. Standard address access of t (not during Embedded Algorithms). The system timings provide new data when addresses are changed. READY can read data tRH after the RESET# pin returns to VIH. While in sleep mode, output data is latched and always Refer to the tables in AC Characteristics on page 29 for available to the system. ICC4 in the DC Characteristics on RESET# parameters and to Figure 13, on page 30 for page 27 represents the automatic sleep mode current the timing diagram. specifi cation.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 8 COTS PEM BOOT SECTOR FLASH AS29LV016

OUTPUT DISABLE MODE

When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2: Sector Address Tables (Top Boot Device)

Sector Size Address Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes / Kwords) Byte Mode (x8) Word Mode (x16) SA0 0 0 0 0 0 X X X 64/32 000000-00FFFF 00000-07FFF SA1 0 0 0 0 1 X X X 64/32 010000-01FFFF 08000-0FFFF SA2 0 0 0 1 0 X X X 64/32 020000-02FFFF 10000-17FFF SA3 0 0 0 1 1 X X X 64/32 030000-03FFFF 18000-1FFFF SA4 0 0 1 0 0 X X X 64/32 040000-04FFFF 20000-27FFF SA5 0 0 1 0 1 X X X 64/32 050000-05FFFF 28000-2FFFF SA6 0 0 1 1 0 X X X 64/32 060000-06FFFF 30000-37FFF SA7 0 0 1 1 1 X X X 64/32 070000-07FFFF 38000-3FFFF SA8 0 1 0 0 0 X X X 64/32 080000-08FFFF 40000-47FFF SA9 0 1 0 0 1 X X X 64/32 090000-09FFFF 48000-4FFFF SA10 0 1 0 1 0 X X X 64/32 0A0000-0AFFFF 50000-57FFF SA11 0 1 0 1 1 X X X 64/32 0B0000-0BFFFF 58000-5FFFF SA12 0 1 1 0 0 X X X 64/32 0C0000-0CFFFF 60000-67FFF SA13 0 1 1 0 1 X X X 64/32 0D0000-0DFFFF 68000-6FFFF SA14 0 1 1 1 0 X X X 64/32 0E0000-0EFFFF 70000-77FFF SA15 0 1 1 1 1 X X X 64/32 0F0000-0FFFFF 78000-7FFFF SA1610000XXX 64/32100000-10FFFF 80000-87FFF SA17 1 0 0 0 1 X X X 64/32 110000-11FFFF 88000-8FFFF SA18 1 0 0 1 0 X X X 64/32 120000-12FFFF 90000-97FFF SA1910011XXX 64/32130000-13FFFF 98000-9FFFF SA2010100XXX 64/32140000-14FFFF A0000-A7FFF SA21 1 0 1 0 1 X X X 64/32 150000-15FFFF A8000-AFFFF SA22 1 0 1 1 0 X X X 64/32 160000-16FFFF B0000-B7FFF SA23 1 0 1 1 1 X X X 64/32 170000-17FFFF B8000-BFFFF SA24 1 1 0 0 0 X X X 64/32 180000-18FFFF C0000-C7FFF SA25 1 1 0 0 1 X X X 64/32 190000-19FFFF C8000-CFFFF SA26 1 1 0 1 0 X X X 64/32 1A0000-1AFFFF D0000-D7FFF SA27 1 1 0 1 1 X X X 64/32 1B0000-1BFFFF D8000-DFFFF SA28 1 1 1 0 0 X X X 64/32 1C0000-1CFFFF E0000-E7FFF SA29 1 1 1 0 1 X X X 64/32 1D0000-1DFFFF E8000-EFFFF SA30 1 1 1 1 0 X X X 64/32 1E0000-1EFFFF F0000-F7FFF SA31 1 1 1 1 1 0 X X 32/16 1F0000-1F7FFF F8000-FBFFF SA3211111100 8/41F8000-1F9FFFFC000-FCFFF SA3311111101 8/41FA000-1FBFFFFD000-FDFFF SA341111111X 16/81FC000-1FFFFFFE000-FFFFF Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 6.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 9 COTS PEM BOOT SECTOR FLASH AS29LV016

Table 3: Sector Address Tables (Bottom Boot Device)

Sector Size Address Range (in hexadecimal) Sector A19 A18 A17 A16 A15 A14 A13 A12 (Kbytes / Kwords) Byte Mode (x8) Word Mode (x16) SA00000000X 16/8000000-003FFF 00000-01FFF SA100000010 8/4004000-005FFF 02000-02FFF SA200000011 8/4006000-007FFF 03000-03FFF SA3000001XX 32/16008000-00FFFF 04000-04FFF SA400001XXX 64/32010000-01FFFF 08000-0FFFF SA500010XXX 64/32020000-02FFFF 10000-17FFF SA600011XXX 64/32030000-03FFFF 18000-1FFFF SA700100XXX 64/32040000-04FFFF 20000-27FFF SA800101XXX 64/32050000-05FFFF 28000-2FFFF SA900110XXX 64/32060000-06FFFF 30000-37FFF SA10 0 0 1 1 1 X X X 64/32 070000-07FFFF 38000-3FFFF SA1101000XXX 64/32080000-08FFFF 40000-47FFF SA1201001XXX 64/32090000-09FFFF48000-4FFFF SA13 0 1 0 1 0 X X X 64/32 0A0000-0AFFFF 50000-57FFF SA1401011XXX 64/320B0000-0BFFFF58000-5FFFF SA1501100XXX 64/32 0C0000-0CFFFF 60000-67FFF SA16 0 1 1 0 1 X X X 64/32 0D0000-0DFFFF 68000-6FFFF SA1701110XXX 64/320E0000-0EFFFF70000-77FFF SA1801111XXX 64/320F0000-0FFFFF78000-7FFFF SA19 1 0 0 0 0 X X X 64/32 100000-10FFFF 80000-87FFF SA2010001XXX 64/32110000-11FFFF88000-8FFFF SA2110010XXX 64/32120000-12FFFF 90000-97FFF SA2210011XXX 64/32130000-13FFFF98000-9FFFF SA2310100XXX 64/32140000-14FFFFA0000-A7FFF SA2410101XXX 64/32150000-15FFFF A8000-AFFFF SA2510110XXX 64/32160000-16FFFF B0000-B7FFF SA26 1 0 1 1 1 X X X 64/32 170000-17FFFF B8000-BFFFF SA2711000XXX 64/32180000-18FFFFC0000-C7FFF SA2811001XXX 64/32190000-19FFFF C8000-CFFFF SA29 1 1 0 1 0 X X X 64/32 1A0000-1AFFFF D0000-D7FFF SA3011011XXX 64/321B0000-1BFFFF D8000-DFFFF SA3111100XXX 64/321C0000-1CFFFF E0000-E7FFF SA32 1 1 1 0 1 X X X 64/32 1D0000-1DFFFF E8000-EFFFF SA3311110XXX 64/321E0000-1EFFFFF0000-F7FFF SA3411111XXX 64/321F0000-1FFFFF F8000-FFFFF Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See Word/Byte Configuration on page 6.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 10 COTS PEM BOOT SECTOR FLASH AS29LV016

AUTOSELECT MODE The autoselect mode provides manufacturer and In addition, when verifying sector protection, the sector device identifi cation, and sector protection verifi cation, address must appear on the appropriate highest order through identifier codes output on DQ7–DQ0. This address bits (see Table 2 on page 9 and Table 3 on mode is primarily intended for programming equipment page 10). Table 4, immediately below, shows the remaining to automatically match a device to be programmed with address bits that are don’t care. When all necessary bits its corresponding programming algorithm. However, have been set as required, the programming equipment the autoselect codes can also be accessed in-system may then read the corresponding identifi er code on through the command register. DQ7-DQ0.

When using programming equipment, the autoselect To access the autoselect codes in-system, the host system can issue the autoselect command via the mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in command register, as shown in Table 9 on page 21. This method does not require VID. See Command Defi nitions on page 17 for details on using the autoselect mode.

Table 4: AS29LV016 Autoselect Codes (High Voltage Method)

A19 to A11 to A8 to A5 to A3 to DQ8 to Description Mode CE# OE# WE# A9 A6 A1 A0 DQ7 to DQ0 A12 A10 A7 A4 A2 DQ15

Manufacturer ID: Spansion LLHXXVID XLXLLLX 01h Device ID: S29AL016D Word L L H X X 22h C4h V XLXLLH (Top Boot Block) Byte L L H X XID X C4h Device ID: S29AL016D Word L L H X X 22h 49h V XLXLLH (Bottom Boot Block) Byte L L H X XID X 49h X 01h (protected) Sector Protection Verification L L H SA X V XLXLHL ID X 00h (unprotected)

L= Logic Low = V IL , H=Logic High=V IH , SA = Sector Address, X=Don't Care Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9 on page 21.

SECTOR PROTECTION / UNPROTECTION

The hardware sector protection feature disables both The primary method requires VID on the RESET# pin program and erase operations in any sector. The only, and can be implemented either in-system or via hardware sector unprotection feature re-enables both programming equipment. Figure 2, on page 13 shows the program and erase operations in previously protected algorithms and Figure 22, on page 36 shows the timing sectors. diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected The device is shipped with all sectors unprotected. sectors must fi rst be protected prior to the fi rst sector unprotect write cycle. It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode above for details. The alternate method intended only for programming

equipment requires VID on address pin A9 and OE#. Sector protection/unprotection can be implemented via two methods.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 11 COTS PEM BOOT SECTOR FLASH AS29LV016

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector

Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the algorithm, and Figure 21, on page 35 shows the timing diagrams, for this feature.

START

RESET# = VID (Note 1)

Perform Erase or Program Operations

RESET# = VIH

Temporary Sector Unprotect Completed (Note 2)

Notes: 1. All protected sectors unprotected. 2. All previously protected sectors are protected once again.

Figure 1. Temporary Sector Unprotect Operation

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 12 COTS PEM BOOT SECTOR FLASH AS29LV016

START START Protect all sectors: PLSCNT = 1 The indicated portion PLSCNT = 1 of the sector protect algorithm must be RESET# = V RESET# = VID ID performed for all unprotected sectors μ Wait 1 μs Wait 1 s prior to issuing the first sector unprotect address No Temporary Sector No First Write First Write Temporary Sector Unprotect Mode Cycle = 60h? Cycle = 60h? Unprotect Mode

Yes Yes

Set up sector No address All sectors protected?

Sector Protect: Yes Write 60h to sector address with Set up first sector A6 = 0, A1 = 1, address A0 = 0

Sector Unprotect: Wait 150 μs Write 60h to sector address with Verify Sector A6 = 1, A1 = 1, Protect: Write 40h A0 = 0 to sector address Reset Increment with A6 = 0, PLSCNT = 1 Wait 15 ms PLSCNT A1 = 1, A0 = 0

Verify Sector Read from Unprotect: Write sector address 40h to sector with A6 = 0, address with A1 = 1, A0 = 0 Increment A6 = 1, A1 = 1, No PLSCNT A0 = 0

No PLSCNT Data = 01h? Read from = 25? sector address with A6 = 1, Yes A1 = 1, A0 = 0 Yes No Set up next sector Yes No address Protect another PLSCNT Device failed Data = 00h? sector? = 1000?

No Yes Yes

Remove VID from RESET# Last sector No Device failed verified? Write reset Yes command

Remove VID from RESET# Sector Protect Sector Protect Sector Unprotect Algorithm complete Algorithm Write reset command

Sector Unprotect complete Figure 2. In-System Sector Protect/Unprotect Algorithms

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 13 COTS PEM BOOT SECTOR FLASH AS29LV016

COMMON FLASH MEMORY INTERFACE (CFI)

The Common Flash Interface (CFI) specifi cation outlines The system can also write the CFI query command when device and host system software interrogation handshake, the device is in the autoselect mode. The device enters which allows specifi c vendor-specifi ed software algorithms the CFI query mode, and the system can read CFI data to be used for entire families of devices. Software at the addresses given in Tables 5–8. The system must support can then be device-independent, JEDEC ID- write the reset command to return the device to the independent, and forward- and backward-compatible autoselect mode. for the specifi ed fl ash device families. Flash vendors can standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5–8. In word mode, the upper address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.

Table 5: CFI Query Identification String

Addresses Addresses (Word Mode) (Byte Mode) Data Description 10h 20h 0051h 11h 22h 0052h Query Unique ASCII String "QRY" 12h 24h 0059h 13h 26h 0002h Primary OEM Command Set 14h 28h 0000h 15h 2Ah 0040h Address for Primary Extended Table 16h 2Ch 0000h 17h 2Eh 0000h Alternate OEM Command Set (00h=none exists) 18h 30h 0000h 19h 32h 0000h Address for Alternate OEM Extended Table (00h=none exists) 1Ah 34h 0000h

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 14 COTS PEM BOOT SECTOR FLASH AS29LV016 Table 6: System Interface String

Addresses Addresses (Word Mode) (Byte Mode) Data Description

1Bh 36h 0027h VCC Min. (write/erase) D7-D4:volt, D3-D0L 100 millivolt

1Ch 38h 0036h VCC Max. (write/erase) D7-D4:volt, D3-D0L 100 millivolt

1Dh 3Ah 0000h VPP Min. voltage (00h=no VPP pin present)

1Eh 3Ch 0000h VPP Max. voltage (00h=no VPP pin present) N 1Fh 3Eh 0004h Typical timeout per single byte/word write 2 μs N 20h 40h 0000h Typical timeout for Min. size buffer write 2 μs (00h=not supported) N 21h 42h 000Ah Typical timeout per individual block erase 2 ms N 22h 44h 0000h Typical timeout for full chip erase 2 ms (00h=not supported) N 23h 46h 0005h Max. timeout for byte/word write 2 times typical N 24h 48h 0000h Max. timeout for buffer write 2 times typical N 25h 4Ah 0004h Max. timeout per individual block erase 2 times typical N 26h 4Ch 0000h Max. timeout for full chip erase 2 times typical (00h=not supported) Table 7: Device Geometry Definition

Addresses Addresses (Word Mode) (Byte Mode) Data Description 27h 4Eh 0015h Device Size = 2N Byte 28h 50h 0002h Flash Device Interface description (refer to CFI publication 100) 29h 52h 0000h 2Ah 54h 0000h Max. number of byte in multi-byte write = 2N (00h= not supported) 2Bh 56h 0000h 2Ch 58h 0004h Number of Erase Block Regions within device 2Dh 5Ah 0000h 2Eh 5Ch 0000h Erase Block Region 1 Information 2Fh 5Eh 0040h (refer to the CFI specification or CFI publication 100) 30h 60h 0000h 31h 62h 0001h 32h 64h 0000h Erase Block Region 2 Information 33h 66h 0020h 34h 68h 0000h 35h 6Ah 0000h 36h 6Ch 0000h Erase Block Region 3 Information 37h 6Eh 0080h 38h 70h 0000h 39h 72h 001Eh 3Ah 74h 0000h Erase Block Region 4 Information 3Bh 76h 0000h 3Ch 78h 0001h

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 15 COTS PEM BOOT SECTOR FLASH AS29LV016

Table 8: Primary Vendor-Specific Extended Query

Addresses Addresses (Word Mode) (Byte Mode) Data Description 40h 80h 0050h 41h 82h 0052h Query-unique ASCII string "PRI" 42h 84h 0049h 43h 86h 0031h Major version number, ASCII 44h 88h 0030h Major version number, ASCII Address Sensitive Unlock 45h 8Ah 0000h 0=Required, 1=Not Required Erase Suspend 46h 8Ch 0002h 0=Not Supported, 1=To Read Only, 2=To Read and Write Sector Protect 47h 8Eh 0001h 0=Not Supported, X=Number of Sectors Per Group Sector Temorary Unprotect 48h 90h 0001h 00=Not Supported, 01=Supported Sector Protect / Unprotect Scheme 49h 92h 0004h 01=29F040 mode, 02=29F016 mode, 03=29F400 mode, 04=29LV800A mode Simultaneous Operation 4Ah 94h 0000h 00=Not Supported, 01=Supported Burst Mode Type 4Bh 96h 0000h 00=Not Supported, 01= Supported Page Mode Type 4Ch 98h 0000h 00=Not Supported, 01=4 Word Page, 02= 8 Word Page

HARDWARE DATA PROTECTION The command sequence requirement of unlock cycles WRITE PULSE GLITCH PROTECTION for programming or erasing provides data protection Noise pulses of less than 5 ns (typical) on OE#, CE# or against inadvertent writes (refer to Table 9 on page 21 for WE# do not initiate a write cycle. command defi nitions). In addition, the following hardware data protection measures prevent accidental erasure LOGICAL INHIBIT or programming, which might otherwise be caused by Write cycles are inhibited by holding any one of OE# spurious system level signals during VCC power-up and = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, power-down transitions, or from system noise. CE# and WE# must be a logical zero while OE# is a logical one.

LOW VCC WRITE INHIBIT

When VCC is less than VLKO, the device does not accept POWER-UP WRITE INHIBIT any write cycles. This protects data during VCC power-up If WE# = CE# = VIL and OE# = VIH during power up, the and power-down. The command register and all internal device does not accept commands on the rising edge of program/erase circuits are disabled, and the device WE#. The internal state machine is automatically reset resets. Subsequent writes are ignored until VCC is greater to reading array data on power-up. than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when

VCC is greater than VLKO. AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 16 COTS PEM BOOT SECTOR FLASH AS29LV016

COMMAND DEFINITIONS Once erasure begins, however, the device ignores reset commands until the operation is complete. Writing specific address and data commands or sequences into the command register initiates device The reset command may be written between the operations. Table 9 on page 21 defi nes the valid register sequence cycles in a program command sequence command sequences. Writing incorrect address and before programming begins. This resets the device to data values or writing them in the improper sequence reading array data (also applies to programming in Erase resets the device to reading array data. Suspend mode). Once programming begins, however, the device ignores reset commands until the operation All addresses are latched on the falling edge of WE# is complete. or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens The reset command may be written between the fi rst. Refer to the appropriate timing diagrams in AC sequence cycles in an autoselect command sequence. Characteristics on page 29. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies READING ARRAY DATA to autoselect during Erase Suspend). The device is automatically set to reading array data after device power-up. No commands are required to If DQ5 goes high during a program or erase operation, retrieve data. The device is also ready to read array data writing the reset command returns the device to reading after completing an Embedded Program or Embedded array data (also applies during Erase Suspend). Erase algorithm. AUTOSELECT COMMAND SEQUENCE After the device accepts an Erase Suspend command, The autoselect command sequence allows the host the device enters the Erase Suspend mode. The system system to access the manufacturer and devices codes, can read array data using the standard read timings, and determine whether or not a sector is protected. except that if it reads at an address within erase- Table 9 on page 21 shows the address and data suspended sectors, the device outputs status data. requirements. This method is an alternative to that shown After completing a programming operation in the Erase in Table 4 on page 11, which is intended for PROM Suspend mode, the system may once again read array programmers and requires VID on address bit A9. data with the same exception. See Erase Suspend/Erase Resume Commands on page 20 for more information The autoselect command sequence is initiated by writing on this mode. two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the The system must issue the reset command to re-enable system may read at any address any number of times, the device for reading array data if DQ5 goes high, or without initiating another command sequence. while in the autoselect mode. See Reset Command, next. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h returns the device See also Requirements for Reading Array Data on code. A read cycle containing a sector address (SA) and page 7 for more information. The Read Operations on the address 02h in word mode (or 04h in byte mode) page 29 provides the read parameters, and Figure 12, returns 01h if that sector is protected, or 00h if it is on page 29 shows the timing diagram. unprotected. Refer to Table 2 on page 9 and Table 3 on page 10 for valid sector addresses. RESET COMMAND Writing the reset command to the device resets the The system must write the reset command to exit the device to reading array data. Address bits are don’t care for this command.

The reset command may be written between the sequence cycles in an erase command sequence before

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 17 COTS PEM BOOT SECTOR FLASH AS29LV016

WORD/BYTE PROGRAM COMMAND This mode dispenses with the initial two unlock cycles SEQUENCE required in the standard program command sequence, The system may program the device by word or byte, resulting in faster total programming time. Table 9 on depending on the state of the BYTE# pin. Programming page 21 shows the requirements for the command is a four-bus-cycle operation. The program command sequence. sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program During the unlock bypass mode, only the Unlock Bypass address and data are written next, which in turn initiate Program and Unlock Bypass Reset commands are valid. the Embedded Program algorithm. The system is not To exit the unlock bypass mode, the system must issue required to provide further controls or timings. The device the two-cycle unlock bypass reset command sequence. automatically generates the program pulses and verifi es The fi rst cycle must contain the data 90h; the second the programmed cell margin. Table 9 on page 21 shows cycle the data 00h. Addresses are don’t care for both the address and data requirements for the byte program cycles. The device then returns to reading array data. command sequence. Figure 3 illustrates the algorithm for the program When the Embedded Program algorithm is complete, the operation. See Erase / Program Operations on page 32 device then returns to reading array data and addresses for parameters, and to Figure 16, on page 33 for timing are no longer latched. The system can determine the diagrams. status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status on page 22 for information on these status bits. START

Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the programming Write Program Command Sequence operation. The Byte Program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. Data Poll from System Programming is allowed in any sequence and across Embedded Program sector boundaries. A bit cannot be programmed from a algorithm 0 back to a 1. Attempting to do so may halt the operation in progress and set DQ5 to 1, or cause the Data# Polling algorithm Verify Data? to indicate the operation was successful. However, a No succeeding read will show that the data is still 0. Only erase operations can convert a 0 to a 1. Yes

UNLOCK BYPASS COMMAND SEQUENCE No Increment Address Last Address? The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock Yes bypass command sequence is initiated by fi rst writing two unlock cycles. This is followed by a third write cycle Programming Completed containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock Note: See Table 9 on page 21 for program command bypass program command sequence is all that is required sequence. to program in this mode. The fi rst cycle in this sequence contains the unlock bypass program command, A0h; the Figure 3. Program Operation second cycle contains the program address and data. Additional data is programmed in the same manner.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 18 COTS PEM BOOT SECTOR FLASH AS29LV016

CHIP ERASE COMMAND SEQUENCE Chip erase is a six bus cycle operation. The chip erase After the command sequence is written, a sector erase command sequence is initiated by writing two unlock time-out of 50 μs begins. During the time-out period, cycles, followed by a set-up command. Two additional additional sector addresses and sector erase commands unlock write cycles are then followed by the chip erase may be written. Loading the sector erase buffer may be command, which in turn invokes the Embedded Erase done in any sequence, and the number of sectors may algorithm. The device does not require the system be from one sector to all sectors. The time between these to preprogram prior to erase. The Embedded Erase additional cycles must be less than 50 μs, otherwise the algorithm automatically preprograms and verifi es the last address and command might not be accepted, and entire memory for an all zero data pattern prior to erasure may begin. It is recommended that processor electrical erase. The system is not required to provide interrupts be disabled during this time to ensure all any controls or timings during these operations. Table 9 commands are accepted. The interrupts can be re- on page 21 shows the address and data requirements enabled after the last Sector Erase command is written. for the chip erase command sequence. If the time between additional sector erase commands can be assumed to be less than 50 μs, the system need Any commands written to the chip during the Embedded not monitor DQ3. Any command other than Sector Erase algorithm are ignored. Note that a hardware reset Erase or Erase Suspend during the time-out period during the chip erase operation immediately terminates resets the device to reading array data. The system the operation. The Chip Erase command sequence must rewrite the command sequence and any additional should be reinitiated once the device has returned to sector addresses and commands. reading array data, to ensure data integrity. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer The system can determine the status of the erase on page 25.) The time-out begins from the rising edge of operation by using DQ7, DQ6, DQ2, or RY/BY#. See the fi nal WE# pulse in the command sequence. Write Operation Status on page 22 for information on these status bits. When the Embedded Erase algorithm Once the sector erase operation has begun, only the is complete, the device returns to reading array data and Erase Suspend command is valid. All other commands addresses are no longer latched. are ignored. Note that a hardware reset during the sector erase operation immediately terminates the Figure 4, on page 20 illustrates the algorithm for the operation. The Sector Erase command sequence should erase operation. See Erase / Program Operations on be reinitiated once the device has returned to reading page 32 for parameters, and Figure 17, on page 33 for array data, to ensure data integrity. timing diagrams. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status SECTOR ERASE COMMAND SEQUENCE of the erase operation by using DQ7, DQ6, DQ2, or RY/ BY#. (Refer to Write Operation Status on page 22 for Sector erase is a six bus cycle operation. The sector information on these status bits.) erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two Figure 4 illustrates the algorithm for the erase operation. addi-tional unlock write cycles are then followed by Refer to Erase / Program Operations on page32 for the address of the sector to be erased, and the sector parameters, and to Figure 17, on page 33 for timing erase command. Table 9 on page 21 shows the address diagrams. and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifi es the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 19 COTS PEM BOOT SECTOR FLASH AS29LV016

ERASE SUSPEND / ERASE RESUME COMMANDS The system must write the Erase Resume command The Erase Suspend command allows the system to (address bits are don’t care) to exit the erase suspend interrupt a sector erase operation and then read data mode and continue the sector erase operation. Further from, or program data to, any sector not selected for writes of the Resume command are ignored. Another erasure. This command is valid only during the sector Erase Suspend command can be written after the device erase operation, including the 50 μs time-out period has resumed erasing. during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. Writing START the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend command. Write Erase When the Erase Suspend command is written during a Command Sequence sector erase operation, the device requires a maximum of 20 μs to suspend the erase operation. However, when the Erase Suspend command is written during the sector Data Poll erase time-out, the device immediately terminates the from System time-out period and suspends the erase operation. Embedded Erase After the erase operation has been suspended, the algorithm system can read array data from or program data to in progress any sector not selected for erasure. (The device “erase No suspends” all sectors selected for erasure.) Normal Data = FFh? read and write timings and command defi nitions apply. Reading at any address within erase-suspended sectors Yes produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Erasure Completed Write Operation Status on page 22 for information on these status bits. After an erase-suspended program operation is complete, the system can once again read array data within non- Notes: suspended sectors. The system can determine the status 1. See Table 9 on page 21 for erase command of the program operation using the DQ7 or DQ6 status sequence. bits, just as in the standard program operation. See Write 2. See DQ3: Sector Erase Timer on page 25 for more Operation Status on page 22 for more information. information. The system may also write the autoselect command sequence when the device is in the Erase Suspend Figure 4. Erase Operation mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on page 17 for more information.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 20 COTS PEM BOOT SECTOR FLASH AS29LV016

TABLE 9: COMMAND DEFINITIONS Bus Cycles2-5 First Second Third Fourth Fifth Sixth 1

Command Sequence Cycles Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read6 1RARD Reset7 1 XXX F0 Word 555 2AA 555 Manufacturer ID 4 AA 55 90 X00 01 Byte AAA 555 AAA Device ID, Word 555 2AA 555 X01 22C4

8 4 AA 55 90 Top Boot Block Byte AAA 555 AAA X02 C4 Device ID, Word 555 2AA 555 X01 2249 4 AA 55 90 Bottom Boot Block Byte AAA 555 AAA X02 49 (SA) XX00 Autoselect Word 555 2AA 555 X02 XX01 Sector Protect Verify9 4 AA 55 90 (SA) 00 Byte AAA 555 AAA X04 01 Word 55 1 98 CFI Query10 Byte AA Word 555 2AA 555 4 AA 55 A0 PA PD Program Byte AAA 555 AAA Word 555 2AA 555 3 AA 55 20 Unlock Bypass Byte AAA 555 AAA Unlock Bypass Program11 2 XXX A0 PA PD Unlock Bypass Reset12 2 XXX 90 XXX F0 Word 555 2AA 555 555 2AA 555 6 AA 55 80 AA 55 10 Chip Erase Byte AAA 555 AAA AAA 555 AAA Word 555 2AA 555 555 2AA 6 AA 55 80 AA 55 SA 30 Sector Erase Byte AAA 555 AAA AAA 555 Erase Suspend13 1 XXX B0 Erase Resume14 1 XXX 30

Legend:

X = Don’t care

RA = Address of the memory location to be read.

RD = Data read from location RA during read operation.

PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.

PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens fi rst.

SA = Address of the sector to be verifi ed (in autoselect mode) or erased. Address bits A19–A12 uniquely select any sector.

Note: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles. 5. Address bits A19–A11 are don’t cares for unlock and command cycles, unless SA or PA required. 6. No unlock or command cycles required when reading array data. 7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 8. The fourth cycle of the autoselect command sequence is a read cycle. 9. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. 10. Command is valid when device is ready to read array data or when device is in autoselect mode. 11. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 12. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode. F0 is also acceptable. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 14. The Erase Resume command is valid only during the Erase Suspend mode.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 21 COTS PEM BOOT SECTOR FLASH AS29LV016

WRITE OPERATION STATUS The device provides several bits to determine the status When the system detects DQ7 has changed from of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/ the complement to true data, it can read valid data at BY#. Table 10 on page 25 and the following subsections DQ7–DQ0 on the following read cycles. This is because describe the functions of these bits. DQ7, RY/BY#, and DQ7 may change asynchronously with DQ0–DQ6 while DQ6 each offer a method for determining whether a Output Enable (OE#) is asserted low. Figure 18, on program or erase operation is complete or in progress. page 34, illustrates this. These three bits are discussed fi rst. Table 10 on page 25 shows the outputs for Data# DQ7: DATA# POLLING Polling on DQ7. Figure 5 below shows the Data# Polling The Data# Polling bit, DQ7, indicates to the host system algorithm. whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend. START Data# Polling is valid after the rising edge of the fi nal WE# pulse in the program or erase command sequence.

Read DQ7–DQ0 During the Embedded Program algorithm, the device Addr = VA outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum DQ7 = Data? Yes programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# No Polling on DQ7 is active for approximately 1 μs, then the No device returns to reading array data. DQ5 = 1?

During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase Yes algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. Read DQ7–DQ0 This is analogous to the complement/true datum output Addr = VA described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The Yes system must provide an address within any of the sectors DQ7 = Data? selected for erasure to read valid status information on DQ7. No

After an erase command sequence is written, if all sectors FAIL PASS selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 μs, then the device Notes: 1. VA = Valid address for programming. During a sector returns to reading array data. If not all selected sectors erase operation, a valid address is an address within are protected, the Embedded Erase algorithm erases the any sector selected for erasure. During chip erase, a unprotected sectors, and ignores the selected sectors valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = 1 because that are protected. DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 22 COTS PEM BOOT SECTOR FLASH AS29LV016

RY/BY#: READY/BUSY# If a program address falls within a protected sector, The RY/BY# is a dedicated, open-drain output pin that DQ6 toggles for approximately 1 μs after the program indicates whether an Embedded Algorithm is in progress command sequence is written, then returns to reading or complete. The RY/BY# status is valid after the rising array data. edge of the fi nal WE# pulse in the command sequence. DQ6 also toggles during the erase-suspend-program Since RY/BY# is an open-drain output, several RY/ mode, and stops toggling once the Embedded Program BY# pins can be tied together in parallel with a pull-up algorithm is complete. resistor to VCC. Table 10 on page 25 shows the outputs for Toggle Bit If the output is low (Busy), the device is actively erasing or I on DQ6. Figure 6, on page 24 shows the toggle bit programming. (This includes programming in the Erase algorithm in fl owchart form, and Reading Toggle Bits Suspend mode.) If the output is high (Ready), the device DQ6/DQ2 on page 24 explains the algorithm. Figure 19, is ready to read array data (including during the Erase on page 34 shows the toggle bit timing diagrams. Figure Suspend mode), or is in the standby mode. 20, on page 5 shows the differences between DQ2 and Table 10 on page 25 shows the outputs for RY/BY#. DQ6 in graphical form. See also the subsection on DQ2: Figures: Figure 12, on page 29, Figure 13, on page 30, Toggle Bit II below. Figure 16, on page 33 and Figure 17, on page 33 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ2: TOGGLE BIT II The “Toggle Bit II” on DQ2, when used with DQ6, DQ6: TOGGLE BIT I indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), Toggle Bit I on DQ6 indicates whether an Embedded or whether that sector is erase-suspended. Toggle Bit II Program or Erase algorithm is in progress or complete, is valid after the rising edge of the fi nal WE# pulse in the or whether the device has entered the Erase Suspend command sequence. mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the fi nal WE# pulse in DQ2 toggles when the system reads at addresses within the command sequence (prior to the program or erase those sectors that have been selected for erasure. operation), and during the sector erase time-out. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the During an Embedded Program or Erase algorithm sector is actively erasing or is erase-suspended. DQ6, operation, successive read cycles to any address cause by comparison, indicates whether the device is actively DQ6 to toggle. (The system may use either OE# or erasing, or is in Erase Suspend, but cannot distinguish CE# to control the read cycles.) When the operation is which sectors are selected for erasure. Thus, both status complete, DQ6 stops toggling. bits are required for sector and mode information. Refer After an erase command sequence is written, if all sectors to Table 10 on page 25 to compare outputs for DQ2 and selected for erasing are protected, DQ6 toggles for DQ6. approximately 100 μs, then returns to reading array data. Figure 6, on page 24 shows the toggle bit algorithm If not all selected sectors are protected, the Embedded in fl owchart form, and the section Reading Toggle Bits Erase algorithm erases the unprotected sectors, and DQ6/DQ2 on page 24 explains the algorithm. See also ignores the selected sectors that are protected. the DQ6: Toggle Bit I subsection. Figure 19, on page The system can use DQ6 and DQ2 together to determine 34 shows the toggle bit timing diagram. Figure 20, on whether a sector is actively erasing or is erase- page 35 shows the differences between DQ2 and DQ6 suspended. When the device is actively erasing (that in graphical form. is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling on page 22). AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 23 COTS PEM BOOT SECTOR FLASH AS29LV016

READING TOGGLE BITS DQ6/DQ2 Refer to Figure 6 for the following discussion. Whenever START the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system Read DQ7–DQ0 would note and store the value of the toggle bit after the fi rst read. After the second read, the system would compare the new value of the toggle bit with the fi rst. If the toggle bit is not toggling, the device has completed Read DQ7–DQ0 (Note 1) the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle.

However, if after the initial two read cycles, the system Toggle Bit No determines that the toggle bit is still toggling, the system = Toggle? also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then Yes determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 No went high. If the toggle bit is no longer toggling, the DQ5 = 1? device has successfully completed the program or erase operation. If it is still toggling, the device did not complete Yes the operation successfully, and the system must write the reset command to return to reading array data. (Notes Read DQ7–DQ0 1,2) Twice The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the Toggle Bit No toggle bit and DQ5 through successive read cycles, = Toggle? determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the Yes beginning of the algorithm when it returns to determine Program/Erase the status of the operation (top of Figure 6). Operation Not Program/Erase Complete, Write Operation Complete Reset Command Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

Figure 6. Toggle Bit Algorithm

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 24 COTS PEM BOOT SECTOR FLASH AS29LV016

DQ5: EXCEEDED TIMING LIMITS After the sector erase command sequence is written, the DQ5 indicates whether the program or erase time has system should read the status on DQ7 (Data# Polling) exceeded a specifi ed internal pulse count limit. Under or DQ6 (Toggle Bit I) to ensure the device has accepted these conditions DQ5 produces a 1. This is a failure the command sequence, and then read DQ3. If DQ3 is 1, condition that indicates the program or erase cycle was the internally controlled erase cycle has begun; all further not successfully completed. commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device The DQ5 failure condition may appear if the system will accept additional sector erase commands. To ensure tries to program a 1 to a location that is previously the command has been accepted, the system software programmed to 0. Only an erase operation can change should check the status of DQ3 prior to and following a 0 back to a 1. Under this condition, the device halts each subsequent sector erase command. If DQ3 is high the operation, and when the operation has exceeded the on the second status check, the last command might timing limits, DQ5 produces a 1. not have been accepted. Table 10 shows the outputs Under both these conditions, the system must issue the for DQ3. reset command to return the device to reading array data.

DQ3: SECTOR ERASE TIMER After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 μs. See also the Sector Erase Command Sequence section on page 19.

Table 10: Write Operation Status

Operation DQ72 DQ6 DQ11 DQ3 DQ22 RY/BY# Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No Toggle 0 Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0 Reading within Erase 1 No Toggle 0 N/A Toggle 1 Erase Suspended Sector Suspend Reading within Non-Erase Data Data Data Data Data 1 Mode Suspended Sector Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0

Notes: 1. DQ5 switches to 1 when and Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See DQ5: Exceeded Timing Limits for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 25 COTS PEM BOOT SECTOR FLASH AS29LV016

ABSOLUTE MAXIMUM RATINGS

Storage Temperature Plastic Packages ...... –65°C to +150°C Ambient Temperature with Power Applied ...... –65°C to +125°C Voltage with Respect to Ground 1 VCC ...... –0.5 V to +4.0 V A9, OE#, and RESET#2...... –0.5 V to +12.5 V 1 All other pins ...... –0.5 V to VCC+0.5 V Output Short Circuit Current3 ...... 200 mA Notes: 1.Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot

VSS to –2.0 V for periods of up to 20 ns. See Figure 7 below. Maximum DC voltage on input or I/O pins is

VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8 below. 2.Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and

RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 7 below. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3.No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING RANGES

Enhanced (/ET) Devices Ambient Temperature (TA)...... -40°C to +105°C

Extended (/XT) Devices Ambient Temperature (TA)...... -55°C to +125°C

VCC Supply Voltages

VCC for standard voltage range...... 2.7 V to 3.6 V Operating ranges defi ne those limits between which the functionality of the device is guaranteed.

20 ns 20 ns 20 ns

+0.8 V VCC +2.0 V –0.5 V VCC +0.5 V –2.0 V 2.0 V

20 ns 20 ns

Figure 7. Maximum Negative Figure 8. Maximum Positive Overshoot Waveform Overshoot Waveform

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 26 COTS PEM BOOT SECTOR FLASH AS29LV016

DC CHARACTERISTICS

CMOS Compatible

Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN=VSS to VCC, VCC=VCCmax ±1.0

ILIT A9 Input Load Current VCC=VCCmax; A9=12.5V 35 μA

ILO Output Leakage Current VOUT=VSS to VCC, VCC=VCCmax ±1.0 10 MHz 15 30 CE#=VIL, OE#-VIH, Byte Mode 5 MHz 9 16 1,2 1 MHz 2 4 ICC1 V Active Read Current mA CC 10 MHz 18 35 CE#=VIL, OE#-VIH, Word Mode 5 MHz 9 16 1 MHz 2 4 2,3,5 ICC2 VCC Active Write Current CE#=VIL, OE#=VIH 20 35 mA 2,4 ICC3 VCC Standby Current CE#, RESET#=VCC ±0.3V 0.2 μA 2,4 ICC4 VCC Standby Current During Reset RESET#=VSS ±0.3V 0.2 5 μA 2,4,6 ICC5 Automatic Sleep Mode VIH=VCC ±0.3V; VIL=VSS ±0.3V 0.2 μA

VIL Input Low Voltage -0.5 0.8

VIH Input High Voltage 0.7 x VCC VCC + 0.3 Voltage for Autoselect and Temporary V V =3.3V 11.5 12.5 ID Sector Unprotect CC V VOL Output Low Voltage IOL=4.0 mA, VCC=VCCmin 0.45

V IOH=-2.0 mA, VCC=VCCmin 2.4 OH1 Output High Voltage VOH2 IOH=-100 μA, VCC=VCCmin VCC-0.4

VLKO Low VCC Lock-Out Voltage 2.3 2.5

Notes:

1.The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.

2.Maximum ICC specifi cations are tested with VCC = VCCmax.

3.ICC active while Embedded Erase or Embedded Program is in progress. 4.At extended temperature range (>+85°C), typical current is 5 μA and maximum current is 10 μA.

5.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6.Not 100% tested.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 27 COTS PEM BOOT SECTOR FLASH AS29LV016

TEST CONDITIONS

3.3 V

2.7 k: Device Under Test

CL 6.2 k:

Note: Diodes are IN3064 or equivalent

Figure 10. Test Setup

Table 11: Test Specifications

Test Condition 70 90 100 Unit Output Load 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 100 100 pF Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0 or VCC

Input timing measurement reference levels 0.5 VCC V

Output timing meausrement reference levels 0.5 VCC

Key to Switching Waveforms

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

VCC Input 0.5 VCC Measurement Level 0.5 VCC Output 0.0 V

Figure 11. Input Waveforms and Measurement Levels

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 28 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

Read Operations

Parameter Speed Options JEDEC Std Description Test Setup 70 90 100 Unit 1 tAVAV tRC Read Cycle Time Min 70 90 100

CE#=VIL, tAVQV tACC Address to Output Delay Max 70 90 100 OE#=VIL

tELQV tCE Chip Enable to Output Delay OE#=VIL Max 70 90 100

tGLQV tOE Output Enable to Output Delay Max 30 35 40

1 tEHQZ tDF Chip Enable to Ouput High Z Max 25 30 35 ns 1 tGHQZ tDF Output Enable to Output High Z Max 25 30 35

tSR/W Latency Between Read and Write Operations Min 20

Output Enable Read Min 0 tOEH 1 Hold Time Toggle and Data# Polling Min 10 Output Hold Time From Addresses, CE# or t t Min 0 AXQX OH OE#, Whichever Occurs First1

Notes: 1. Not 100% Tested 2. See Figure 10, on page 28 and Table 11 on page 28 for test specifications.

Addresses Addresses Stable

tACC CE#

tDF t OE# OE

tOEH

WE# tCE t SR/W tOH HIGH Z HIGH Z Outputs Output Valid

RESET#

RY/BY# 0 V

Figure 12. Read Operations Timings

S29LV016 Rev.1.0 05/06

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 29 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS Hardware Reset (RESET#)

Parameter JEDEC Std Description Test Setup All Speed Options Unit RESET# Pin Low (During Embedded Algorithms) t Max 20 μs READY to Read or Write 1 RESET# Pin Low (NOT During Embedded t Max 500 READY Algorithms) to Read or Write 1 ns tRP RESET# Pulse Width 500 t RESET# High Time Before Read1 50 RH Min tRPD RESET# Low to Standby Mode 20 μs

tRB RY/BY# Recovery Time 0ns

Note: 1. Not 100% Tested

RY/BY#

CE#, OE#

tRH

RESET#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

Reset Timings during Embedded Algorithms

tReady RY/BY#

tRB

CE#, OE#

RESET#

tRP

Figure 13. RESET# Timings

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 30 COTS PEM BOOT SECTOR FLASH AS29LV016 AC CHARACTERISTICS

Word / Byte Configuration (BYTE#)

Parameter Speed Options JEDEC StdDescription Test Setup 70 90 100 Unit

tELFL / tELFH CE# to BYTE# Switching Low or High Max 5

tFLQZ BYTE# Switching Low to Output HIGH Z Max 25 30 35 ns

tFHQV BYTE# Switching High to Output Active Min 70 90 100

OE#

BYTE#

tELFL BYTE# DQ0–DQ14 Data Output Data Output Switching (DQ0–DQ14) (DQ0–DQ7) from word to byte mode DQ15/A-1 DQ15 Address Output Input

tFLQZ

tELFH BYTE#

BYTE# Switching from byte DQ0–DQ14 Data Output Data Output to word (DQ0–DQ7) (DQ0–DQ14) mode DQ15/A-1 Address DQ15 Input Output

t FHQV Figure 14. BYTE# Timings for Read Operations

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 31 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

CE#

The falling edge of the last W WE#

BYTE# tSET (tAS) tHOLD (tAH)

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 15. BYTE# Timings for Write Operations

Erase / Program Operations

Parameter Speed Options JEDEC Std Description Test Setup 70 90 100 Unit 1 tAVAV tWC Write Cycle Time 70 90 100

tAVWL tAS Address Setup Time 0

tWLAX tAH Address Hold Time 45

tDVWH tDS Data Setup Time 35 45 55

tWHDX tDH Data Hold Time 0

tOES Output Enagle Setup Time 0 Read Recovery Time Before Write, Min ns t t 0 GHWL GHWL (OE# High to WE# Low)

tELWL tCS CE# Setup Time 0

tWHEH tCH CE# Hold Time 0

tWLWH tWP Write Pulse Width 35

tWHWL tWPH Write Pulse Width High 30

tSR/W Latency Between Read and Write Operations 20

2 Byte 5 tWHWH1 tWHWH1 Programming Operation μs Word Typ 7 2 tWHWH2 tWHWH2 Sector Erase Operation 0.7 sec t V Setup Time1 50 μs VCS CC Min t Recovery Time from RY / BY# 0 RB ns tBUSY Program / Erase Valid to RY / BY# Delay Max 90

Notes: 1. Not 100% Tested. 2. See Erase and Programming Performance on page 38 for more information.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 32 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

Program Command Sequence (last two cycles) Read Status Data (last two cycles)

tWC tAS Addresses 555h PAPA PA

tAH

CE# tCH OE# t tWP WHWH1

WE# tWPH tCS tDS tDH

Data A0h PD Status DOUT

tBUSY tRB

RY/BY#

tVCS

VCC

Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode. Figure 16. Program Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

tWC tAS Addresses 2AAh SA VA VA 555h for chip erase tAH CE#

OE# tCH

tWP WE# tWPH tWHWH2 tCS tDS tDH In Data 55h 30h Progress Complete 10 for Chip Erase

tBUSY tRB

RY/BY#

tVCS

VCC

Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 31). Notes: 2. Illustration shows device in word mode. 1.SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 22). Figure 17. Chip/Sector Erase Operation Timings 2.Illustration shows device in word mode.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 33 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

tRC Addresses VA VA VA

tACC

tCE CE#

tCH tOE OE#

tOEH tDF WE#

tOH High Z DQ7 Complement Complement True Valid Data

High Z DQ0–DQ6 Status Data Status Data True Valid Data

tBUSY RY/BY#

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. Figure 18. Data# Polling Timings (During Embedded Algorithms)

tRC Addresses VA VA VA VA

tACC

tCE CE#

tCH tOE OE# tOEH tDF WE#

tOH High Z DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data (first read) (second read) (stops toggling) tBUSY RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. Figure 19. Toggle Bit Timings (During Embedded Algorithms)

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 34 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS Enter Embedded Erase Enter Erase Erase Erasing Suspend Suspend Program Resume

WE# Erase Erase Suspend Erase Erase Suspend Erase Erase Read Suspend Read Complete Program

DQ6

DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 20. DQ2 vs. DQ6 for Erase and Erase Suspend Operations

Temporary Sector Unprotect

Parameter JEDEC Std Description Test Setup All Speed Options Unit 1 tVIDR VID Rise and Fall Time Min 500 ns

tRSP RESET# Setup Time for Temporary Sector Unprotect Min 4 μs

Note: 1. Not 100% Tested.

RESET# 0 or 3 V

tVIDR tVIDR Program or Erase Command Sequence

CE#

WE#

tRSP

RY/BY#

Figure 21. Temporary Sector Unprotect/Timing Diagram

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 35 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

VID

VIH RESET#

SA, A6, Valid* Valid* Valid* A1, A0 Sector Protect/Unprotect Verify

Data 60h 60h 40h Status

Sector Protect: 150 μs 1 μs Sector Unprotect: 15 ms

CE#

WE#

OE#

Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 22. Sector Protect/Unprotect Timing Diagram

Alternate CE# Controlled Erase / Program Operations

Parameter Speed Options JEDEC Std Description Test Setup 70 90 100 Unit 1 tAVAV tWC Write Cycle Time 70 90 100

tAVEL tAS Address Setup Time 0

tELAX tAH Address Hold Time 45 45 55

tDVEH tDS Data Setup Time 35 45 55

tEHDX tDH Data Hold Time 0

tOES Output Enagle Setup Time 0 Read Recovery Time Before Write, Min ns t t 0 GHEL GHEL (OE# High to OE# Low)

tWLEL tWS WE# Setup Time 0

tEHWH tWH WE# Hold Time 0

tELEH tCP CE# Pulse Width 35 35 40

tEHEL tCPH CE# Pulse Width High 30

tSR/W Latency Between Read and Write Operations 20

2 Byte 5 tWHWH1 Programming Operation μs tWHWH1 Word Typ 7 2 tWHWH2 tWHWH2 Sector Erase Operation 0.7 sec

Notes: 1. Not 100% Tested. 2. See Erase and Programming Performance on page 38 for more information.

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 36 COTS PEM BOOT SECTOR FLASH AS29LV016

AC CHARACTERISTICS

555 for program PA for program 2AA for erase SA for sector erase 555 for chip erase Data# Polling

Addresses PA

tWC tAS tAH

tWH WE#

tGHEL OE# t tCP WHWH1 or 2

CE# tWS tCPH tBUSY tDS

tDH DQ7# D Data OUT

tRH A0 for program PD for program 55 for erase 30 for sector erase 10 for chip erase RESET#

RY/BY#

Notes: 1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device. 2. Figure indicates the last two bus cycles of the command sequence. 3. Word mode address used as an example.

Figure 23. Alternate CE# Controlled Write Operation Timings

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 37 COTS PEM BOOT SECTOR FLASH AS29LV016

ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ1 Max2 Unit Comments Sector Erase Time 0.7 10 s Excludes 00h programming Chip Erase Time 25 s prior to erasure4 Byte Programming Time 7210μs Word Programming Time 7210μs Excludes system level Byte Mode 11 33 s overhead5 Chip Programming Time3 Word Mode 7.2 21.6 s

Notes:

1.Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.

2.Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3.The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4.In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5.System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 on page 21 for further information on command defi nitions. 6.The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.

TSOP, SO AND BGA PIN CAPACITANCE

Parameter Symbol Parameter Description Test Setup Package Typ Max Unit

CIN Input Capacitance VIN=0 TSOP, SO 6 7.5 pF

COUT Output Capacitance VOUT=0 TSOP, SO 8.5 12 pF

CIN2 Control Pin Capacitance VIN=0 TSOP, SO 7.5 9 pF

Notes: 1. Samples, not 100% tested. o 2. Test conditions T A =25 C, f=1.0 MHz

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 38 COTS PEM BOOT SECTOR FLASH AS29LV016 PHYSICAL DIMENSIONS

TS 048—48-Pin Standard TSOP 2X STANDARD PIN OUT (TOP VIEW) 0.10 2X (N/2 TIPS) 2X 2 0.10 0.10 A2 1 N REVERSE PIN OUT (TOP VIEW)

ABSEE DETAIL B 3 1 N E 5

N N +1 e 2 2 5 9 D1 N 4 A1 N +1 D 2 2 0.25 B C 2X (N/2 TIPS) SEATING A PLANE B SEE DETAIL A 0.08MM (0.0031") M C A - B S

b 6 7 WITH PLATING

7 (c) c1

b1 BASE METAL SECTION B-B R

(c) e/2 GAUGE PLANE

θ° 0.25MM (0.0098") BSC PARALLEL TO C X SEATING PLANE L X = A OR B DETAIL A DETAIL B

NOTES: CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). Jedec MO-142 (D) DD 1 (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982) Symbol MIN NOM MAX 2 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP). A 1.20 A1 0.05 0.15 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. A2 0.95 1.00 1.05 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF b1 0.17 0.20 0.23 CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT b 0.17 0.22 0.27 HORIZONTAL SURFACE. c1 0.10 0.16 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS c 0.10 0.21 0.15mm (.0059") PER SIDE. D 19.80 20.00 20.20 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE D1 18.30 18.40 18.50 0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE E 11.90 12.00 12.10 BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028"). e 0.50 BASIC 7 THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND L 0.50 0.60 0.70 0.25MM (0.0098") FROM THE LEAD TIP. 0 0˚ 8˚ 8 LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE. R 0.08 0.20 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. N 48 3355 \ 16 038 10

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 39 COTS PEM BOOT SECTOR FLASH AS29LV016

DOCUMENT TITLE 16 Megabit (2M x 8-Bit / 1M x 16-Bit), CMOS 3.0 Volt-Only Boot Sector Flash Memory

REVISION HISTORY Rev # History Release Date Status 2.1 Added Pb-Free & Tape & Reel Option October 2008 Release 2.2 Added Micross information January 2010 Release

AS29LV016 Micross Components reserves the right to change products or specifi cations without notice. Rev. 2.2 01/10 40