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Remote Radio Heads and the Evolution Towards 4G Networks

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Remote Radio Heads and the Evolution Towards 4G Networks Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II processor instruction set. TD-SCDMA rCFR rCPRI rQRD-RLS core for polynomial DPD rDPD t6TJOHDVTUPNJOTUSVDUJPOT ZPVDBOSFEVDFB complex sequence of standard instructions to a rCORDIC reference design rRF hardware board single instruction implemented in hardware. WiMAX rMulti-antenna WiMAX DUC/DDC rOBSAI RP3-01 LTE rCFR for OFDM systems rCPRI tѮF/JPT**DPOêHVSBUJPOXJ[BSE QBSUPG Quartus II so!ware’s SOPC Builder, provides a rQRD-RLS core for polynomial DPD rDPD (6*VTFEUPBEEVQUPDVTUPNJOTUSVDUJPOT rCORDIC reference design rRF hardware board to the Nios II processor, including "oating point operations. t Alternatively, hardware accelerators can also be created using the C-to-Hardware (C2H) DSP Builder Advanced Blockset tool acceleration compiler included in the Nios II 8JUIUIF%41#VJMEFSGFBUVSFPG2VBSUVT¡**EFTJHOTPѫXBSF ZPV &NCFEEFE%FTJHO4VJUF have a synthesis tool that quickly implements Simulink designs in high-performance FPGA platforms. An enhancement to this GFBUVSF UIF%41#VJMEFS"EWBODFE#MPDLTFUMJCSBSZ QSPWJEFTB Want to dig deeper? number of new Simulink blocksets that further increase produc- For more information about how Altera’s 40-nm tivity, particularly for the synthesis of multi-channel designs. transceiver device portfolio can support your You’ll also have a unique synthesis technology that optimizes the RRH applications, contact your local sales high-level, unregistered netlist into a pipelined register transfer SFQSFTFOUBUJWFPS'"& PSWJTJUwww.altera.com/ level (RTL) targeted and optimized to your chosen device and wireless. desired clock rate. Altera Corporation Altera European Headquarters Altera Japa Ltd. Altera International Ltd. 101 Innovation Drive Holmers Farm Way Shinjuku i-Land Tower 32F Unit 11- 18, 9/F San Jose, CA 95134 High Wycombe 6-5-1, Nishi-Shinjuku Millennium City 1, Tower 1 USA Buckinghamshire Shinjuku-ku, Tokyo 163-1332 388 Kwun Tong Road Telephone: (408) 544-7000 HP12 4XF Japan Kwun Tong www.altera.com United Kingdom Telephone: (81) 3 3340 9480 Kowloon, Hong Kong Telephone: (44) 1494 602000 www.altera.co.jp Telephone: (852) 2 945 7000 www.altera.com.cn $PQZSJHIU¥"MUFSB$PSQPSBUJPO"MMSJHIUTSFTFSWFE"MUFSB ѮF1SPHSBNNBCMF4PMVUJPOT$PNQBOZ UIFTUZMJ[FE"MUFSBMPHP TQFDJêDEFWJDFEFTJHOBUJPOT BOEBMMPUIFSXPSET BOEMPHPTUIBUBSFJEFOUJêFEBTUSBEFNBSLTBOEPSTFSWJDFNBSLTBSF VOMFTTOPUFEPUIFSXJTF UIFUSBEFNBSLTBOETFSWJDFNBSLTPG"MUFSB$PSQPSBUJPOJOUIF64BOEPUIFSDPVO- USJFT"MMPUIFSQSPEVDUPSTFSWJDFOBNFTBSFUIFQSPQFSUZPGUIFJSSFTQFDUJWFIPMEFST"MUFSBQSPEVDUTBSFQSPUFDUFEVOEFSOVNFSPVT64BOEGPSFJHOQBUFOUTBOEQFOEJOHBQQMJDB- UJPOT NBTLXPSLSJHIUT BOEDPQZSJHIUT"MUFSBXBSSBOUTQFSGPSNBODFPGJUTTFNJDPOEVDUPSQSPEVDUTUPDVSSFOUTQFDJêDBUJPOTJOBDDPSEBODFXJUI"MUFSBTTUBOEBSEXBSSBOUZ CVU reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any JOGPSNBUJPO QSPEVDU PSTFSWJDFEFTDSJCFEIFSFJOFYDFQUBTFYQSFTTMZBHSFFEUPJOXSJUJOHCZ"MUFSB"MUFSBDVTUPNFSTBSFBEWJTFEUPPCUBJOUIFMBUFTUWFSTJPOPGEFWJDFTQFDJêDBUJPOT Remote Radio Heads and the evolution towards CFGPSFSFMZJOHPOBOZQVCMJTIFEJOGPSNBUJPOBOECFGPSFQMBDJOHPSEFSTGPSQSPEVDUTPSTFSWJDFT%FDFNCFS SS-01050-1.0 4G networks Christian F. Lanzani,∗ Georgios Kardaras,† Deepak Boppana‡ Abstract ::;<%:(("(> ::;<%,"??%@(=)' ::;<%5(8$*%.(=)' Distributed base stations with remote radio head (RRH) capability greatly help mobile operators to resolve cost, performance, and efficiency challenges when deploying new base stations on the road to fully developed 4G networks. Multi-mode radios capable of operating according to GSM, HSPA, LTE, and WiMAX standards and advanced software config- urability are key features in the deployment of more flexible and energy-efficient radio networks. This white ,-./0%(*% paper describes the key market and technology require- !"#$%&'"!()%&$*+$* 1233%456%7$'8(*9 ments for RRHs and how Radiocomps state-of-the-art WiMAX/LTE RRH and intellectual property (IP) core A!&/B%(*%C3:B%*"'$#%=>%'(%1<DEF%.G># solutions, combined with latest FPGA technology from A>!H"?%!G$*#%=>%'(%FD%9@ Altera, helps design compact, green, and full-featured &("8"*$%H()!I=*"G?$%A!&/BLC3:B%G-'%*"'$ applications for mobile network solutions. &("8"*$%H()!I=*"G?$%HJ"))$?%G")K8-K'J Keywords: LTE, WiMAX, Remote Radio Head, OB- SAI, CPRI, CFR, DPD, DSP, SRC, Radiocomp ApS, Altera, Figure 1: Distributed Wireless Base Station system. StratixIV GX, ArriaII GX, DTU, FPGA. ure 1) have evolved in parallel with the evolution of INTRODUCTION the standards to provide a flexible, cheaper, and more scalable modular environment for managing the radio Wireless and mobile network operators face the con- access evolution. For example, the Open Base Station tinuing challenge of building networks that effectively Architecture Initiative (OBSAI) and the Common Pub- manage high data-traffic growth rates. Mobility and lic Radio Interface (CPRI) standards introduced stan- an increased level of multimedia content for end users dardized interfaces separating the Base Station server require end-to-end network adaptations that support and the remote radio head (RRH) part of a base station both new services and the increased demand for broad- by an optical fiber. band and flat-rate Internet access. In addition, net- work operators must consider the most cost-effective evolution of the networks towards 4G. Wireless and mo- II - RRH SYSTEM REQUIREMENTS bile technology standards are evolving towards higher bandwidth requirements for both peak rates and cell- The RRH concept constitutes a fundamental part of a throughput growth. The latest standards supporting state-of-the-art base station architecture. RRH-based this are HSPA+, WiMAX, and LTE. system implementation is driven by the need to reduce The network upgrades required to deploy networks both CAPEX and OPEX consistently, which allows a based on these standards must balance the limited more optimized, energy-efficient, and greener base de- availability of new spectrum, leverage existing spec- ployment. Figure 2 illustrates an architecture where trum, and ensure operation of all desired standards. a 2G/3G/4G base station is connected to RRHs over This all must take place at the same time during the optical fibers. Either CPRI or OBSAI may be used to transition phase, which usually spans many years. Dis- carry RF data to the RRH to cover a three-sector cell. tributed open base station architecture concepts (Fig- The RRH incorporates a large number of digital in- terfacing and processing functions as depicted in Fig- ∗email: [email protected], www.radiocomp.com †email: [email protected], www.radiocomp.com ure 3. It also includes high-performance, efficient, and ‡email: [email protected], www.altera.com frequency-agile analog functions, all packaged into a 1 Choosing the right device Comparing devices Our 40-nm FPGA and ASICs with transceivers portfolio provides Device Arria II GX Stratix IV GX and a number of options for performance, densities, transceiver requirements FPGA HardCopy IV GX channels, power, and more. #e portfolio includes: devices CPRI/OBSAI line Up to 3.75 Up to 8.5 Gbps Stratix IV GX FPGAs, which feature up to 530K logic elements, rates Gbps 1,288 18x18 multipliers, and 48 full-duplex clock data recovery- Number of transmit Up to 2 Up to 4 $%3 CBTFEUSBOTDFJWFSTBUVQUP(CQT processing chains (DUC+CFR+DPD) HardCopy IV GX ASICs, which feature an equivalent transceiver Number of sectors 1 Up to 3 block and package- and pin-compatibility to Stratix IV GX FPGAs processing to help you achieve the lowest risk and lowest total cost in ASIC designs with embedded transceivers. Arria II GX FPGAs, a low-power, cost-e$ective FPGA family that Nios II embedded soft processor makes using transceivers for applications up to 3.75 Gbps easy. You can use Altera’s Nios II so! processor to JNQMFNFOUUIF%1%BEBQUBUJPOBMHPSJUINJO so!ware while also handling all the operation and maintenance functionality for the RRH. RF/RRH reference designs Standard Altera reference designs Partner solutions t Time-critical so!ware algorithms can be accelerated by adding custom instructions to WCDMA rSingle and multi-antenna DUC/DDC rOBSAI RP3-01 the Nios II
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