Received: July 2, 2019 37

A Practical Implementation of Emulator Circuit Based on Operational Transconductance

Apichata Thongrak1* Suchada Sitjongsataporn2 Sanya Khunkhao3 Phichet Moungnoul1

1 Faculty of Engineering, King Mongkut's Institute of Technology Ladkrabang 1 Chalongkrung Rd., Ladkrabang, Bangkok 10520 Thailand 2Department of Electronic Engineering, Faculty of Engineering, Mahanakorn University of Technology 140 Cheumsamphan Rd., Nongchok, Bangkok 10530 Thailand 3Faculty of Engineering, Rajamangala University of Technology Phra Nakhon 1381 Pracharat 1 Road, Wongsawang Subdistrict, Bang Sue District, Bangkok 10800 * Corresponding author’s Email: [email protected]

Abstract: As described of electrical circuit have been considering that there are three fundamental passive two- terminal circuit elements; , , and respectively. In 1971, Prof. L. Chua proposed and described memristor which defines the relationship between magnetic flux and charge. This paper are purposed a memristor emulator circuit based on operational transconductance amplifiers (OTAs). The proposed circuits can be realized using commercially integrated circuits OTA, op amp as AD844, TL084, inductor, capacitor and . The characteristic of memristor emulators can be examined in a practical experiment with the active and passive components. As described, the results could be demonstrated with the memristor circuit application. Furthermore, OTA is used to realize electronically tunable current conveyors emulator circuit. As a result of simulation, the decremental and incremental memristor emulator circuit is suitable for connecting in a series circuit. It was found that the frequency-dependent pinched hysteresis loop of proposed memristor emulator circuits can be updated by changing the value of capacitance and resistance, besides it increases the current gain of current conveyor. In addition to the expected results of memristor (RM), Memcapacitor (CM) and meminductor (LM) are proposed to determine in time-domain characteristics of R-L-C mode circuits. The results of experimental are discussed of phenomena studies by the memory characteristics. Keywords: Memristor, Emulator circuit, Operational transconductance (OTA).

(DDCCs) have been proposed in [7] using 1. Introduction memristor emulator circuit using two CFOAs, one OTA, three resistors and two . A multiple- Recently, the are purposed in form of memory-resistor and memristive devices that were output OTA (MO-OTA) has been used to realize presumed to exist when the link was made to voltage- either decremental or incremental memristor polarity-dependent. The formulation of a memristor was emulator circuits in [8]. first devised in 1971 by Chua [1] as a fourth circuit on Memristors offer a nonvolatile memory storage passive elements such as R, L and C respectively. A with simple device structure as detailed in [9, 10] number of memristor applications has been rapidly including the artificial neural networks as synaptic reported for digital logic circuits in [2-4] and neural weights with a pulse based memristor circuit [2], networks in [5, 6]. memristor XOR gate for resistive multiplier [3] and The memristor emulator circuits based on phase shift keying modulators based memristor [4]. CMOS differential difference current conveyors

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

Received: July 2, 2019 38

Table 1. Comparison of the proposed circuit with those of some previous works Circuits No. of active components No. of passive components Decremental/Incremental 1-EDDCC Proposed circuit (3-LM13600), 2-R, 1-C Decremental Fig. 5 1-AD633 1-EDDCC Fig. 6 (3-LM13600), 2-R, 1-C Incremental 1-AD633 Ref. [16] (2017) 1-CCTA 3-R, 1-C, 1-SW Both Ref. [17] (2017) 1-DVCCTA 3-R, 1-C, 1-SW Both Ref. [18] (2018) 7-MOS 1-C Decremental 3-ECCII (6-LM13600), Ref. [19] (2015) 1-R, 1-C Decremental 1-AD633

Many types of mixed-mode circuits have V been studied such as differential voltage current

Resistor Capacitor =

conveyors (DVCCs), second-generation current dvRdi=  dqCdv= d vdt conveyors (CCIIs), current controlled current i dqidt= q conveyors (CCCIIs), DDCCs and OTAs [11].

Based on the light-dependent resistor (LDR), a Inductor Memristor memcapacitor emulator has been presented dLdi = dMdq =  using RM-CM converter and a method is used to Memristor systems satisfy a LDR memristor-based meminductor- Figure.1 Four fundamental two-terminal circuit elements: equivalent circuit detailed in [12]. resistor, capacitor, inductor and memristor [22] The modern active devices have been used to realize memristor emulator circuits such as current This paper is organized as follows. The conveyor transconductance amplifier (CCTA) in definitions and concept of memristor model is [16], differential voltage current conveyor introduced in Section 2 and Section 3 is described transconductance amplifier (DVCCTA) in [17]. The about OTA-based ECCII. We present an OTA-based circuits in [17] provide decremental and incremental EDDCC memristor emulator that is similar to that of memristor emulators into one circuit by selecting the a memristor shown in Section 4. Experimental . The circuit in [16] is simulated using CMOS results and conclusion are given in Section 5 and 6, implementation of CCTA while the circuit in [17] is respectively. simulated using CMOS implementation of DVCCTA whereas experiment tests, these circuits 2. Memristor model have been built using commercially available ICs AD844 and CA3080. The circuit in [18] realizes Following [13], there are four fundamental memristor emulator circuit based on MOSFET-C. circuit variables: electric current i, voltage v, charge The comparison of proposed circuits with those q and magnetic flux  described in Fig.1. The previous works are summarized in Table 1. memristor, with memristance M-provides a Compared with [16-18], the proposed circuits can be functional relation between charge and flux, pushed the operating of high frequency by d=Mdq. Basic mathematical definition of a capacitance, resistance and current gain of current current-controlled memristor for circuit analysis is 푑푤 conveyor, compared with [16, 18, 19], the proposed given by 푣 = 푅(푤)푖 and (i), where w is the state circuits in Figs. 5 and 6 provide decremental and 푑푡 variable and R is a generalized resistance. incremental memristor emulators into single circuit The concept of memristive systems is described and compared with [16, 17], the proposed circuits 푑푤 as 푣 = 푅(푤, 푖) and (푖) where 푓 is function of can be tested both simulation and experiment with 푑푡 the same active and passive components. time. In this paper, we introduce a compact circuit A thin semiconductor film of thickness D model and physical hardware emulation for sandwiched between two metal contacts is memristor using the electronically tunable considered in Fig. 2. The total resistance is assigned differential different current conveyor (EDDCC). with 2-variable resistors connected in series, where The hardware emulator will demonstrate the resistances are given for the full length D of the experimentally memristor dynamics. International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

Received: July 2, 2019 39

I V1 o A g V W m

Doped Undoped V 2 D Figure. 3 Circuit symbol of OTA (a) Undoped : ECCII Iy Iz1

Roff Doped : Vy y z1 Vz1 W W Ron R off R D on D (b) Vx x z2 Vz2 Figure.2 Coupled variable-resistor model for a memristor: Ix Iz2 (a) structure and symbol of the memristor and (b) Figure.4 Symbol of ECCII diagram with a simplified equivalent circuit ECCII device. However, the semiconductor film has a Iy y OTA3 region with a high concentration of dopants having I Vy gm1 z1 low resistance Ron. The remainder closes to gm3 z1 essentially zero dopant concentration with higher OTA1 I resistance Roff. An external bias v(t) across the z2 g g device will move the boundary between the two m2 Vs m4 z2 regions causing the charged dopants to drift, we get OTA 2 OTA4

푤(푖) 푤(푖) x Vx 푣(푡) = {푅표푛 + 푅표푓푓 (1 − )} 푖(푡) (1) 퐷 퐷 Ix R

푑푤(푡) 푅 Figure. 5 OTA implementation for ECCII = 휇 표푛 푖(푡) (2) 푑푡 퐷 The symbol of the ECCII is shown in Fig. 4 and w(t) is given as and its ideal characteristics can be described by

푅 푤(푡) = 휇 표푛 푞(푡) (3) 퐼푦 0 0 0 퐼푦 푣 퐷 [푉푥] = [1 0 0] [푉푥] (5) 퐼푧 0 ∓푘 0 퐼푧 By substituting Eq. (3) into Eq. (1), the memristance for RON = ROFF can be expressed as ECCII has a unity voltage gain between 휇 푅 terminals y and x and has current gain k between 푀(푔) = 푅 (1 − 푣 표푛) 푞(푡) (4) 표푓푓 퐷2 terminals z and z. OTA implementation for ECCII can be shown in Fig. 5. Using nodal analysis, the where the term of q-dependent is the crucial support relation between Vx and Vy can be expressed as to the memristance. It becomes larger with higher dopant mobilities µV and smaller semiconductor 푔푚1푔푚2훾푖푛푅 푉푥 = 푉푦 (6) film thicknesses D, respectively. 1+푔푚1푔푚2훾푖푛푅

3. OTA-based electronically tunable second- where gm1 and gm2 are respectively the generation current conveyor (ECCII) transconductance gains of OTA1 and OTA2, R is the given resistor and rin is the small-signal input OTA is important active device that has been resistance of OTA2. used to realize both voltage- and current-mode analog circuits. OTA-based circuits can be tested 4. OTA-based electronically tunable both simulation and breadboard experiment. Symbol differential different current conveyor of OTA is shown in Fig.3. The ideal OTA is (EDDCC) described by 퐼0 = 푔푚(푉1 − 푉2) , where is the output The part relationship of EDDCC is shown in Fig. current, gm is the transconductance gain, V1 and V2 6 which is given as denote respectively the non-inverting and inverting input voltages. The transconductance gm of OTA can be controlled using external bias current.

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

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EDDCC From Fig. 7, we assume the current Ix is equal IZ1 to output current of OTA3 which is given as VY3 Y3 z1 VZ1

VY2 Y2 퐼푥 = 푔푚3(푉퐶 − 푉푥) (10) VY1 Y1 X z2 VZ2 IZ2 퐼푍1 = 푔푚4(푉퐶 − 푉푥) (11) IX 퐼푍2 = 푔푚5(푉푥 − 푉퐶) (12) VX Figure.6 Circuit symbol of EDDCC Substituting this equations 푉푥 1 −1 1 0 퐼 퐼푦1 0 0 0 0 푉푦1 푉 − 푉 = 푍1 (13) 퐶 푥 푔 퐼 푉 푚4 푦2 0 0 0 0 푦2 = ∙ (7) 퐼푍2 퐼푦3 0 0 0 0 푉푦3 푉퐶 − 푉푥 = (14) 푔푚5 0 0 0 푘1 퐼푧1 [ 퐼푥 ] [퐼 ] [ 0 0 0 −푘2] into this equation 푧2 퐼푥 푉퐶 − 푉푥 = (15) where gm is transconductance of EDDCC. 푔푚3

Then, we can rewrite Iz1 and Iz2 as

푔푚4 퐼푍1 = ( ) 퐼푥 = 푘1퐼푥 (16) 푔푚3

푔푚5 퐼푍1 = ( ) 퐼푥 = 푘2퐼푥 (17) 푔푚3

It is noted that k1 and k2 are the current gain of EDDCC controlled by gm4 and gm5. Current gain of Iz1 and Iz2 is amplified by k1 and k2 that is different from the ordinary DDCC. Hence, the gain k1 and k2 are independently controlled.

Figure. 7 Symbol of developed EDDCC The multi-output EDDCC can simply create by increasing plus-type of EDDCC, when the increased OTA implementation for EDDCC based on parallel input of OTA is connected to OTA4. If CMOS is depicted in Fig. 7. The OTA1 to OTA3 are minus-type EDDCC is increased, the parallel input used to provide a differential difference amplifier of OTA will increase by connecting with OTA5. (DDA). By using nodal analysis, the relation of Relationship of voltage and current is given as voltages Vx, Vy1, Vy2 and Vy3 can be expressed by 푤(푡) 푤(푡) 푉(푡) = {(푅 ) + 푅 (1 − )} 푖(푡) (18) 표푛 퐷 표푓푓 퐷 (푔푚2푔푚3훾푖푛푅)푉푦1−(푔푚1푔푚3훾푖푛푅)푉푦2+(푔푚1푔푚3훾푖푛푅)푉푦3 푉푦 = 1+(푔푚3푅+푔푚2푅+푔푚3훾푖푛푅) where D and W are the thick of sandwiched area and (8) doped area in memristor. R and R are the on off resistance on the concentrated area of high and low where gmi is the gain of transconductance of OTAi, , R is the defined resistor and rin is input resistor in doped. Memristor emulator circuits are proposed in case of small signal of OTA3 which has highly Figs. 8 and 9 with 2-resistor, 1-capacitor and 1- resistance. Relationship between Vx, Y1, Y2, and Y3 analog multiplier which are used the concept Ports for EDDCC is given as followed in [17]. By using the nodal analysis, we get 푉푥 ≈ 푉푦1 − 푉푦2 + 푉푦3 (9) 푉푚 = 푖푚푅1 + 푉푥 (19)

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

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푘2 1 OUTPUT ( ) EDDCC 푉퐶 = ∫0 푣푚 휏 푑휏 푅1퐶1 (20) AD844 Y1 z2 VR 1 7 RMD Y2 z1 X1 W INPUT OUTPUT 6 VC 3 Y1 푉푅 = −푘1푅2 + 퐼푚 Y3 z2 (21) V X VSUm SUm C1 2 z VX R2 X2 Y2 4 R1 VX Following the characteristic of input/output of INPUT Vm Voff1 Voff3 Im Voff2 AD844, the voltage Vmul is given as Figure. 8 Emulator circuit symbol of decremental 푘1푘2푅2 푡 EDDCC memristor and equivalent circuit 푉푚푢푙 = −푖푚 ∫ 푣푚 (휏)푑휏 (22) 10푅1퐶1 0 OUTPUT EDDCC AD844 Y1 z2 7 VR 1 1 RMI Y2 z1 X W OUTPUT Using the input properties of DDCC is given as 6 INPUT VC 3 Y1  Y3 z1 V X V SUm C1 2 z SUm VX R2 X2 Y2 푉 = 푉 − 푉 + 푉 (23) R1 4 푥 푦1 푦2 푌3 INPUT V Voff1 Voff3 m I Voff2 m 푘1푘2푅2 1 ( ) Figure.9 Emulator circuit symbol of incremental 푉푚 = 푖푚푅1 − (푖푚 ∫0 푉푚 휏 푑휏) + 푉푠푢푚 (24) 10푅1퐶1 EDDCC memristor and equivalent circuit

From Eq.(22), we assume Vsum is equal to zero From Eq.(28), the memristance consists of linear and flux m ()t is defined by time-variant and linear time-invariant resistors. If 1 the frequency increases, the linear time-invariant 휙푚(푡) = ∫ 푉푚(푡)푑푡 (25) 0 resistor will decrease. That mean the dependent frequency is pinched the hysteresis loop, when the Then, Eq. (22) can rewrite as frequency is increased. At the fix time, the linear time-variant resistor is updated by frequency that 푉푚 푘1푘2푅2 = 푅1 − ( 휙푚(푡)) = 푀(휙(푡)) (26) will update this circuit by adjusting k1 and k2, 푖푚 10푅1퐶1 respectively. where 푀(휙(푡)) is the resistance of memristor that is 5. Simulation results used k1 and k2 to compensate the attenuation rate constant at 1/10 from multiplier circuit. Moreover, it In order to investigate the operation of the can compensate the effect from frequency that affect proposed memristor emulator circuits, the circuits of to pinched hysteresis loop behavior of memristor. Figs. 7 to 9 were simulated using PSPICE From Figs. 8 and 9, the DC voltage Voff1, Voff2, simulations. ECCII in Fig. 3 and EDDCC in Fig. 5 Voff3 are the bias current to improve the pinched were implemented using commercially available IC hysteresis loop behavior, when the characteristic is LM13600N [57]. A commercially available IC distorted. Voltage Voff1 and Voff2 is applied to adjust AD844J [56] was used for voltage multiplier. the symmetry between the positive and negative of pinched hysteresis loop and then V is defined to Table 2. Summarized performances of ECCII and off3 EDDCC tune the zero-crossing of pinched hysteresis loop. Parameters Value We assume that 푣푖푛(푡) = 푣푝sin (휔푡) is the input of Fig. 8, where 휔 = 2휋푓and Vp is the amplitude of Supply voltage 10 V voltage signal. Then we define OTA LM13600N 푉 푉 휙 (푡) = − ( 푝) cos(휔푡) = ( 푝) cos(휔 − 푡) (27) Vx/Vy and Vx/Vy1 (no load) -0.9 V to 0.9 V 푚 휔 휔 Vx/Vy2 and Vx/Vy3 (no load) -0.1 V to 0.1 V and substitute 휙푚 (푡) in Eq.(30), the memristance is -3dB bandwidth (Vx/Vyi); i = 1, 2, 3 7.3 MHz given as -3dB bandwidth (Iz/Ix) 11 MHz 푘1푘2푅2 Ryi: Cyi; i = 1, 2, 3 185 k: 8.4 pF 푀(휙푚 (푡)) = 푅1 − ( cos(휔푡 − 휋)) 10푅1휔퐶2 (28) Rx: Lx 17 : 24 H Rz: Cz 22 k: 6.12 pF

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

Received: July 2, 2019 42

40 performances of the ECCII and EDDCC were f = 1.0 kHz 30 shown in Table 2. f = 0.5 kHz 20 The proposed decremental memristor emulator circuits in Figs. 8 and 9 were simulated. The values f = 1.5 kHz 10

of resistances and capacitance were given as R1=15

A 

0.0 ,

m k, R2=5 k and C1=1 nF. In case to simulate the I

-10 proposed incremental memristor emulator circuits in Fig.8, the low resistance value such as R1=5 k -20 should be used. The DC voltages Voff1, Voff2, and Voff3 -30 in Fig.9 were given as 26 mV, 0 V and –50 mV, -40 respectively, and current gain k1 was fixed as 1 (k1 = -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vm, V 1). Figure.10 Simulated frequency dependent pinched Fig. 10 shows the simulated frequency- hysteresis loop of memristor emulator at current gain k1 = dependent pinched hysteresis loop in voltage-current k2 = 1 and different frequencies relationship corresponding to vtm ( ) versus itm ( ) 40 plane for the frequencies of 0.5, 1.0 and 1.5 kHz k =1.5 30 2 with amplitude of applied signal 0.5 V (peak) k2=2.0 constant and the current gain k2 was 1. This result 20 was confirmed that when amplitude of applied

10 k2=1.0 signal and capacitance-value constants, the proposed A

 memristir emulator circuit depends on the frequency

, 0.0 m I of the exciting source. -10 Fig. 11 shows the simulated frequency-

-20 dependent pinched hysteresis loop in voltage-current relationship corresponding to versus -30 plane for the current gains k2 of 1.0, 1.5 and 2.0 -40 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 while the frequency of 1 kHz with amplitude of V , V m applied signal 0.5 V (peak) constants. This result Figure.11 Simulated frequency dependent pinched was confirmed that the frequency-dependent hysteresis loop of memristor emulator at f = 1 kHz and k1 = 1 with different current gains k2 pinched hysteresis loop in voltage-current relationship of the proposed circuits can also be 40 controlled by adjusting current gains of current f = 10 kHz 30 conveyor. f = 20 kHz To confirm Eq. (17) that by increasing the 20 current gain of current conveyor, the pinched

10 hysteresis loop behavior of proposed memristor

emulator circuit can be pushed for operating at

A

, 0.0 m

I higher frequency. Fig. 12 shows the simulated

-10 frequency-dependent pinched hysteresis loop in voltage-current relationship corresponding to vm(t) -20 versus im(t) plane for the current gain k2 = 20. In this -30 case, the frequencies of the exciting source of 10 kHz and 20 kHz at amplitude of 0.5 V (peak) were -40 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 applied and value of capacitance C1 is constant. In V , V m this result, the voltages V = 48 mV and V = – Figure.12 Simulated frequency dependent pinched off1 off3 40 mV were used to obtain perfect the pinched hysteresis loop of memristor emulator at k1 = 1 and k2 = 20 with frequency of 10 and 20 kHz hysteresis loop behavior. The proposed decremental memristor emulator The commercially available IC LM13600N was circuit in Fig. 8 was and simulated. The values of supplied by the DC supply voltages of 10 V while resistances and capacitance were similar to the OTA1, OTA2 for ECCII in Fig. 3 and OTA1, OTA2, simulation in Fig. 8 The circuit was design as k1 = k2 OTA3 for EDDCC in Fig. 5 were biased by the DC = 1. Fig. 13 shows simulated frequency-dependent current sources of 50 A. The simulated

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

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60 Therefore, the meminductance is obtained from RM- single L converter as parallel M 40 serial 푑휎퐶푀 푅1푅2푅3 20 퐿푀 = = (34) parallel 푑푞퐿푀 푅1푅푀

A single

, 0.0

m 100 kΩ 620 kΩ 47 kΩ 10 kΩ

I serial

LDR VCC 100 Ω -20 220 nF 5 kΩ - 160 kΩ V TL084 in - 1 kΩ + TL084 - TL084 + 10 kΩ 10 kΩ + -40 D1 VEE -60 Figure.14 Schematic of proposed RM-CM circuit -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Vm, V Figure.13 Simulated pinched hysteresis loop of memristor 100 kΩ 620 kΩ 47 kΩ 10 kΩ at 1 kHz frequency with series and parallel connection LDR CR = 22 mF 100 Ω 4 kΩ 10 kΩ - 160 kΩ TL084 Vin LR = 2 H - 1 kΩ + TL084 - TL084 + 10 kΩ pinched hysteresis loop in voltage-current 10 kΩ + D1 relationship corresponding to 푣푚(푡) versus 푖푚(푡) RM-L-C plane for the frequency of 1 kHz with amplitude of Figure.15 Schematic of proposed R -L-C circuit applied signal 0.5 V (peak) constant. This result was M confirmed that proposed circuit in Fig. 9 can be 100 kΩ 620 kΩ 47 kΩ 10 kΩ LDR applied to connection in serial and in parallel. VCC 100 Ω 220 nF 5 kΩ 10 kΩ - 160 kΩ TL084 - 1 kΩ + TL084 - TL084 6. Circuit implementation of RM-CM and RM- + 10 kΩ 10 kΩ + D1 LM convertor VEE 10 kΩ

220 nF 10 kΩ +V +V Following [14], the memcapacitor and 220 nF LC 2H RC 1 kΩ meminductor emulators are constructed using 330 Ω - x - AD844 - Vin 2 kΩ X’ AD844 shown in RM-CM convertor in Fig. 14. + + 220 nF AD844 y + 220 nF Relationship of vCM and vRM is give as vRM = vCM. Y’ Then, OTA formed by AD844 to produce the current iRM is given as Figure.16 Schematic of proposed R-L-CM circuit

RL CL y 1 + - LDR 10 kΩ 푖푅푀 = ( ) ∫ 푖퐶푀푑푡 (29) Vin 1.2 kΩ AD844 Z 푅퐶 - 22µF x + 1 kΩ 1 kΩ 10 kΩ - y + TL074 - Z Memcapacitance from RM-CM is defined as V + AD844 LM + - 1 kΩ x 푑휎퐶 푅퐶 퐶 = 푀 = (30) 10 kΩ 푀 푑휙퐶푀 푅푀 Figure. 17 Schematic of proposed R-LM-C circuit

Fig. 15 depicts the RM-LM convertor, when vX=xY, 620 kΩ 47 kΩ 10 kΩ vZ=voutput, iZ = iX that is used for RM-LM convertor. 100 kΩ LDR The current through the equivalent meminductor iLM VCC 100 Ω 220 nF 5 kΩ - 160 kΩ is defined as TL084 - 1 kΩ + TL084 - TL084 + 10 kΩ 10 kΩ + D1 (0−푉푥) (0−푉푦) VEE 푖 = , 푖 = (31) RL CL 퐿푀 푅 푅푀 푅 y’ 1 3 + - 10 kΩ Vin 1.2 kΩ AD844 Z’ - 22µF x’ + 1 kΩ OUT PUT Then, the relationship of vLM and vRM as 1 kΩ 10 kΩ - y TL074 - Z + AD844 + 1 kΩ x

푣퐿푀 = 푣푍 = 푣푦′ = 푣푥′ (32) 10 kΩ R-LM-C 1 푣푅푀 = ∫ 푣퐿푀푑푡 (33) 푅2퐶2 Figure.18 Schematic of proposed R-LM-C circuit

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

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Figure.19 Physical implementation of R-LM-C circuit from schematic shown in Fig. 18

Figure.22 Experimental result vRM, vCR, vLR of RM-L-C circuit at f = 6 Hz, vin = 2 V

Figure.20 Physical implementation of R-L-CM circuit is used schematic of proposed RM-CM circuit in Fig.14

Figure.23 Experimental result vRM, vCR, vLR of RM-L-CM circuit at f = 16 Hz, vin = 2 V

From the experiment setup of RM-L-CM circuit are performed at 6 Hz and 16 Hz for vin 2 V sinusoidal signal of input voltage shown in Figs. 22 and 23. The voltage vCR across the capacitor CR, voltage vLR across the capacitor LR, and voltage vRM across the memristor for the given frequencies can

Figure.21 Experimental setup of LDR circuit is used be seen that vRM is ahead of vCR and vRM lags behind vLR. These results demonstrate that LDR-memristor schematic of proposed R-L-CM circuit in Fig. 16 equivalent circuit can be occupied both the 7. Experimental results for characteristics of memristor circuit and memory-less resistor characteristics. RM-L-C and R-LM-C circuits

We consider the design of equivalent circuit for 6.2 Experiment of R-LM-C circuit RLC-mode circuit in the RM-L-C and R-LM-C circuits shown in Figs. 17-18, respectively. Design of R-LM-C circuit using LDR-based Experimental setup for LDR circuit used is depicted memristor-equivalent circuit is shown in Fig. 17. in Fig. 21. The experiment setup of R-LM-C circuit are performed at 16 Hz and 30 Hz for 2 V sinusoidal

6.1 Experiment of RM-L-C circuit signal of input voltage shown in Figs. 24 and 25. The voltage vCR, voltage vLR , and voltage vRM for the Design of RM-L-C circuit using LDR-based given frequencies can be realized that vRM is ahead memristor-equivalent circuit shown in Fig. 15. of vCR and vRM lags behind vLR

International Journal of Intelligent Engineering and Systems, Vol.12, No.6, 2019 DOI: 10.22266/ijies2019.1231.04

Received: July 2, 2019 45

Figure.24 Experimental result vRM, vCR, vLR of R-LM-C Figure. 27 Experimental result vRM, vCR, vLR of R-LM-C circuit at f = 16 Hz, vin = 2 V circuit at f = 15 Hz, vin = 2 V

linear characteristics of memristor. Futhermore, the measurement phase relation is obtained at low frequency of sinusoidal, which is applied to a memristor device. After that the frequency are increases, then the phase shift is very narrow until it becomes as a line.

8. Conclusion We have proposed the memristor emulator circuits based on commercially available ICs as AD844, TL074, TL084, resistors, and capacitors. OTA has been used to realize ECCII and Figure.25 Experimental result vRM, vCR, vLR of R-LM-C EDDCC, which are the important active element. circuit at f = 30 Hz, vin = 2 V Proposed emulator circuits with memresitive- element-equivalent circuits have been simulated by PSPICE simulator and circuit board is used for experiment tests. RLC-mode circuits are studied including with memristor, memcapacitor and meminductor. In the practical experiments, the proposed memcapacitor and meminductor circuits based on the LDR memristor-equivalent circuit can be verified that the experimental results are agreed with the proposed theory.

Acknowledgments This work was supported by Rajamangala University of Technology Phra Nakhon. Figure. 26 Experimental result vRM vCR, vLR of R-LM-C circuit at f = 3.5 Hz, vin = 2 V References

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