DOCSLIB.ORG

Ultra Low Power Robust 12T Sram Architecture Based on Parallel Cross- Coupling Feedback

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Ultra Low Power Robust 12T Sram Architecture Based on Parallel Cross- Coupling Feedback OF JOURNAL CRITICAL REVIEWS ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS- COUPLING FEEDBACK Dr.H.Kareemullah2, Mr.C.Venkatnarayanan2 1Assistant Professor, Department of Electronics & Instrumentation Engineering, B.S.A.Crescent Institute of Science & Technology, Chennai, email: [email protected] 2Teaching Fellow, Department of ECE,University College of Engineering Arni, Thatchur, Arni – 632 326. email: [email protected] ABSTRACT: Ultra-low power, low on-chip processing circuits are highly desirable for lightweight and wearable applications. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This paper provides a new standard memory cell based (SCM) twelve-transistor (12 T) circuit. In order to achieve high region performance and low energy usage, three gating transistors for each column of SRAM cells have been used. The three-stage read-out system eliminates reading delays as well as energy consumption. As compared to the previously published SCM circuit in a 65-nm CMOS technology, the read and write energy consumption per operation is reduced. In comparison to the previously published SCM circuit, read time and cell lay-out are also reduced . In comparison, the traditional T-architecture guarantees high data consistency and writes functionality with the proposed 12 T SRAM module. KEYWORDS: SCM, twelve-transistor and SRAM cells I. INTRODUCTION: The need for low power / energy consumption of the integrated ICs, is increasingly rigid with the prosperity of portable and wearable electronic devices and the ubiquitous implementation of wireless sensor networks. The supply voltage of the ICs can be reduced in the sub / near threshold regions if the frequency is not a main concern in order to suppress the power / energy consumption of these devices. The embedded chips include essential elements which make a major contribution to overall power / energy use [16] in static random access memory (SRAM) circuits. Nonetheless, due to the serious damage in read static noise margins and the write capacity, as well as the severe impacts of the read bitline leakage current[17], a regular six transister (6 T) SRAM track typically provided by the foundry can not be scaled to sub / near threshold regions. For embedded chips in portable or wearable electronics, designing Ultra-low-power SRAM circuits is therefore vital. The topology of the SRAM cell is revamped to allow more transistors to maximize the read static noise gap, also to boost write performance, and reduce the read bitline leakage present. However, the compilers of the memory must be designed in a complicated and custom way, given the existence of analog and analog signals in the SRAM array as pre-loaded circuitry and sensor amplifiers. The architecture of the standard cell- based memory (SCM) circuit is an alternative to performing ultra-low power operations for SRAM circuits[19]. By using regular logic cells to construct the SRAM modules, all inputs and outputs are electrical signals. Peripheral electronics can also be fully implemented for automated model cells. The current EDA software can therefore be used to conduct logic synthesis as well as automated positioning and routing to produce the net list and configuration of the necessary SRAM arrays. The rapid generation of these SRAM arrays is highly desirable for those embedded system applications where a large number of different sized memory circuits are needed. In comparison, read and write operations are performed similarly through the use of modern standard cells as the signal transmission in traditional combinational circuits, which guarantees high data reliability and good write capacity. The biggest problem with the SCM cells is the large area of each cell overhead. Compared to conventional 6 T SRAM cell, the layout region of each SCM cell could be two to three times greater. Nevertheless, the area output of the total SRAM system could be even higher with the regular cell-based SRAM circuit relative to the previously published ultra-low voltage SRAM circuits. It happens when there is relatively little size of the memory array so the peripheral circuit greatly contributes to the entire array area [7]. A novel robust 12 T standard cell based SRAM cell for ultra-low-voltage ultra-low-power applications is proposed in this article. The circuit is powered at a lower supply voltage to minimize leakage in Complementary Metal Oxide Systems (CMOS), which, in effect, slower the circuit speed. Delay can be minimized using lower 407 OF JOURNAL CRITICAL REVIEWS ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 threshold voltage transistors, but this reduces the flow rate again (mainly the flow cycle). Contrary conditions exist and the construction of a memory cell with a low standing leak and reasonable reliability requires good optimization. Higher voltages and smaller measurements induce important data reliability loss in cells. In order to achieve high range performance and low write energy consumption, three transistors are used on every column of SRAM cells. During the three-stage reading cycle, reading delays and power consumption are minimized. In addition, parallel cross-coupling feedback with the proposed SRAM 12 T cell, ensures high data stability and writing ability. That is how the paper is arranged. Section II reviews previously published SRAM standard cell-based circuits. Sections III in which the problem statement was depicted and Section IV present and evaluate proposed novel 12 T standard cell-based SRAM circuit. Section V depicts the summary of the paper. II. LITERATURE SURVEY In [1] a modern 12 T memory cell that is energy-efficient is suggested to help architecture hardened radiation (RHD) in close-to-threshold voltage resistance multi-node (SEMNU) single-event upsets. Through monitoring cross-coupled PMOS devices of inverters through foolish access transistors, the radiation complexity of the proposed storage cell will be increased. In STMicroelectronics 6, we validated the proposed memory cell. In [2] they propose an overall reduction in the amount of VMIN and resources per service with a 12 ST-based SRAM-bit cell to promote the process variance sensitive write- capability. In [3] a halve select 12 T SRAM free cell features an input cutting tool to enhance the ability to write and separate reading paths in order to improve reading stability. The read and write capabilities are 1.95 and 2.84 respectively better than the normal 6 T cell at 0.4 V, respectively. In [4] Present the SRAM, a compiler that targets small to media array sizes and provides a smaller area solution compared to traditional 6T-based SRAMs, with the ultra low Voltage one-port random access memory. The design uses a 12 T write and the read upset free bit-cell. Array architecture uses a read-modifying writing scheme to enable masking and multiplexing columns for bit-write (BW). The Built-inside Self-Test (BIST) and Synchronous Writing Through (SWT) methods have testability, while the Sleep-and Shutdown Methods Power Management (PM) alternative is included. In [5] a 9-Transistor (TG9 T) SRAM bitcell power-efficient transmission gate has been proposed. In [6] Optimized MTJ (Approximate Calculation Application (AC) Procedure, focused on resistive ternary information addressable memory (ReTCAM). In [7] a new 12 T SRAM cell is introduced that is used to improve reliability with an Schmitt control circuit and to reduce the leakage current in standby mode with a transistor. In [8] discusses the phenomenon of crucial linear transfer of energy (LET) and the charge obtained by scaling the technology of each circuit. In [9] Propose modified 12 T SRAM cell (WWL12 T) FinFET and self refreshing. To increase the FinFET's reliability and performance, the double-k gate isolator and symmetric distance is used.. In [10] the 12 T static random access memory (SRAM) cell dependent on the one-ended Schmitt signal (ST). Cross-point data-conscious writing framework is used in the planned cell and therefore promotes interlocking architecture to minimize soft errors. The proposed cell is not interrupted by reading because the bit line is completely isolated from the data storage node. In [11] presents a 12 T 2RW SRAM low voltage with parallel exposure and blocked interruption to improve the performance without degradation. The suggested SRAM cell reduces interference by splitting reading from internal nodes and minimizes the probability of worst case stability with a 6 percent region cost. Furthermore, hierarchical bitlines, a virtual ground technology and the minimum voltage and energy consumption will be further reduced. In [12] the design based on the 12 transistor (12 T) cell is proposed for the low power and variability-aware static random access memory (SRAM). In [13] an advanced 12 T Static Random Access Memory (SRAM) cell with the following advantages: decreased leakage current and increased efficiency utilizing 180NM Technology was proposed. In [14] Presents a 9 T static random access memory (SRAM) cell with a single-ended Schmitt signal. The architecture suggested offers improved reading stability when ST-based inverters are used. In [15] The introduction of the Schmitt Trigger (ST) enhanced switching functionality, reduced the power outages and increased the SNM. Upon applying the memistor to the SRAM trigger Schmitt, the cell was not fragile and the SNM improved more. III. PROBLEM STATEMENT The SRAM technology suffered a lot due to leakage issues. There are several other existing technologies that are there, but they are all not useful. Hence there is a need for an effective method to overcome the leakage issues in the SRAM technology. We would propose a new SCM with parallel cross-coupling logic that will reduce expenses, time, power, and memory complexity.
Load more

Recommended publications
  • Memristive Devices for Computing J
    REVIEW ARTICLE PUBLISHED ONLINE: 27 DECEMBER 2012 | DOI: 10.1038/NNANO.2012.240 Memristive devices for computing J. Joshua Yang1, Dmitri B. Strukov2 and Duncan R. Stewart3 Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met. he search for new computing technologies is driven by the con- excellent review articles8–19. Here, we focus on the chemical and phys- tinuing demand for improved computing performance, but ical mechanisms of memristive devices, and try to identify the key Tto be of use a new technology must be scalable and capable. issues that impede the commercialization of memristors as computer Memristor or memristive nanodevices seem to fulfil these require- memory and logic. ments — they can be scaled down to less than 10 nm and offer fast, non-volatile, low-energy electrical switching.
    [Show full text]
  • Navaraj, William Ringal Taube (2019) Inorganic Micro/Nanostructures- Based High-Performance Flexible Electronics for Electronic Skin Application
    Navaraj, William Ringal Taube (2019) Inorganic micro/nanostructures- based high-performance flexible electronics for electronic skin application. PhD thesis. https://theses.gla.ac.uk/40973/ This work is made available under the Creative Commons Attribution- NonCommercial 4.0 License: https://creativecommons.org/licenses/by- nc/4.0/ Enlighten: Theses https://theses.gla.ac.uk/ [email protected] Inorganic Micro/Nanostructures-based High-performance Flexible Electronics for Electronic Skin Application William Ringal Taube Navaraj A Thesis submitted to School of Engineering University of Glasgow in fulfilment of the requirements for the degree of Doctor of Philosophy January 2019 Supervisors: Prof. Ravinder Dahiya Prof. Duncan Gregory Abstract Electronics in the future will be printed on diverse substrates, benefiting several emerging applications such as electronic skin (e-skin) for robotics/prosthetics, flexible displays, flexible/conformable biosensors, large area electronics, and implantable devices. For such applications, electronics based on inorganic micro/nanostructures (IMNSs) from high mobility materials such as single crystal silicon and compound semiconductors in the form of ultrathin chips, membranes, nanoribbons (NRs), nanowires (NWs) etc., offer promising high-performance solutions compared to conventional organic materials. This thesis presents an investigation of the various forms of IMNSs for high-performance electronics. Active components (from Silicon) and sensor components (from indium tin oxide (ITO), vanadium pentaoxide (V2O5), and zinc oxide (ZnO)) were realised based on the IMNS for application in artificial tactile skin for prosthetics/robotics. Inspired by human tactile sensing, a capacitive-piezoelectric tandem architecture was realised with indium tin oxide (ITO) on a flexible polymer sheet for achieving static (upto 0.25 kPa-1 sensitivity) and dynamic (2.28 kPa-1 sensitivity) tactile sensing.
    [Show full text]
  • Modeling of Memristive Systems and Its Applications
    Modeling of memristive systems and its applications By Jose´ Balaam Alarcon´ Angulo Thesis submitted as a partial requirement for the degree of Master in Science with specialty in Electronics at the Instituto Nacional de Astrof´ısica, Optica´ y Electronica´ San Andres´ Cholula, Puebla Adviser: Dr. Librado Arturo Sarmiento Reyes, INAOE c INAOE 2017 The author hereby grants to INAOE permission to reproduce and to distribute copies of this thesis document in whole or in part Modeling of memristive systems and its applications Master's Thesis By: Jos´eBalaam Alarc´onAngulo Adviser: Dr. Librado Arturo Sarmiento Reyes Instituto Nacional de Astrof´ısica Optica´ y Electr´onica Electronics Department San Andres´ Cholula, Puebla. January 16, 2018 i Agradezco a mis padres Guadalupe Alarc´ony Ma. Teresa y a mi hermana Dayanira Alarc´onpor su incondicional apoyo a lo largo de toda mi vida. Al doctor Arturo Sarmiento por su orientaci´ondurante el desarrollo de esta tesis.Y a todos mis amigos que siempre est´anah´ıe hicieron invaluables aportes para el desarrollo de este trabajo. Modeling of memristive systems and its applications iii To my future readers. I hope you will enjoy reading this work as much as I did when writing it and that it will serves as a guide for future work. Modeling of memristive systems and its applications Resumen Desde el advenimiento del memristor como elemento b´asicode circuito real, ha habido un significativo impulso en la investigaci´onorientada al desarrollo de aplicaciones del memristor en dise~node circuitos y procesamiento de se~nales.Amplificadores con retroalimentac´onnegativa basados en nullores se encuentran entre las aplicaciones m´as factibles debido a que la propiedad de memoria del memristor puede ser incorporada a la transferencia de amplificaci´onal colocar el memristor directamente en el lazo de retroalimentaci´on.
    [Show full text]
  • A Survey of Memristive Threshold Logic Circuits Akshay Kumar Maan, Deepthi Anirudhan Jayadevi, and Alex Pappachen James, Senior Member, IEEE
    IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS 1 A Survey of Memristive Threshold Logic Circuits Akshay Kumar Maan, Deepthi Anirudhan Jayadevi, and Alex Pappachen James, Senior Member, IEEE Abstract—In this paper, we review the different memristive Threshold logic (TL) itself was first introduced by Warren threshold logic (MTL) circuits that are inspired from the synaptic McCulloch and Walter Pitts in 1943 [17] in the early model action of flow of neurotransmitters in the biological brain. of an artificial neuron based on the basic property of firing Brain-like generalisation ability and area minimisation of these threshold logic circuits aim towards crossing the Moore’s law of the biological neuron. The logic computed the sign of the boundaries at device, circuits and systems levels. Fast switch- weighted sum of its inputs. Modelling a neuron as a threshold ing memory, signal processing, control systems, programmable logic gate (TLG) that fires when input reaches a threshold has logic, image processing, reconfigurable computing, and pattern been the basis of the research on neural networks (NNs) and recognition are identified as some of the potential applications of their hardware implementation in standard CMOS logic [18]. MTL systems. The physical realization of nanoscale devices with However, to continue geometrical scaling of semiconductor memristive behaviour from materials like TiO2, ferroelectrics, silicon, and polymers has accelerated research effort in these components as per Moore’s Law (and beyond), semiconductor application areas inspiring the scientific community to pursue industry needs to investigate a future beyond CMOS, and design of high speed, low cost, low power and high density designs beyond the fetch-decode-execute paradigm of von neuromorphic architectures.
    [Show full text]
  • Feedback Systems with Memristors
    Feedback Systems with Memristors Milan Stork1, Josef Hrusak2, Daniel Mayer3 1,2Department of Applied Electronics and Telecommunications, 3Department of Theory of Electrical Engineering University of West Bohemia, 30614 Plzen, Czech Republic [email protected], [email protected], [email protected] Abstract In 1971 the electrical engineer Leon Chua pointed out [1], that, a fourth passive element should in fact be added to the list The contribution is concerned on the properties of the new of basic circuits elements. He named this hypothetical element, ideal circuit element, a memristor. By definition, a linking flux and charge, the memristor. It is just the inability to memristor relates the charge q and the magnetic flux in a duplicate the properties of the memistor with a combination of circuit, and complements a resistor R, a capacitor C, and an the other three passive circuits elements, what makes the inductor L as an ingredient of ideal electrical circuits. The existence question of the memristor fundamental. properties of these three elements and their circuits are a The point is that a static nonlinearity interpreted as a part of the standard curricula. The existence of the memristor always appears instantaneously as a nonlinear memristor as the fourth ideal circuit element was predicted resistor. However, in fact it represents a new passive element, in 1971 based on symmetry arguments, but was clearly which may relate some state variable to flux without storing a experimentally demonstrated in 2008. The definition of the magnetic field. memristor is based solely on fundamental circuit variables, The HP memristor is a passive two-terminal electronic device similar to the resistor, capacitor, and inductor.
    [Show full text]
  • A Non-Destructive Crossbar Architecture of Multi-Level Memory-Based Resistor" (2015)
    Southern Illinois University Carbondale OpenSIUC Theses Theses and Dissertations 5-1-2015 A Non-destructive Crossbar Architecture of Multi- Level Memory-Based Resistor Seyedmorteza Sahebkarkhorasani Southern Illinois University Carbondale, [email protected] Follow this and additional works at: http://opensiuc.lib.siu.edu/theses Recommended Citation Sahebkarkhorasani, Seyedmorteza, "A Non-destructive Crossbar Architecture of Multi-Level Memory-Based Resistor" (2015). Theses. Paper 1629. This Open Access Thesis is brought to you for free and open access by the Theses and Dissertations at OpenSIUC. It has been accepted for inclusion in Theses by an authorized administrator of OpenSIUC. For more information, please contact [email protected]. A NON-DESTRUCTIVE CROSSBAR ARCHITECTURE OF MULTI-LEVEL MEMORY-BASED RESISTOR by Seyedmorteza Sahebkarkhorasani B.S., Sadjad University of Technology, 2011 A Thesis Submitted in Partial Fulfillment of the Requirements for the Master of Science Department of Electrical and Computer Engineering in the Graduate School Southern Illinois University Carbondale May 2015 THESIS APPROVAL A NON-DESTRUCTIVE CROSSBAR ARCHITECTURE OF MULTI-LEVEL MEMORY-BASED RESISTOR By Seyedmorteza Sahebkarkhorasani A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science in the field of Electrical and Computer Engineering Approved by: Dr. Themistoklis Haniotakis, Chair Dr. Reza Ahmadi Dr. Mohammad Sayeh Graduate School Southern Illinois University Carbondale April 4, 2015 AN ABSTRACT OF THE THESIS OF Seyedmorteza Sahebkarkhorasani, for the Master of Science degree in Electrical and Computer Engineering, presented on April 4, 2015, at Southern Illinois University Carbondale. TITLE: A NON-DESTRUCTIVE CROSSBAR ARCHITECTURE OF MULTI-LEVEL MEMORY-BASED RESISTOR MAJOR PROFESSOR: Dr.
    [Show full text]
  • Memristor and Memristive Devices and Systems
    Memristive Devices and Circuits for Computing, Memory, and Neuromorphic Applications by Omid Kavehei B. Eng. (Computer Systems Engineering, Honours) Arak Azad University, Iran, 2003 M. Eng. (Computer Architectures Engineering, Honours) Shahid Beheshti University, Iran, 2005 Thesis submitted for the degree of Doctor of Philosophy in School of Electrical & Electronic Engineering Faculty of Engineering, Computer & Mathematical Sciences The University of Adelaide, Australia December, 2011 Supervisors: Dr Said Al-Sarawi, School of Electrical & Electronic Engineering Prof Derek Abbott, School of Electrical & Electronic Engineering c 2011 Omid Kavehei All Rights Reserved Contents Contents iii Abstract vii Statement of Originality ix Acknowledgements xi Conventions xv Publications xvii List of Figures xxi List of Tables xxv Chapter 1. Introduction 1 1.1 Definition of memristor ............................ 3 1.2 Applications of memristor ........................... 5 1.3 Prospects for memristors ............................ 7 1.4 Thesis outline .................................. 8 1.5 Summary of original contributions ...................... 11 Chapter 2. Memristor and Memristive Devices 13 2.1 Introduction ................................... 15 2.2 Memristor and memristive devices ...................... 15 2.2.1 Memristive devices within Chua’s periodic table . 16 2.2.2 Properties and fundamentals ..................... 16 2.3 Emerging non-volatile memory technologies . 22 2.3.1 Significance ............................... 22 2.3.2 Phase change memory
    [Show full text]
  • Memristive Systems Analysis of 3-Terminal Devices
    Memristive Systems Analysis of 3-Terminal Devices Blaise Mouttet George Mason University Fairfax, Va USA Abstract— Memristive systems were proposed in 1976 by Leon rarely been applied in electronic device design or analysis. Chua and Sung Mo Kang as a model for 2-terminal passive Only recently has it been recognized that the memristive nonlinear dynamical systems which exhibit memory effects. Such systems framework may be relevant to the modeling of passive, systems were originally shown to be relevant to the modeling of 2-terminal semiconductor devices which exhibit memory action potentials in neurons in regards to the Hodgkin-Huxley resistance effects [3]. This is despite the fact that materials model and, more recently, to the modeling of thin film materials exhibiting such effects were known [4] several years prior to such as TiO2-x proposed for non-volatile resistive memory. the original memristive systems paper ! However, over the past 50 years a variety of 3-terminal non- passive dynamical devices have also been shown to exhibit The memristive systems framework has recently been memory effects similar to that predicted by the memristive expanded to cover memory capacitance and memory system model. This article extends the original memristive inductance devices [5]. This begs the question of whether it systems framework to incorporate 3-terminal, non-passive would also be useful to develop an expanded memristive devices and explains the applicability of such dynamic systems systems model to cover memory transistors. Several examples models to 1) the Widrow-Hoff memistor, 2) floating gate memory of memory transistors are found in the literature dating back 50 cells, and 3) nano-ionic FETs.
    [Show full text]
  • Exploring Memristor Based Analog Design in Simscape
    EXPLORING MEMRISTOR BASED ANALOG DESIGN IN SIMSCAPE Mahesh Gautam Thesis Prepared for the Degree of MASTER OF SCIENCE UNIVERSITY OF NORTH TEXAS May 2013 APPROVED: Saraju P. Mohanty, Major Professor Elias Kougianos, Co-Major Professor Mahadevan Gomathisankaran, Committee Member Barrett Bryant, Chair of the Department of Computer Science and Engineering Costas Tsatsoulis, Dean of the College of Engineering Mark Wardell, Dean of the Toulouse Graduate School Gautam, Mahesh. Exploring Memristor Based Analog Design in Simscape. Master of Science (Computer Engineering), May 2013, 47 pp., 4 tables, 41 figures, bibliography, 46 titles. With conventional CMOS technologies approaching their scaling limits, researchers are actively investigating alternative technologies for ever increasing computing and mobile demand. A number of different technologies are currently being studied by different research groups. In the last decade, one-dimensional (1D) carbon nanotubes (CNT), graphene, which is a two-dimensional (2D) natural occurring carbon rolled in tubular form, and zero-dimensional (0D) fullerenes have been the subject of intensive research. In 2008, HP Labs announced a ground-breaking fabrication of memristors, the fourth fundamental element postulated by Chua at the University of California, Berkeley in 1971. In the last few years, the memristor has gained a lot of attention from the research community. In-depth studies of the memristor and its analog behavior have convinced the community that it has the potential in future nano-architectures for optimization of high-density memory and neuromorphic computing architectures. The objective of this thesis is to explore memristors for analog and mixed-signal system design using Simscape. This thesis presents a memristor model in the Simscape language.
    [Show full text]
  • A Survey of Neuromorphic Computing and Neural Networks in Hardware Catherine D
    1 A Survey of Neuromorphic Computing and Neural Networks in Hardware Catherine D. Schuman, Member, IEEE, Thomas E. Potok, Member, IEEE, Robert M. Patton, Member, IEEE, J. Douglas Birdwell, Fellow, IEEE, Mark E. Dean, Fellow, IEEE, Garrett S. Rose, Member, IEEE, and James S. Plank, Member, IEEE Abstract—Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neu- roscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brain- like ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we Fig. 1. Areas of research involved in neuromorphic computing, and how they provide a comprehensive survey of the research and motivations are related. for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromor- phic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and research, as well as provide a starting point for those new to learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion the field.
    [Show full text]
  • Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin
    ORIGINAL RESEARCH published: 20 September 2017 doi: 10.3389/fnins.2017.00501 Nanowire FET Based Neural Element for Robotic Tactile Sensing Skin William Taube Navaraj 1, Carlos García Núñez 1, Dhayalan Shakthivel 1, Vincenzo Vinciguerra 2, Fabrice Labeau 3, Duncan H. Gregory 4 and Ravinder Dahiya 1* 1 Bendable Electronics and Sensing Technologies Group, School of Engineering, University of Glasgow, Glasgow, United Kingdom, 2 ST Microelectronics, Catania, Italy, 3 Department of Electrical and Computer Engineering, McGill University, Montreal, QC, Canada, 4 WestCHEM, School of Chemistry, University of Glasgow, Glasgow, United Kingdom This paper presents novel Neural Nanowire Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in electronic skin (e-skin). The viability of Si nanowires (NWs) as the active material for υ-NWFETs in HNN is explored through modeling and demonstrated by fabricating the first device. Using υ-NWFETs to realize HNNs is an interesting approach as by printing NWs on large area flexible substrates it will be possible to develop a bendable tactile skin with distributed neural elements (for local data processing, as in biological Edited by: skin) in the backplane. The modeling and simulation of υ-NWFET based devices show Calogero Maria Oddo, Sant’Anna School of Advanced that the overlapping areas between individual gates and the floating gate determines Studies, Italy the initial synaptic weights of the neural network - thus validating the working of Reviewed by: υ-NWFETs as the building block for HNN. The simulation has been further extended to Martin Ziegler, University of Kiel, Germany υ-NWFET based circuits and neuronal computation system and this has been validated Sunil L.
    [Show full text]
  • Tungsten Oxide Memristive Devices for Neuromorphic Applications
    Tungsten Oxide Memristive Devices for Neuromorphic Applications by Ting Chang A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering) in The University of Michigan 2012 Doctoral Committee: Associate Professor Wei Lu, Chair Associate Professor Çagliyan Kurdak Assistant Research Scientist Becky Lorenz Peterson Assistant Professor Zhaohui Zhong © Ting Chang 2012 DEDICATION To my mom “Perfect you in every good work for the doing of His will, doing in us that which is well pleasing in His sight through Jesus Christ…..” Hebrews 13:21 ii ACKOWLEDGEMENTS I would not have been who I am without His blessing and plentiful supply, especially the encouragement, nourishing, and cherishing from His loved ones. The Lord Jesus Christ is worthy of my highest praise! Enormous gratitude is extended to my advisor, Prof. Wei Lu, who has given me the opportunity and constant support throughout my course of study. He has always been available and helpful, and has really set up a great example of blending smart mind and hard work into success. I have been granted exposures to many new experiences, from developing research ideas, preparing proposals, involving in collaborations, attending prestigious conferences, to mentoring students. I would like to thank my committee members for their useful discussions: Dr. Becky L. Peterson, Prof. Çagliyan Kurdak, and Prof. Zhaohui Zhong. I would also like to express my appreciation to my former and current group members: Sung Hyun Jo, Kuk-Hwan Kim, Wayne Fung, Siddharth Gaba, Patrick Sheridan, Lin Chen, Shinhyun Choi, Chao Du, and Dr. Yang for their helpful discussions and timely assistances, each of whom a brilliant individual.
    [Show full text]