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ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 ULTRA LOW POWER ROBUST 12T SRAM ARCHITECTURE BASED ON PARALLEL CROSS- COUPLING FEEDBACK

Dr.H.Kareemullah2, Mr.C.Venkatnarayanan2

1Assistant Professor, Department of Electronics & Instrumentation Engineering, B.S.A.Crescent Institute of Science & Technology, Chennai, email: [email protected] 2Teaching Fellow, Department of ECE,University College of Engineering Arni, Thatchur, Arni – 632 326. email: [email protected]

ABSTRACT: Ultra-low power, low on-chip processing circuits are highly desirable for lightweight and wearable applications. Memory is an integral part of most of these systems and is also diminished as the scale of the system reduces. Low power and processing architecture at high speed is therefore a major concern. The durability of random static access memory cells (SRAM) is another critical factor. This paper provides a new standard based (SCM) twelve- (12 T) circuit. In order to achieve high region performance and low energy usage, three gating for each column of SRAM cells have been used. The three-stage read-out system eliminates reading delays as well as energy consumption. As compared to the previously published SCM circuit in a 65-nm CMOS technology, the read and write energy consumption per operation is reduced. In comparison to the previously published SCM circuit, read time and cell lay-out are also reduced . In comparison, the traditional T-architecture guarantees high data consistency and writes functionality with the proposed 12 T SRAM module.

KEYWORDS: SCM, twelve-transistor and SRAM cells

I. INTRODUCTION:

The need for low power / energy consumption of the integrated ICs, is increasingly rigid with the prosperity of portable and wearable electronic devices and the ubiquitous implementation of wireless sensor networks. The supply voltage of the ICs can be reduced in the sub / near threshold regions if the frequency is not a main concern in order to suppress the power / energy consumption of these devices. The embedded chips include essential elements which make a major contribution to overall power / energy use [16] in static random access memory (SRAM) circuits. Nonetheless, due to the serious damage in read static noise margins and the write capacity, as well as the severe impacts of the read bitline leakage current[17], a regular six transister (6 T) SRAM track typically provided by the foundry can not be scaled to sub / near threshold regions. For embedded chips in portable or wearable electronics, designing Ultra-low-power SRAM circuits is therefore vital. The topology of the SRAM cell is revamped to allow more transistors to maximize the read static noise gap, also to boost write performance, and reduce the read bitline leakage present. However, the compilers of the memory must be designed in a complicated and custom way, given the existence of analog and analog signals in the SRAM array as pre-loaded circuitry and sensor . The architecture of the standard cell- based memory (SCM) circuit is an alternative to performing ultra-low power operations for SRAM circuits[19]. By using regular logic cells to construct the SRAM modules, all inputs and outputs are electrical signals. Peripheral electronics can also be fully implemented for automated model cells. The current EDA software can therefore be used to conduct logic synthesis as well as automated positioning and routing to produce the net list and configuration of the necessary SRAM arrays. The rapid generation of these SRAM arrays is highly desirable for those embedded system applications where a large number of different sized memory circuits are needed. In comparison, read and write operations are performed similarly through the use of modern standard cells as the signal transmission in traditional combinational circuits, which guarantees high data reliability and good write capacity. The biggest problem with the SCM cells is the large area of each cell overhead. Compared to conventional 6 T SRAM cell, the layout region of each SCM cell could be two to three times greater. Nevertheless, the area output of the total SRAM system could be even higher with the regular cell-based SRAM circuit relative to the previously published ultra-low voltage SRAM circuits. It happens when there is relatively little size of the memory array so the peripheral circuit greatly contributes to the entire array area [7]. A novel robust 12 T standard cell based SRAM cell for ultra-low-voltage ultra-low-power applications is proposed in this article. The circuit is powered at a lower supply voltage to minimize leakage in Complementary Metal Oxide Systems (CMOS), which, in effect, slower the circuit speed. Delay can be minimized using lower

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ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 threshold voltage transistors, but this reduces the flow rate again (mainly the flow cycle). Contrary conditions exist and the construction of a memory cell with a low standing leak and reasonable reliability requires good optimization. Higher voltages and smaller measurements induce important data reliability loss in cells. In order to achieve high range performance and low write energy consumption, three transistors are used on every column of SRAM cells. During the three-stage reading cycle, reading delays and power consumption are minimized. In addition, parallel cross-coupling feedback with the proposed SRAM 12 T cell, ensures high data stability and writing ability.

That is how the paper is arranged. Section II reviews previously published SRAM standard cell-based circuits. Sections III in which the problem statement was depicted and Section IV present and evaluate proposed novel 12 T standard cell-based SRAM circuit. Section V depicts the summary of the paper.

II. LITERATURE SURVEY

In [1] a modern 12 T memory cell that is energy-efficient is suggested to help architecture hardened radiation (RHD) in close-to-threshold voltage resistance multi-node (SEMNU) single-event upsets. Through monitoring cross-coupled PMOS devices of inverters through foolish access transistors, the radiation complexity of the proposed storage cell will be increased. In STMicroelectronics 6, we validated the proposed memory cell. In [2] they propose an overall reduction in the amount of VMIN and resources per service with a 12 ST-based SRAM-bit cell to promote the process variance sensitive write- capability. In [3] a halve select 12 T SRAM free cell features an input cutting tool to enhance the ability to write and separate reading paths in order to improve reading stability. The read and write capabilities are 1.95 and 2.84 respectively better than the normal 6 T cell at 0.4 V, respectively. In [4] Present the SRAM, a compiler that targets small to media array sizes and provides a smaller area solution compared to traditional 6T-based SRAMs, with the ultra low Voltage one-port random access memory. The design uses a 12 T write and the read upset free bit-cell. Array architecture uses a read-modifying writing scheme to enable masking and multiplexing columns for bit-write (BW). The Built-inside Self-Test (BIST) and Synchronous Writing Through (SWT) methods have testability, while the Sleep-and Shutdown Methods Power Management (PM) alternative is included. In [5] a 9-Transistor (TG9 T) SRAM bitcell power-efficient transmission gate has been proposed. In [6] Optimized MTJ (Approximate Calculation Application (AC) Procedure, focused on resistive ternary information addressable memory (ReTCAM). In [7] a new 12 T SRAM cell is introduced that is used to improve reliability with an Schmitt control circuit and to reduce the leakage current in standby mode with a transistor. In [8] discusses the phenomenon of crucial linear transfer of energy (LET) and the charge obtained by scaling the technology of each circuit. In [9] Propose modified 12 T SRAM cell (WWL12 T) FinFET and self refreshing. To increase the FinFET's reliability and performance, the double-k gate isolator and symmetric distance is used.. In [10] the 12 T static random access memory (SRAM) cell dependent on the one-ended Schmitt signal (ST). Cross-point data-conscious writing framework is used in the planned cell and therefore promotes interlocking architecture to minimize soft errors. The proposed cell is not interrupted by reading because the bit line is completely isolated from the node. In [11] presents a 12 T 2RW SRAM low voltage with parallel exposure and blocked interruption to improve the performance without degradation. The suggested SRAM cell reduces interference by splitting reading from internal nodes and minimizes the probability of worst case stability with a 6 percent region cost. Furthermore, hierarchical bitlines, a virtual ground technology and the minimum voltage and energy consumption will be further reduced. In [12] the design based on the 12 transistor (12 T) cell is proposed for the low power and variability-aware static random access memory (SRAM). In [13] an advanced 12 T Static Random Access Memory (SRAM) cell with the following advantages: decreased leakage current and increased efficiency utilizing 180NM Technology was proposed. In [14] Presents a 9 T static random access memory (SRAM) cell with a single-ended Schmitt signal. The architecture suggested offers improved reading stability when ST-based inverters are used. In [15] The introduction of the Schmitt Trigger (ST) enhanced switching functionality, reduced the power outages and increased the SNM. Upon applying the memistor to the SRAM trigger Schmitt, the cell was not fragile and the SNM improved more.

III. PROBLEM STATEMENT

The SRAM technology suffered a lot due to leakage issues. There are several other existing technologies that are there, but they are all not useful. Hence there is a need for an effective method to overcome the leakage issues in the SRAM technology. We would propose a new SCM with parallel cross-coupling logic that will reduce expenses, time, power, and memory complexity.

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ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 IV. PROPOSED METHODOLOGY

This portion proposes to decrease write and read energy consumption in order to maintain high data reliability and write skills on the current 12 T SCM low power circuit. With the use of advanced 65-nm CMOS materials, all transistors in SRAM cells use minimum channel width (80 nm) and channel length (60 nm). Each column of SRAM cells shares the three transistors and . The proposed SRAM cell could be designed and described as a standard cell for physical design. and are treated in a similar manner to the sleep transistors used during positioning and routing.

Figure 1 Schematic representation of the proposed methodology

It consists of a block that can handle 4 bits . Such 4 bits are interpreted by 4 pairs of intertwined cross coupled inverters, gate transistors, mask transistors, writer entry transistors and a read buffer. This read buffer is based on the stacked nMOS configuration theory. This configuration is done to prevent leakage voltage. It consists of a line to pick the signal you need called BPS[ Block Pick Signal]. The typical 12T cell process is carried on as follows. BPS is set to 0V to enforce write operation. And therefore the word line is permitted. Likewise, BPS is set at 1V for a read operation, and the word line is disabled. Thus the line of terms serves as an ON-OFF turn.

For LBL discharge, a service voltage VDD is carried. This will shut the read buffers off, in effect. In the meantime, word lines are kept at 0V, the RBLs are preloaded to full VDD supply voltage. The block mask transistors are forced to remain in the OFF place in the read process. The word line is disabled to hold the transistors in ON place for the transfer doors. As a consequence, the data stored in a single cell is passed from LBL to the RBL via the pass gate transistor. Once the data is stored, it discharges the RBLs. These RBLs are located on the blocks of the given row and column. Once the read process terminates word lines are held at 0V to transistors OFF pass-gate. The best way to minimize energy consumption through the use of 12T SRAM is to do so. This novel configuration is built. It minimizes energy consumption as a result of standby, read wait, writing delays, etc. Experimentally demonstrated by implementing the parallel cross coupling logic in 12 T SRAM which is the best way to save energy use and operating delays.

With lower processing nodes, the capacity of a memory cell is also minimized. The current memory cell leakage factor will be increased thereby. The intersection of leakage, gate leakage and multi-threshold leakage current are several additives that trigger the 12 T SRAM cell leakage. However in lower-technology, multi-threshold leakage is prevalent. When the leakage current is off, the transistor gate voltage is less than the voltage at its highest and consists mainly of a diffusion stream; the transistor gate voltage is the lowest. It is represented by the following equation,

= (W/L)(KT/Q)^2(N-1) exp[q( ( ) (1)

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The circuit for a MT-CMOS 12 T cell is shown in Figure 4. This comprises of M6 transistors. BL and RBL, are also used. Such act as input / output lines from the memory cell. The cell leakage element must be calculated for estimation. The cell ratio is the reader-sized ratio to the connection transistor during processing, and the PR-to-access ratio is the load-transistor ratio across the whole write activity.

During Read operation,

( ) (2)

During write operation

( ) ( ) (3)

Where CR is the cell ratio and PuR is he pull up ratio. In this architecture we try to analyze in 12T SRAM, the bit-lined complex energy consumption of every write process. To encourage this, we analyze as an illustration two columns of SRAM cells (i.e. 4-bit lines). Each SRAM cell has been loaded to the GND (ground) since a write process. Two bit lines from GND to VDD should be paid after this written service. The complex energy consumption is therefore estimated for a 12T SRAM cell.

* + (4)

With respect to our 12T-SRAM cells suggested, 4 bit voltages are VDD, 1⁄2 VDD, 1⁄2 VDD, and GND after a written process. As the only 1⁄2 VDD to VDD line is expected to charge, a complex power consumption is induced by the robust 12T SRAM cell.

= ¼ C* =1/4 (5)

It can be seen from the above calculation that the planned system would reduce the electricity consumption. The projected power consumption is less than typical 6 T or 8 T owing to leakage of power consumption.

LEAKAGE POWER CALCULATION

Multi-threshold leakage and gate leakage are the main sources of SRAM leakage capacity. This is where a technique for the elimination of multi-threshold leakage and the leakage of robust 12T-SRAM cells is implemented and suggested. Nonetheless, the leakage present is less than 8 percent of total power, even if body distortion is introduced. Therefore, eliminating leakage is not our original design intent. The potential energy usage of 12 T leakage is less than the conventional system. The small energy consumption difference was found due to the different pre-loaded bitline voltages. In a Robust 12- T SRAM data manager, bit lines BL1 and BL1 N are preloaded onto "1" and word line write on "0" while the gate-leakage is induced from the source to the gate by the CMOS transistor switch.

= + (6)

V. RESULT AND DISCUSSION

The new method results in an effective 12 T SRAM network for power consumption, and the research that is being developed further shows that 12T cells can be extremely valuable for modeling SRAM cells relative to standby, read-and-write operation. The tool is used for cadence design systems.

Differing temperature conditions in standby mode are established in the power dissipation capacity of the proposed cell along with proposed robust 12T SRAM Cell. The measured dissipation of the current depends upon the differed temperature. Figure 2 provides an analysis of the temperature in various SRAM cell types.

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Figure 2 Power Dissipation at Different Temperature

Figure 3 The read and write delays of the SCM arrays

From the figure 3 note that the propagation delay of the robust 12T SCM circuit is still shorter compared to the conventional circuit due to the significantly longer read access delay of the conventional SCM circuit.

The leakage power consumption of the memory arrays in idle mode is shown in Figure 4. To minimize the layout area of the memory cell, the minimum channel length is used for all the transistors in the proposed robust 12T SCM cell. The leakage power consumption of the proposed 12T SCM array is therefore slightly higher compared to the conventional memory array. When the supply voltage scales down to 0.1 V, the leakage overhead with the 12T SCM array increases from 0.7% to 8.9%, compared to the conventional memory array.

Figure 4 The leakage power consumption

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ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 VI. CONCLUSION

The Cadence method for SRAM cells has been developed and modeled here. The results from the simulation showed that the 12 T SRAM cell circuits proposed decreased leakage. With increasing supply voltages and increased temperatures with specific supply voltage, leak power increases. Total power use is also substantially reduced for all planned loops. Nevertheless, the trustworthiness of the proposed circuits is jeopardized because leakage is minimized for the individual states in the proposed circuit. It makes the use of low-power 12T SRAMs.

VII. REFERENCES

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ISSN- 2394-5125 VOL 7, ISSUE 19, 2020 [20] Wang, X., Lu, C., & Mao, Z. (2016). Charge recycling 8T SRAM design for low voltage robust operation. AEU - International Journal of Electronics and Communications, 70(1), 25–32. doi:10.1016/j.aeue.2015.09.014 [21] Ahmad, S., Ahmad, S. A., Muqeem, M., Alam, N., & Hasan, M. (2019). TFET-Based Robust 7T SRAM Cell for Low Power Application. IEEE Transactions on Electron Devices, 66(9), 3834-3840.

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