Intel® Intel® PXA255 Processor
Design Guide
March, 2003
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ii Intel® PXA255 Processor Design Guide Contents
Contents
1 Introduction...... 1-1 1.1 Functional Overview ...... 1-1 1.2 Package Information...... 1-2 1.2.1 Package Introduction ...... 1-2 1.2.2 Signal Pin Descriptions...... 1-3 2 System Memory Interface ...... 2-1 2.1 Overview...... 2-1 2.2 SDRAM Interface...... 2-3 2.3 SDRAM memory wiring diagram ...... 2-4 2.4 SDRAM Support ...... 2-5 2.5 SDRAM Address Mapping...... 2-6 2.6 Static Memory...... 2-7 2.6.1 Overview...... 2-7 2.6.2 Boot Time Defaults ...... 2-8 2.6.3 Flash Memory ...... 2-9 2.6.3.1 Synchronous Intel® StrataFlash® Memory Reset ...... 2-9 2.6.4 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options ...... 2-9 2.6.5 Variable Latency I/O Interface Overview ...... 2-10 2.6.6 External Logic for PCMCIA Implementation ...... 2-12 2.6.7 DMA / Companion Chip Interface ...... 2-15 2.7 System Memory Layout Guidelines ...... 2-18 2.7.1 System Memory Topologies (Min and Max Simulated Loading)...... 2-18 2.7.2 System Memory Recommended Trace Lengths...... 2-19 3 LCD Display Controller ...... 3-1 3.1 LCD Display Overview...... 3-1 3.2 Passive (DSTN) Displays ...... 3-1 3.2.1 Typical Connections for Passive Panel Displays...... 3-2 3.2.1.1 Passive Monochrome Single Panel Displays...... 3-2 3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data...... 3-3 3.2.1.3 Passive Monochrome Dual Panel Displays ...... 3-3 3.2.1.4 Passive Color Single Panel Displays ...... 3-4 3.2.1.5 Passive Color Dual Panel Displays...... 3-4 3.3 Active (TFT) Displays ...... 3-5 3.3.1 Typical connections for Active Panel Displays...... 3-6 3.4 PXA255 processor Pinout...... 3-7 3.5 Additional Design Considerations...... 3-8 3.5.1 Contrast Voltage ...... 3-8 3.5.2 Backlight Inverter ...... 3-8 3.5.3 Signal Routing and Buffering ...... 3-8 3.5.4 Panel Connector ...... 3-9 4 USB Interface ...... 4-1 4.1 Self Powered Device ...... 4-1 4.1.1 Operation if GPIOn and GPIOx are Different Pins...... 4-1 4.1.2 Operation if GPIOn and GPIOx are the Same Pin...... 4-2
Intel® PXA255 Processor Design Guide iii Contents
4.2 Bus Powered Device ...... 4-2 5 MultiMediaCard (MMC)...... 5-1 5.1 Schematics ...... 5-1 5.1.1 Signal Description...... 5-1 5.1.2 How to Wire ...... 5-2 5.1.2.1 SDCard Socket ...... 5-4 5.1.2.2 MMC Socket ...... 5-4 5.1.3 Simplified Schematic ...... 5-5 5.1.4 Pull-up and Pull-down...... 5-5 5.2 Utilized Features...... 5-6 6AC97...... 6-1 6.1 Schematics ...... 6-1 6.2 Layout...... 6-2 7I2C...... 7-1 7.1 Schematics ...... 7-1 7.1.1 Signal Description...... 7-1 7.1.2 Digital-to-Analog Converter (DAC) ...... 7-2 7.1.3 Other Uses of I2C...... 7-2 7.1.4 Pull-Ups and Pull-Downs...... 7-3 7.2 Utilized Features...... 7-4 8 Power and Clocking ...... 8-1 8.1 Operating Conditions...... 8-1 8.2 Electrical Specifications...... 8-2 8.2.1 Power Supply Connectivity...... 8-2 8.3 Example Form Factor Reference Design Power Delivery Example ...... 8-7 8.3.1 Power System...... 8-7 8.3.1.1 Power System Configuration ...... 8-8 8.3.2 CORE Power ...... 8-9 8.3.3 PLL Power ...... 8-9 8.3.4 I/O 3.3 V Power ...... 8-9 8.3.5 Peripheral 5.5 V Power...... 8-9 9 JTAG/Debug Port...... 9-1 9.1 Description...... 9-1 9.2 Schematics ...... 9-1 9.3 Layout...... 9-2 A SA-1110/Processor Migration...... A-1 A.1 SA-1110 Hardware Migration Issues...... A-2 A.1.1 Hardware Compatibility...... A-2 A.1.2 Signal Changes ...... A-2 A.1.3 Power Delivery...... A-4 A.1.4 Package...... A-4 A.1.5 Clocks...... A-4 A.1.6 UCB1300 ...... A-4 A.2 SA-1110 to PXA255 Processor Software Migration Issues...... A-5 A.2.1 Software Compatibility...... A-5
iv Intel® PXA255 Processor Design Guide Contents
A.2.2 Address space ...... A-5 A.2.3 Page Table Changes ...... A-6 A.2.4 Configuration registers...... A-6 A.2.5 DMA...... A-6 A.3 Using New PXA255 Processor Features...... A-7 A.3.1 Intel® XScale™ Microarchitecture...... A-7 A.3.2 Debugging ...... A-8 A.3.3 Cache Attributes ...... A-8 A.3.4 Other features...... A-8 A.3.5 Conclusion ...... A-8 B Example Form Factor Reference Design Schematic Diagrams ...... B-1 B.1 Notes ...... B-1 B.2 Schematic Diagrams...... B-1 C BBPXA2xx Development Baseboard Schematic Diagram ...... C-1 C.1 Schematic Diagram ...... C-1 D PXA250 Processor Card Schematic Diagram ...... D-1 D.1 Schematic Diagram ...... D-1
Intel® PXA255 Processor Design Guide v Contents
Figures 1-1 Processor Block Diagram...... 1-2 1-2 PXA255 Processor ...... 1-13 2-1 General Memory Interface Configuration ...... 2-2 2-2 SDRAM Memory System Example...... 2-4 2-3 Flash Memory Reset Using State Machine ...... 2-9 2-4 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...... 2-9 2-5 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)...... 2-11 2-6 Expansion Card External Logic for a Two-Socket Configuration...... 2-13 2-7 Expansion Card External Logic for a One-Socket Configuration...... 2-14 2-8 Alternate Bus Master Mode...... 2-16 2-9 Variable Latency I/O...... 2-17 2-10 CS, CKE, DQM, CLK, MA minimum loading topology...... 2-18 2-11 CS, CKE, DQM, CLK, MA Maximum Loading Topology ...... 2-18 2-12 MD Minimum Loading Topology...... 2-18 2-13 MD maximum loading topology ...... 2-19 3-1 Single Panel Monochrome Passive Display Typical Connection ...... 3-3 3-2 Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection...... 3-3 3-3 Passive Monochrome Dual Panel Displays Typical Connection ...... 3-4 3-4 Passive Color Single Panel Displays Typical Connection...... 3-4 3-5 Passive Color Dual Panel Displays Typical Connection...... 3-5 3-6 Active Color Display Typical Connection...... 3-7 4-1 Self Powered Device ...... 4-1 5-1 Processor MMC and SDCard Signal Connections...... 5-3 5-2 Processor MMC to SDCard Simplified Signal Connection ...... 5-5 6-1 AC97 connection ...... 6-1 7-1 Linear Technology DAC with I2C Interface ...... 7-2 7-2 Using an Analog Switch to Allow a Second CF Card ...... 7-3 7-3 I2C Pull-Ups and Pull-Downs ...... 7-3 8-1 Example Form Factor Reference Design Power System Design...... 8-8 9-1 JTAG/Debug Port Wiring Diagram ...... 9-1
Tables 1-1 Related Documentation...... 1-1 1-2 Pin & Signal Descriptions for the PXA255 Processor ...... 1-3 1-3 Pin Description Notes...... 1-12 1-4 PXA255 Processor Pinout — Ballpad Number Order ...... 1-14 2-1 Memory Address Map ...... 2-3 2-2 SDRAM Memory Types Supported by the Processor...... 2-5 2-3 Normal Mode Memory Address Mapping...... 2-6 2-4 Processor Compatibility Mode Address Line Mapping...... 2-7 2-5 Valid Booting Configurations Based for the PXA255 processor ...... 2-8 2-6 BOOT_SEL Definitions ...... 2-8 2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications...... 2-10 2-8 Variable Latency I/O Interface AC Specifications ...... 2-11 2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications ...... 2-14 2-10 Minimum and Maximum Trace Lengths for the SDRAM Signals ...... 2-19 3-1 LCD Controller Data Pin Utilization ...... 3-1
vi Intel® PXA255 Processor Design Guide Contents
3-2 Passive Display Pins Required ...... 3-2 3-3 Active Display Pins Required ...... 3-6 3-4 PXA255 processor LCD Controller Ball Positions...... 3-7 5-1 MMC Signal Description...... 5-1 5-2 SDCard Socket Signals...... 5-2 5-3 MMC Controller Supported Sockets and Devices...... 5-2 5-4 SDCard Pull-up and Pull-down Resistors...... 5-6 5-5 MMC Pull-up and Pull-down Resistors...... 5-6 7-1 I2C Signal Description...... 7-1 8-1 Voltage, Temperature, and Frequency Electrical Specifications...... 8-1 8-2 Absolute Maximum Ratings...... 8-2 8-3 PXA255 Processor VCCN vs. VCCQ...... 8-2
Intel® PXA255 Processor Design Guide vii Contents
Revision History
Date Revision Description
January 2003 -001 Initial Release
viii Intel® PXA255 Processor Design Guide Introduction 1
This document presents design recommendations, board schematics, and debug recommendations for the Intel® PXA255 Processor (PXA255 processor). The PXA255 processor is a 32-bit device.
The guidelines presented in this document ensure maximum flexibility for board designers, while reducing the risk of board-related issues. Use the schematics in Appendix B, “Example Form Factor Reference Design Schematic Diagrams” as a reference for your own design. While the included schematics cover a specific design, the core schematics remain the same for most PXA255 processor based platforms. Consult the debug recommendations when debugging a processor based system. To ensure the correct implementation of the debug port (refer to Section 9 for more information), these debug recommendations should be understood before completing a board design, in addition to other debug features.
Table 1-1. Related Documentation
Document Title Order Number
Intel® PXA255 Processor Developer’s Manual 278693 Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification 278695
1.1 Functional Overview
The PXA255 processor is an integrated system-on-a-chip design based on the Intel® XScale™ microarchitecture. The PXA255 processor integrates the Intel® XScale™ microarchitecture core with many peripherals to let you design products for the handheld market.
Figure 1-1 on page 1-2 is a block diagram of the processor.
Intel® PXA255 Processor Design Guide 1-1 Introduction
s Figure 1-1. Processor Block Diagram
RTC Color or Grayscale Memory OS Timer LCD Controller Controller PWM(2) Int. Controller Clocks & Variable Power Man. Latency I/O ASIC I2S System Bus Control
I2C PCMCIA Socket 0
and Bridge & CF XCVR Peripheral Bus Socket 1 AC97 DMA Controller Control
UARTs Dynamic SDRAM/ SMROM
General Purpose I/O Memory 4 banks NSSP IntelÆ XScaleô Control Microarchitecture Slow IrDA ROM/ Static Flash/ Memory SRAM Fast IrDA Control 4 banks SSP 3.6864 32.768 USB Client MHz KHz Osc Osc MMC
The PXA255 processor package is: 256 pin, 17x17 mBGA – 32-bit functionality.
Section 1.2.1, “Package Introduction” contains a breakdown of the features supported by the PXA255 processor.
1.2 Package Information
This section describes the package, pinout, and signal descriptions.
1.2.1 Package Introduction
Features of the PXA255 processor are: • Core frequencies supported - 100 MHz - 400 MHz • System memory interface —100MHz SDRAM — 4 MB to 256 MB of SDRAM memory — Support for 16, 64, 128, or 256 Mbit DRAM technologies
1-2 Intel® PXA255 Processor Design Guide Introduction
— 4 Banks of SDRAM, each supporting 64 MB of memory — Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh) — Supports as many as 6 static memory devices (SRAM, Flash, or VLIO) • PCMCIA/Compact Flash card control pins • LCD Controller pins • Full Function UART • Bluetooth UART • Hardware UART • MMC Controller pins • SSP Pins • Network SSP Pins • USB Client Pins • AC'97 Controller Pins • Standard UART Pins • I2C Controller pins • PWM pins • 15 dedicated GPIOs pins • Integrated JTAG support
1.2.2 Signal Pin Descriptions
Table 1-2 defines the signal descriptions for the processor.
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
Memory Controller Pins Memory address bus. (output) Signals the address MA[25:0] OCZ Driven Low Driven Low requested for memory accesses. Memory data bus. (input/output) Lower 16 bits of the MD[15:0] ICOCZ Hi-Z Driven Low data bus. Memory data bus. (input/output) Used for 32-bit MD[31:16] ICOCZ Hi-Z Driven Low memories. Memory output enable. (output) Connect to the output nOE OCZ Driven High Note [4] enables of memory devices to control data bus drivers. Memory write enable. (output) Connect to the write nWE OCZ Driven High Note [4] enables of memory devices. SDRAM CS for banks 3 through 0. (output) Connect to nSDCS[3:0] OCZ the chip select (CS) pins for SDRAM. For the PXA255 Driven High Note [5] processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot. SDRAM DQM for data bytes 3 through 0. (output) DQM[3:0] OCZ Connect to the data output mask enables (DQM) for Driven Low Driven Low SDRAM.
Intel® PXA255 Processor Design Guide 1-3 Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
SDRAM RAS. (output) Connect to the row address nSDRAS OCZ Driven High Driven High strobe (RAS) pins for all banks of SDRAM. SDRAM CAS. (output) Connect to the column address nSDCAS OCZ Driven High Driven High strobe (CAS) pins for all banks of SDRAM. Synchronous Static Memory clock enable. (output) SDCKE[0] OC Connect to the CKE pins of SMROM. The memory Driven Low Driven Low controller provides control register bits for deassertion. SDRAM and/or Synchronous Static Memory clock enable. (output) Connect to the clock enable pins of SDCKE[1] OC SDRAM. It is deasserted during sleep. SDCKE[1] is Driven low Driven low always deasserted upon reset. The memory controller provides control register bits for deassertion. Synchronous Static Memory clock. (output) Connect to the clock (CLK) pins of SMROM. It is driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be SDCLK[0] OC turned off via free running control register bits in the memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static memory bank 0 is configured for SMROM. SDCLK[1] OCZ SDRAM Clocks (output) Connect SDCLK[1] and Driven Low Driven Low SDCLK[2] to the clock pins of SDRAM in bank pairs 0/1 and 2/3, respectively. They are driven by either the internal memory controller clock, or the internal memory controller clock divided by 2. At reset, all clock pins are free running at the divide by 2 clock speed and may be SDCLK[2] OCturned off via free running control register bits in the Driven Low Driven Low memory controller. The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin. SDCLK[2:1] control register assertion bits are always deasserted upon reset. nCS[5]/ ICOCZ GPIO[33] nCS[4]/ ICOCZ GPIO[80] Static chip selects. (output) Chip selects to static nCS[3]/ memory devices such as ROM and Flash. Individually ICOCZ Hi-Z - Note [1] Note [4] GPIO[79] programmable in the memory configuration registers. nCS[5:0] can be used with variable latency I/O devices. nCS[2]/ ICOCZ GPIO[78] nCS[1]/ ICOCZ GPIO[15] Static chip select 0. (output) Chip select for the boot nCS[0] ICOCZ Driven High Note [4] memory. nCS[0] is a dedicated pin. Read/Write for static interface. (output) Signals that the RD/nWR OCZ Driven Low Holds last state current transaction is a read or write.
RDY/ Variable Latency I/O Ready pin. (input) Notifies the ICOCZ memory controller when an external bus device is ready Hi-Z - Note [1] Note [3] GPIO[18] to transfer data.
1-4 Intel® PXA255 Processor Design Guide Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. L_DD[8]/ ICOCZ Memory Controller alternate bus master request. Hi-Z - Note [1] Note [3] GPIO[66] (input) Allows an external device to request the system bus from the Memory Controller. LCD display data. (output) Transfers pixel information L_DD[15]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[73] Memory Controller grant. (output) Notifies an external device that it has been granted the system bus. MBGNT/ Memory Controller grant. (output) Notifies an external ICOCZ Hi-Z - Note [1] Note [3] GP[13] device that it has been granted the system bus. Memory Controller alternate bus master request. MBREQ/ ICOCZ (input) Allows an external device to request the system Hi-Z - Note [1] Note [3] GP[14] bus from the Memory Controller. PCMCIA/CF Control Pins
nPOE/ PCMCIA output enable. (output) Reads from PCMCIA ICOCZ Hi-Z - Note [1] Note [5] GPIO[48] memory and to PCMCIA attribute space.
nPWE/ PCMCIA write enable. (output) Performs writes to ICOCZ PCMCIA memory and to PCMCIA attribute space. Also Hi-Z - Note [1] Note [5] GPIO[49] used as the write enable signal for Variable Latency I/O.
nPIOW/ PCMCIA I/O write. (output) Performs write transactions ICOCZ Hi-Z - Note [1] Note [5] GPIO[51] to PCMCIA I/O space.
nPIOR/ PCMCIA I/O read. (output) Performs read transactions ICOCZ Hi-Z - Note [1] Note [5] GPIO[50] from PCMCIA I/O space. PCMCIA card enable 2. (output) Selects a PCMCIA card. nPCE[2] enables the high byte lane and nPCE[1] nPCE[2]/ ICOCZ enables the low byte lane. Hi-Z - Note [1] Note [5] GPIO[53] MMC clock. (output) Clock signal for the MMC Controller.
nPCE[1]/ PCMCIA card enable 1. (outputs) Selects a PCMCIA ICOCZ card. nPCE[2] enables the high byte lane and nPCE[1] Hi-Z - Note [1] Note [5] GPIO[52] enables the low byte lane.
nIOIS16/ IO Select 16. (input) Acknowledge from the PCMCIA ICOCZ card that the current address is a valid 16 bit wide I/O Hi-Z - Note [1] Note [5] GPIO[57] address.
nPWAIT/ PCMCIA wait. (input) Driven low by the PCMCIA card to ICOCZ extend the length of the transfers to/from the PXA255 Hi-Z - Note [1] Note [5] GPIO[56] processor. PCMCIA socket select. (output) Used by external steering logic to route control, address, and data signals PSKTSEL/ to one of the two PCMCIA sockets. When PSKTSEL is ICOCZ Hi-Z - Note [1] Note [5] GPIO[54] low, socket zero is selected. When PSKTSEL is high, socket one is selected. Has the same timing as the address bus.
nPREG/ PCMCIA Register select. (output) Indicates that the ICOCZ target address on a memory transaction is attribute Hi-Z - Note [1] Note [5] GPIO[55] space. Has the same timing as the address bus.
Intel® PXA255 Processor Design Guide 1-5 Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
LCD Controller Pins
L_DD(7:0)/ LCD display data. (outputs) Transfers pixel information ICOCZ Hi-Z - Note [1] Note [3] GPIO[65:58] from the LCD Controller to the external LCD panel. LCD display data. (output) Transfers pixel information from the LCD Controller to the external LCD panel. L_DD[8]/ ICOCZ Memory Controller alternate bus master request. Hi-Z - Note [1] Note [3] GPIO[66] (input) Allows an external device to request the system bus from the Memory Controller. LCD display data. (output) Transfers pixel information L_DD[9]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[67] MMC chip select 0. (output) Chip select 0 for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[10]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[68] MMC chip select 1. (output) Chip select 1 for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[11]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[69] MMC clock. (output) Clock for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[12]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[70] RTC clock. (output) Real time clock 1 Hz tick. LCD display data. (output) Transfers pixel information L_DD[13]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[71] 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. LCD display data. (output) Transfers pixel information L_DD[14]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[72] 32 kHz clock. (output) Output from the 32 kHz oscillator. LCD display data. (output) Transfers pixel information L_DD[15]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[73] Memory Controller grant. (output) Notifies an external device it has been granted the system bus.
L_FCLK/ LCD frame clock. (output) Indicates the start of a new ICOCZ Hi-Z - Note [1] Note [3] GPIO[74] frame. Also referred to as Vsync.
L_LCLK/ LCD line clock. (output) Indicates the start of a new line. ICOCZ Hi-Z - Note [1] Note [3] GPIO[75] Also referred to as Hsync.
L_PCLK/ LCD pixel clock. (output) Clocks valid pixel data into the ICOCZ Hi-Z - Note [1] Note [3] GPIO[76] LCD’s line shift buffer.
L_BIAS/ AC bias drive. (output) Notifies the panel to change the ICOCZ polarity for some passive LCD panel. For TFT panels, Hi-Z - Note [1] Note [3] GPIO[77] this signal indicates valid pixel data. Full Function UART Pins Full Function UART Receive. (input) FFRXD/ ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Hi-Z - Note [1] Note [3] GPIO[34] Controller.
1-6 Intel® PXA255 Processor Design Guide Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
Full Function UART Transmit. (output) FFTXD/ ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Hi-Z - Note [1] Note [3] GPIO[39] Controller. FFCTS/ ICOCZ Full Function UART Clear-to-Send. (input) Hi-Z - Note [1] Note [3] GPIO[35] FFDCD/ ICOCZ Full Function UART Data-Carrier-Detect. (input) Hi-Z - Note [1] Note [3] GPIO[36] FFDSR/ ICOCZ Full Function UART Data-Set-Ready. (input) Hi-Z - Note [1] Note [3] GPIO[37] FFRI/ ICOCZ Full Function UART Ring Indicator. (input) Hi-Z - Note [1] Note [3] GPIO[38] FFDTR/ ICOCZ Full Function UART Data-Terminal-Ready. (output) Hi-Z - Note [1] Note [3] GPIO[40] FFRTS/ ICOCZ Full Function UART Request-to-Send. (output) Hi-Z - Note [1] Note [3] GPIO[41] Bluetooth UART Pins BTRXD/ ICOCZ Bluetooth UART Receive. (input) Hi-Z - Note [1] Note [3] GPIO[42] BTTXD/ ICOCZ Bluetooth UART Transmit. (output) Hi-Z - Note [1] Note [3] GPIO[43] BTCTS/ ICOCZ Bluetooth UART Clear-to-Send. (input) Hi-Z - Note [1] Note [3] GPIO[44] BTRTS/ ICOCZ Bluetooth UART Data-Terminal-Ready. (output) Hi-Z - Note [1] Note [3] GPIO[45] Standard UART and ICP Pins IrDA receive signal. (input) Receive pin for the FIR IRRXD/ ICOCZ function. Hi-Z - Note [1] Note [3] GPIO[46] Standard UART receive. (input) IrDA transmit signal. (output) Transmit pin for the IRTXD/ ICOCZ Standard UART, SIR and FIR functions. Hi-Z - Note [1] Note [3] GPIO[47] Standard UART transmit. (output) HWUART Pins
HWTXD/ Pulled High ICOCZ Hardware UART Transmit Data. Note [3] GPIO[48] Note [1]
HWRXD/ Pulled High ICOCZ Hardware UART Receive Data. Note [3] GPIO[49] Note [1]
HWCTS/ Pulled High ICOCZ Hardware UART Clear-To-Send. Note [3] GPIO[50] Note [1]
HWRTS/ Pulled High ICOCZ Hardware UART Request-to-Send. Note [3] GPIO[51] Note [1] MMC Controller Pins MMCMD ICOCZ Multimedia Card Command. (bidirectional) Hi-Z Hi-Z
Intel® PXA255 Processor Design Guide 1-7 Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
MMDAT ICOCZ Multimedia Card Data. (bidirectional) Hi-Z Hi-Z PCMCIA card enable 2. (outputs) Selects a PCMCIA card. Bit one enables the high byte lane and bit zero nPCE[2]/ ICOCZ enables the low byte lane. Hi-Z - Note [1] Note [5] GPIO[53] MMC clock. (output) Clock signal for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[9]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[67] MMC chip select 0. (output) Chip select 0 for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[10]/ from the LCD Controller to the external LCD panel. ICOCZ Hi-Z - Note [1] Note [3] GPIO[68] MMC chip select 1. (output) Chip select 1 for the MMC Controller. LCD display data. (output) Transfers pixel information L_DD[11]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[69] MMC clock. (output) Clock for the MMC Controller. Full Function UART Receive. (input) FFRXD/ ICOCZ MMC chip select 0. (output) Chip select 0 for the MMC Hi-Z - Note [1] Note [3] GPIO[34] Controller. Full Function UART Transmit. (output) FFTXD/ ICOCZ MMC chip select 1. (output) Chip select 1 for the MMC Hi-Z - Note [1] Note [3] GPIO[39] Controller. MMCCLK/ MMC clock. (output) Clock signal for the MMC ICOCZ Hi-Z - Note [1] Note [3] GP[6] Controller. MMCCS0/ MMC chip select 0. (output) Chip select 0 for the MMC ICOCZ Hi-Z - Note [1] Note [3] GP[8] Controller. MMCCS1/ MMC chip select 1. (output) Chip select 1 for the MMC ICOCZ Hi-Z - Note [1] Note [3] GP[9] Controller. SSP Pins SSPSCLK/ ICOCZ Synchronous Serial Port Clock. (output) Hi-Z - Note [1] Note [3] GPIO[23] SSPSFRM/ ICOCZ Synchronous Serial Port Frame. (output) Hi-Z - Note [1] Note [3] GPIO[24] SSPTXD/ ICOCZ Synchronous Serial Port Transmit. (output) Hi-Z - Note [1] Note [3] GPIO[25] SSPRXD/ ICOCZ Synchronous Serial Port Receive. (input) Hi-Z - Note [1] Note [3] GPIO[26] SSPEXTCLK/ ICOCZ Synchronous Serial Port External Clock. (input) Hi-Z - Note [1] Note [3] GPIO[27] Network SSP pins
NSSPSCLK/ Pulled High ICOCZ Network Synchronous Serial Port Clock. Note [3] GPIO[81] Note [1]
NSSPSFRM/ Pulled High ICOCZ Network Synchronous Serial Port Frame Signal. Note [3] GPIO[82] Note [1]
1-8 Intel® PXA255 Processor Design Guide Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
NSSPTXD/ Pulled High ICOCZ Network Synchronous Serial Port Transmit. Note [3] GPIO[83] Note [1]
NSSPRXD/ Pulled High ICOCZ Network Synchronous Serial Port Receive. Note [3] GPIO[84] Note [1] USB Client Pins USB_P IAOAZ USB Client Positive. (bidirectional) Hi-Z Hi-Z USB_N IAOAZ USB Client Negative pin. (bidirectional) Hi-Z Hi-Z AC97 Controller and I2S Controller Pins AC97 Audio Port bit clock. (input) AC97 clock is generated by Codec 0 and fed into the PXA255 processor and Codec 1. AC97 Audio Port bit clock. (output) AC97 clock is BITCLK/ ICOCZ generated by the PXA255 processor. Hi-Z - Note [1] Note [3] GPIO[28] I2S bit clock. (input) I2S clock is generated externally and fed into PXA255 processor. I2S bit clock. (output) I2S clock is generated by the PXA255 processor. SDATA_IN0/ AC97 Audio Port data in. (input) Input line for Codec 0. ICOCZ Hi-Z - Note [1] Note [3] GPIO[29] I2S data in. (input) Input line for the I2S Controller. AC97 Audio Port data in. (input) Input line for Codec 1. SDATA_IN1/ ICOCZ I2S system clock. (output) System clock from I2S Hi-Z - Note [1] Note [3] GPIO[32] Controller. AC97 Audio Port data out. (output) Output from the SDATA_OUT/ ICOCZ PXA255 processor to Codecs 0 and 1. Hi-Z - Note [1] Note [3] GPIO[30] I2S data out. (output) Output line for the I2S Controller. AC97 Audio Port sync signal. (output) Frame sync SYNC/ signal for the AC97 Controller. ICOCZ Hi-Z - Note [1] Note [3] GPIO[31] I2S sync. (output) Frame sync signal for the I2S Controller. nACRESET OC AC97 Audio Port reset signal. (output) Driven Low Driven Low I2C Controller Pins SCL ICOCZ I2C clock. (bidirectional) Hi-Z Hi-Z SDA ICOCZ I2C data. (bidirectional). Hi-Z Hi-Z PWM Pins PWM[1:0]/ ICOCZ Pulse Width Modulation channels 0 and 1. (outputs) Hi-Z - Note [1] Note [3] GPIO[17:16] DMA Pins
DREQ[1:0]/ DMA Request. (input) Notifies the DMA Controller that ICOCZ an external device requires a DMA transaction. DREQ[1] Hi-Z - Note [1] Note [3] GPIO[19:20] is GPIO[19]. DREQ[0] is GPIO[20]. GPIO Pins General Purpose I/O. Wakeup sources on both rising GPIO[1:0] ICOCZ Hi-Z - Note [1] Note [3] and falling edges on nRESET. General Purpose I/O. More wakeup sources for sleep GPIO[14:2] ICOCZ Hi-Z - Note [1] Note [3] mode.
Intel® PXA255 Processor Design Guide 1-9 Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
General Purpose I/O. Additional General Purpose I/O GPIO[22:21] ICOCZ Hi-Z - Note [1] Note [3] pins. Crystal and Clock Pins PXTAL IA 3.6864 Mhz crystal input. No external laps are required. Note [2] Note [2] 3.6864 Mhz crystal output. No external laps are PEXTAL OA Note [2] Note [2] required. TXTAL IA 32 Khz crystal input. No external laps are required. Note [2] Note [2] TEXTAL OA 32 Khz crystal output. No external laps are required. Note [2] Note [2] LCD display data. (output) Transfers pixel information L_DD[12]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[70] RTC clock. (output) Real time clock 1 Hz tick. LCD display data. (output) Transfers the pixel information from the LCD Controller to the external LCD L_DD[13]/ ICOCZ panel. Hi-Z - Note [1] Note [3] GPIO[71] 3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator. LCD display data. (output) Transfers pixel information L_DD[14]/ ICOCZ from the LCD Controller to the external LCD panel. Hi-Z - Note [1] Note [3] GPIO[72] 32 kHz clock. (output) Output from the 32 kHz oscillator. 48 MHz clock. (output) Peripheral clock output derived from the PLL. 48MHz/GP[7] ICOCZ Hi-Z - Note [1] Note [3] NOTE: This clock is only generated when the USB unit clock enable is set. RTCCLK/ Real time clock. (output) 1 Hz output derived from the ICOCZ Hi-Z - Note [1] Note [3] GP[10] 32kHz or 3.6864MHz output. 3.6864 MHz clock. (output) Output from 3.6864 MHz 3.6MHz/GP[11] ICOCZ Hi-Z - Note [1] Note [3] oscillator. 32kHz/GP[12] ICOCZ 32 kHz clock. (output) Output from the 32 kHz oscillator. Hi-Z - Note [1] Note [3] Miscellaneous Pins BOOT_SEL IC Boot select pins. (input) Indicates type of boot device. Input Input [2:0] Driven low while Power Enable for the power supply. (output) When entering sleep PWR_EN OC negated, it signals the power supply to remove power to Driven High mode. Driven high the core because the system is entering sleep mode. when sleep exit sequence begins. Main Battery Fault. (input) Signals that main battery is low or removed. Assertion causes PXA255 processor to enter sleep mode or force an Imprecise Data Exception, nBATT_FAULT IC Input Input which cannot be masked. PXA255 processor will not recognize a wakeup event while this signal is asserted. Minimum assertion time for nBATT_FAULT is 1 ms. VDD Fault. (input) Signals that the main power source is going out of regulation. nVDD_FAULT causes the PXA255 processor to enter sleep mode or force an nVDD_FAULT IC Imprecise Data Exception, which cannot be masked. Input Input nVDD_FAULT is ignored after a wakeup event until the power supply timer completes (approximately 10 ms). Minimum assertion time for nVDD_FAULT is 1 ms.
1-10 Intel® PXA255 Processor Design Guide Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
Hard reset. (input) Level sensitive input used to start the Input. Driving low processor from a known address. Assertion causes the during sleep will current instruction to terminate abnormally and causes a cause normal nRESET IC reset. When nRESET is driven high, the processor starts Input reset sequence execution from address 0. nRESET must remain low until and exit from sleep the power supply is stable and the internal 3.6864 MHz mode. oscillator has stabilized. Reset Out. (output) Asserted when nRESET is asserted Driven low during and deasserts after nRESET is deasserted but before the any reset sequence nRESET_OUT OC Driven Low first instruction fetch. nRESET_OUT is also asserted for - driven high prior to “soft” reset events: sleep, watchdog reset, or GPIO reset. first fetch. JTAG and Test Pins JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used, drive nTRST from low to nTRST IC high either before or at the same time as nRESET. If Input Input JTAG is not used, nTRST must be either tied to nRESET or tied low. JTAG test data input. (input) Data from the JTAG TDI IC controller is sent to the PXA255 processor using this pin. Input Input This pin has an internal pull-up resistor. JTAG test data output. (output) Data from the PXA255 TDO OCZ processor is returned to the JTAG controller using this Hi-Z Hi-Z pin. JTAG test mode select. (input) Selects the test mode TMS IC required from the JTAG controller. This pin has an Input Input internal pull-up resistor. JTAG test clock. (input) Clock for all transfers on the TCK IC Input Input JTAG test interface. TEST IC Test Mode. (input) Reserved. Must be grounded. Input Input TESTCLK IC Test Clock. (input) Reserved. Must be grounded. Input Input Power and Ground Pins Positive supply for internal logic. Must be connected VCC SUP Powered Note [6] to the low voltage supply on the PCB. Ground supply for internal logic. Must be connected to VSS SUP Grounded Grounded the common ground plane on the PCB. Positive supply for PLLs and oscillators. Must be PLL_VCC SUP Powered Note [6] connected to the common low voltage supply. Ground supply for the PLL. Must be connected to PLL_VSS SUP Grounded Grounded common ground plane on the PCB. Positive supply for all CMOS I/O except memory bus VCCQ SUP and PCMCIA pins. Must be connected to the common Powered Note [7] 3.3v supply on the PCB.
Intel® PXA255 Processor Design Guide 1-11 Introduction
Table 1-2. Pin & Signal Descriptions for the PXA255 Processor (Sheet 10 of 10)
Pin Name Type Signal Descriptions Reset State Sleep State
Ground supply for all CMOS I/O except memory bus VSSQ SUP and PCMCIA pins. Must be connected to the common Grounded Grounded ground plane on the PCB. Positive supply for memory bus and PCMCIA pins. VCCN SUP Must be connected to the common 3.3v or 2.5v supply on Powered Note [7] the PCB. Ground supply for memory bus and PCMCIA pins. VSSN SUP Must be connected to the common ground plane on the Grounded Grounded PCB.
Table 1-3. Pin Description Notes
Note Description
GPIO Reset Operation: Configured as GPIO inputs by default after any reset. The input buffers for these pins are disabled to prevent current drain and the pins are pulled high with 10K to 60K internal resistors. The input paths must be enabled and the pull-ups turned off by clearing the Read Disable Hold (RDH) bit described in [1] Section 3.5.7, “Power Manager Sleep Status Register (PSSR)” on page 3-27 of the Intel® PXA255 Processor Developer’s Manual. Even though sleep mode sets the RDH bit, the pull-up resistors are not re-enabled by sleep mode. Crystal oscillator pins: These pins are used to connect the external crystals to the on-chip oscillators. Refer to [2] Section 3.3.1, “32.768 kHz Oscillator” on page 3-4 and Section 3.3.2, “3.6864 MHz Oscillator” on page 3-4 in the Intel® PXA255 Processor Developer’s Manual for details on sleep mode operation. GPIO Sleep operation: During the transition into sleep mode, the state of these pins is determined by the corresponding PGSRn. See Section 3.5.10, “Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)” and Section 4.1.3.2, “GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)” on page 4-8 in the [3] Intel® PXA255 Processor Developer’s Manual. If selected as an input, this pin does not drive during sleep. If selected as an output, the value contained in the Sleep State Register is driven out onto the pin and held there while the PXA255 processor is in sleep mode. GPIOs configured as inputs after exiting sleep mode cannot be used until PSSR[RDH] is cleared. Static Memory Control Pins: During sleep mode, these pins can be programmed to either drive the value in the Sleep State Register or to be placed in Hi-Z. To select the Hi-Z state, software must set the FS bit in the Power [4] Manager General Configuration Register. If PCFR[FS] is not set, then during the transition to sleep these pins function as described in [3], above. For nWE, nOE, and nCS[0], if PCFR[FS] is not set, they are driven high by the Memory Controller before entering sleep. If PCFR[FS] is set, these pins are placed in Hi-Z. PCMCIA Control Pins: During sleep mode: Can be programmed either to drive the value in the Sleep State [5] Register or to be placed in Hi-Z. To select the Hi-Z state, software must set PCFR[FP]. If it is not set, then during the transition to sleep these pins function as described in [3], above.
[6] During sleep, this supply may be driven low. This supply must never be high impedance.
[7] Remains powered in sleep mode.
1-12 Intel® PXA255 Processor Design Guide Introduction
Figure 1-2. PXA255 Processor
Intel® PXA255 Processor Design Guide 1-13 Introduction
Table 1-4. PXA255 Processor Pinout — Ballpad Number Order (Sheet 1 of 3)
Ball # Signal Ball # Signal Ball # Signal
A1 VCCN F7 GPIO[10] L13 GPIO[2] A2 L_DD[13]/GPIO[71] F8 FFRTS/GPIO[41] L14 VSSQ A3 L_DD[12]/GPIO[70] F9 SSPSCLK/GPIO[23] L15 TEXTAL A4 L_DD[11]/GPIO[69] F10 FFDTR/GPIO[40] L16 TXTAL A5 L_DD[9]/GPIO[67] F11 VCC M1 MA[14] A6 L_DD[7]/GPIO[65] F12 GPIO[9] M2 MD[21] A7 GPIO[11] F13 BOOT_SEL[2] M3 MA[15] A8 L_BIAS/GPIO[77] F14 GPIO[8] M4 VCCN A9 SSPRXD/GPIO[26] F15 VSSQ M5 MD[1] A10 SDATA_OUT/GPIO[30] F16 NSSP_CLK/GPIO[81] M6 MD[6] A11 SDA G1 MA[0] M7 MD[7] A12 FFDCD/GPIO[36] G2 VSSN M8 DQM[0] A13 FFRXD/GPIO[34] G3 nSDCS[2] M9 MD[8] A14 FFCTS/GPIO[35] G4 nWE M10 MD[15] A15 BTCTS/GPIO[44] G5 nOE M11 VCCQ A16 SDATA_IN1/GPIO[32] G6 nSDCS[1] M12 GPIO[22] B1 DQM[1] G7 VCC M13 nPREG/GPIO[55] B2 DQM[2] G8 VSSQ M14 VCCN B3 L_DD[15]/GPIO[73] G9 VCC M15 VSSN B4 GPIO[14] G10 VSSQ M16 nIOIS16/GPIO[57] B5 GPIO[13] G11 TESTCLK N1 MD[22] B6 GPIO[12] G12 TEST N2 VSSN B7 L_DD[3]/GPIO[61] G13 BOOT_SEL[1] N3 MA[16] B8 L_PCLK/GPIO[76] G14 VCCQ N4 MD[0] B9 SSPEXTCLK/GPIO[27] G15 GPIO[7] N5 VCCN B10 FFRI/GPIO[38] G16 BOOT_SEL[0] N6 MD[4] B11 FFDSR/GPIO[37] H1 MA[2] N7 VCCN B12 USB_N H2 MA[1] N8 nCS[0] B13 BTRXD/GPIO[42] H3 MD[16] N9 VCCN B14 BTRTS/GPIO[45] H4 VCCN N10 MD[13] B15 IRRXD/GPIO[46] H5 MD[17] N11 VCCN B16 MMDAT H6 MA[3] N12 DREQ[0]/GPIO[20] C1 RDY/GPIO[18] H7 VSSQ N13 VCCN C2 VSSN H8 VSS N14 DREQ[1]/GPIO[19] C3 L_DD[14]/GPIO[72] H9 VSS N15 GPIO[21] C4 VSSQ H10 VCC N16 nPWAIT/GPIO[56] C5 L_DD[8]/GPIO[66] H11 nTRST P1 MA[17]
1-14 Intel® PXA255 Processor Design Guide Introduction
Table 1-4. PXA255 Processor Pinout — Ballpad Number Order (Sheet 2 of 3)
Ball # Signal Ball # Signal Ball # Signal
C6 VCCQ H12 TCK P2 MA[19] C7 L_DD[2]/GPIO[60] H13 TMS P3 VCCN C8 VSSQ H14 GPIO[6] P4 MA[25] C9 BITCLK/GPIO[28] H15 TDI P5 MA[23] C10 VCCQ H16 TDO P6 MD[24] C11 VSSQ J1 MA[7] P7 MD[26] C12 USB_P J2 VSSN P8 MD[27] C13 VCCQ J3 MA[6] P9 nCS[2]/GPIO[78] C14 VSSQ J4 MD[18] P10 MD[29] C15 IRTXD/GPIO[47] J5 MA[5] P11 MD[12] C16 VSS J6 MA[4] P12 MD[31] D1 SDCLK[2] J7 VCC P13 nPOE/GPIO[48] D2 SDCLK[0] J8 VSS P14 nPCE[1]/GPIO[52] D3 RDnWR J9 VSS P15 VSSN D4 VCCN J10 VSSQ P16 nPSKTSEL/GPIO[54] D5 L_DD[10]/GPIO[68] J11 GPIO[5] R1 MA[18] D6 L_DD[5]/GPIO[63] J12 GPIO[4] R2 VSSN D7 L_DD[1]/GPIO[59] J13 nRESET R3 MA[20] D8 L_LCLK/GPIO[75] J14 VSSQ R4 VSSN D9 SSPTXD/GPIO[25] J15 PLL_VCC R5 MA[22] D10 nACRESET J16 PLL_VSS R6 VSSN D11 SCL K1 MA[8] R7 MD[25] D12 PWM[1]/GPIO[17] K2 MA[9] R8 VSSN D13 BTTXD/GPIO[43] K3 MD[19] R9 MD[10] D14 MMCMD K4 VCCN R10 VSSN D15 VCCQ K5 MA[10] R11 MD[30] NSSP_TXD_RXD/ D16 K6 MA[11] R12 VSSN GPIO[84] E1 nSDRAS K7 VSSQ R13 nCS[4]/GPIO[80] E2 VSSN K8 VCC R14 VSSN E3 SDCKE[1] K9 VSSQ R15 nPIOW/GPIO[51] E4 SDCKE[0] K10 VCC R16 nPCE[2]/GPIO[53] E5 L_DD[6]/GPIO[64] K11 nRESET_OUT T1 VSS E6 L_DD[4]/GPIO[62] K12 nBATT_FAULT T2 VCCN E7 L_DD[0]/GPIO[58] K13 nVDD_FAULT T3 MD[23] E8 L_FCLK/GPIO[74] K14 GPIO[3] T4 MA[21] E9 SSPSFRM/GPIO[24] K15 PXTAL T5 MA[24] E10 SDATA_IN0/GPIO[29] K16 PEXTAL T6 MD[3]
Intel® PXA255 Processor Design Guide 1-15 Introduction
Table 1-4. PXA255 Processor Pinout — Ballpad Number Order (Sheet 3 of 3)
Ball # Signal Ball # Signal Ball # Signal
E11 SYNC/GPIO[31] L1 MA[12] T7 MD[5] E12 PWM[0]/GPIO[16] L2 VSSN T8 nCS[1]/GPIO[15] E13 FFTXD/GPIO[39] L3 MA[13] T9 nCS[3]/GPIO[79] E14 VCCQ L4 MD[20] T10 MD[9] NSSP_TXD_RXD/ E15 L5 MD[2] T11 MD[11] GPIO[83] E16 NSSP_FRAME/GPIO[82] L6 VCC T12 MD[14] F1 nSDCS[0] L7 DQM[3] T13 nCS[5]/GPIO[33] F2 nSDCS[3] L8 MD[28] T14 nPWE/GPIO[49] F3 nSDCAS L9 VCC T15 nPIOR/GPIO[50] F4 VCCN L10 GPIO[0] T16 VCCN F5 SDCLK[1] L11 PWR_EN F6 VSSQ L12 GPIO[1]
1-16 Intel® PXA255 Processor Design Guide System Memory Interface 2
This section describes the design guidelines for the system memory interface.
2.1 Overview
The external memory bus interface for the processor supports: • 100 MHz SDRAM at 3.3 V • 100 MHz SDRAM at 2.5 V • Synchronous and asynchronous Burst mode and Page mode Flash • Synchronous Mask ROM (SMROM) • Page Mode ROM • SRAM • SRAM-like Variable Latency I/O (VLIO) • PCMCIA expansion memory • Compact Flash
Use the memory interface configuration registers to program the memory types. Refer to Figure 1-1, “Processor Block Diagram” on page 1-2 for the block diagram of the Memory Controller configuration. Refer to Figure 2-1, “Memory Address Map” on page 2-3 for the processor memory map. Refer to Table 2-3, “Normal Mode Memory Address Mapping” on page 2- 6 for alternate mode address mapping.
Intel® PXA255 Processor Design Guide 2-1 System Memory Interface
Figure 2-1. General Memory Interface Configuration
nSDCS<0> SDRAM Partition 0
nSDCS<1> SDCLK<1>, SDCKE<1> SDRAM Partition 1 SDRAM Memory Interface nSDCS<2> Up to 4 partitions of SDRAM memory (16- or 32-bit wide) SDRAM Partition 2
nSDCS<3> SDCLK<2>, SDCKE<1> SDRAM Partition 3
DQM<3:0>
nSDRAS, nSDCAS
MD<31:0> Buffers and Card Memory Interface Transceivers Up to 2-socket support. PXA255 MA<25:0> Requires some Memory external buffering. Controller Interface Card Control
nCS<0> Static Memory or Static Bank 0 Variable Latency I/O Interface Up to 6 banks of ROM, Flash, nCS<1> SRAM, Variable Latency I/O, Static Bank 1 (16- or 32-bit wide) NOTE: nCS<2> Static Bank 0 must be populated by SDCLK<0>,SDCKE<0> Static Bank 2 “bootable” memory
nCS<3> Static Bank 3
Synchronous Static Memory Interface Up to 4 banks of synchronous nCS<4> static memory (nCS<3:0>). Static Bank 4 (16- or 32-bit wide) NOTE: nCS<5> Static Bank 0 must be populated by RDY Static Bank 5 “bootable” memory
2-2 Intel® PXA255 Processor Design Guide System Memory Interface
Table 2-1. Memory Address Map
Memory Description Address
0x6000 0000 Reserved Address Space 0x5C00 0000 Reserved Address Space 0x5800 0000 Reserved Address Space 0x5400 0000 Reserved Address Space 0x5000 0000 Reserved Address Space 0x4C00 0000 Reserved Address Space 0x4800 0000 Memory Mapped Registers (Memory Ctl) 0x4400 0000 Memory Mapped Registers (LCD) 0x4000 0000 Memory Mapped Registers (Peripherals) 0x3000 0000 PCMCIA/CF – Slot 1 0x2000 0000 PCMCIA/CF – Slot 0 0x1C00 0000 Reserved Address Space 0x1800 0000 Reserved Address Space 0x1400 0000 Static Chip Select 5 0x1000 0000 Static Chip Select 4 0x0C00 0000 Static Chip Select 3 0x0800 0000 Static Chip Select 2 0x0400 0000 Static Chip Select 1 0x0000 0000 Static Chip Select 0
2.2 SDRAM Interface
The processor supports an SDRAM interface at a maximum frequency of 100 MHz. The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is allocated 64 MBytes of the internal memory map. However, the actual size of each partition is dependent on the particular SDRAM configuration used. The four partitions are divided into two partition pairs: the 0/1 pair and the 2/3 pair. Both partitions within a pair (for example, partition 0 and partition 1) must be identical in size and configuration; however, the two pairs can be different. For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be 50 MHz SDRAM on a 16-bit data bus.
Note: For proper SDRAM operation above 50 MHz, 22 ohm series resistors should be placed on the memory address lines. System designers must run the appropriate high speed design simulations to determine if a different value resistor is needed.
Intel® PXA255 Processor Design Guide 2-3 System Memory Interface
2.3 SDRAM memory wiring diagram
Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer to Section 2.5, “SDRAM Address Mapping” on page 2-6 to determine the individual SDRAM component address. Figure 2-2. SDRAM Memory System Example
nSDCS(3:0) nSDRAS, nSDCAS, nWE, CKE(1) SDCLK(2:1) MA(23:10)
4Mx16 4Mx16 4Mx16 SDRAM SDRAM SDRAM
0 nCS 1 nCS 2 nCS nRAS nRAS nRAS nCAS nCAS nCAS nWE nWE nWE CKE CKE CKE 1 CLK 1 CLK 2 CLK addr(11:0) addr(11:0) addr(11:0) BA(1:0) BA(1:0) BA(1:0) 0 DQML DQML DQML 1 DQMH DQMH DQMH 15:0 DQ(15:0) DQ(15:0) DQ(15:0)
MD(31:0) DQM(3:0)
4Mx16 4Mx16 4Mx16 SDRAM SDRAM SDRAM
0 nCS 1 nCS 2 nCS nRAS nRAS nRAS nCAS nCAS nCAS nWE nWE nWE CKE CKE CKE 1 CLK 1 CLK 2 CLK addr(11:0) addr(11:0) 21:10 addr(11:0) BA(1:0) BA(1:0) 23:22 BA(1:0) 2 DQML DQML DQML 3 DQMH DQMH DQMH 31:16 DQ(15:0) DQ(15:0) DQ(15:0)
2-4 Intel® PXA255 Processor Design Guide System Memory Interface
2.4 SDRAM Support
Table 2-2 shows the SDRAM memory types and densities that are supported by the processor.
Table 2-2. SDRAM Memory Types Supported by the Processor
Maximum Partition Size SDRAM Number Chips/ Total Number Bank Bits x Memory (Mbyte/Partition) Configu- Partition of Chips Chip Row bits x (4 Partitions) ration Size Column (Words x Bits 16-bit 32-bit Bits) 16-bit 32-bit 16-bit 32-bit 16-bit 32-bit Bus Bus Bus bus Bus Bus Bus Bus
2 Mbyte 4 Mbyte 1M x 16 16 Mbit 1 2 1 x 11 x 8 8 Mbyte 16 Mbyte 4 8 4 Mbyte 8 Mbyte 2 M x 8 16 Mbit 2 4 1 x 11 x 9 16 Mbyte 32 Mbyte 8 16 8 Mbyte 16 Mbyte 4 M x 4 16 Mbit 4 8 1 x 11 x 10 32 Mbyte 64 Mbyte 16 32 N/A 8 Mbyte 2 M x 32 64 Mbit N/A 1 2 x 11 x 8 N/A 32 Mbyte N/A 4 1 x 13 x 8 8 Mbyte 16 Mbyte 4 M x 16 64 Mbit 1 2 32 Mbyte 64 Mbyte 4 8 2 x 12 x 8
1 x 13 x 9 128 16 Mbyte 32 Mbyte 8 M x 8 64 Mbit 2 4 64 Mbyte 816 2 x 12 x 9 Mbyte
1 x 13 x 10 128 256 32 Mbyte 64 Mbyte 16 M x 4 64 Mbit 4 8 16 32 2 x 12 x 10 Mbyte Mbyte 128 16 Mbyte 32 Mbyte 8 M x 16 128 Mbit 1 2 2 x 12 x 9 64 Mbyte 48 Mbyte 128 256 32 Mbyte 64 Mbyte 16 M x 8 128 Mbit 2 4 2 x 12 x 10 816 Mbyte Mbyte 256 64 Mbyte N/A 32 M x 4 128 Mbit 4 8 2 x 12 x 11 N/A 16 32 Mbyte 128 256 32 Mbyte 64 Mbyte 16 M x 16 256 Mbit 1 2 2 x 13 x 9 48 Mbyte Mbyte 256 64 Mbyte N/A 32 M x 8 256 Mbit 2 4 2 x 13 x 10 N/A 8 16 Mbyte
Intel® PXA255 Processor Design Guide 2-5 System Memory Interface
2.5 SDRAM Address Mapping
SDRAM Address Mapping is shown in Table 2-3 and Table 2-4.
Table 2-3. Normal Mode Memory Address Mapping
The processor pin mapping to SDRAM devices SDRAM # Bits Bank x (The address lines at the top of the columns are the processor address lines) Row x Device Technology Col A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1Mx16 16Mbit 1x11x8 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2Mx8 16Mbit 1x11x9 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
4Mx4 16Mbit 1x11x10 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x12x8 BS0A11A10A9A8A7A6A5A4A3A2A1A0
1x12x9 BS0A11A10A9A8A7A6A5A4A3A2A1A0
1x12x10 BS0A11A10A9A8A7A6A5A4A3A2A1A0
1x12x11 BS0A11A10A9A8A7A6A5A4A3A2A1A0
1x13x8 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x9 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x10 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x11 BS0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2Mx32 64Mbit 2x11x8 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
2x11x9 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
2x11x10 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
4Mx16/4Mx32 64Mbit/128Mbit 2x12x8 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8Mx8/8Mx16 64Mbit/128Mbit 2x12x9 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
16Mx4/16Mx8 64Mbit/128Mbit 2x12x10 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8Mx32 256Mbit 2x13x8 BS1BS0A12A11A10A9A8A7A6A5A4A3A2A1A0
16MX16 256Mbit 2x13x9 BS1BS0A12A11A10A9A8A7A6A5A4A3A2A1A0
2-6 Intel® PXA255 Processor Design Guide System Memory Interface
Table 2-4. Processor Compatibility Mode Address Line Mapping
The processor pin mapping to SDRAM devices SDRAM # Bits Bank x (The address lines at the top of the columns are the processor address lines) Row x Device Technology Col A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1Mx16 16Mbit 1x11x8 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2Mx8 16Mbit 1x11x9 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
4Mx4 16Mbit 1x11x10 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x12x8 A11BS0A10A9A8A7A6A5A4A3A2A1A0
1x12x9 A11BS0A10A9A8A7A6A5A4A3A2A1A0
1x12x10 A11BS0A10A9A8A7A6A5A4A3A2A1A0
1x12x11 A11BS0A10A9A8A7A6A5A4A3A2A1A0
1x13x8 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x9 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x10 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1x13x11 A12 A11 BS0 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
2Mx32 64Mbit 2x11x8 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
2x11x9 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
2x11x10 BS1BS0A10A9A8A7A6A5A4A3A2A1A0
4Mx16/4Mx32 64Mbit/128Mbit 2x12x8 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8Mx8/8Mx16 64Mbit/128Mbit 2x12x9 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
16Mx4/16Mx8 64Mbit/128Mbit 2x12x10 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
32Mx4 128Mbit 2x12x11 BS1 BS0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
8Mx32 256Mbit 2x13x8 A12BS1BS0A11A10A9A8A7A6A5A4A3A2A1A0
16Mx16 256Mbit 2x13x9 A12BS1BS0A11A10A9A8A7A6A5A4A3A2A1A0
2.6 Static Memory
2.6.1 Overview
The processor external memory bus interface supports the following static memory types: • Synchronous and asynchronous Burst mode and Page mode Flash • Synchronous Mask ROM (SMROM) • Page Mode ROM • SRAM • SRAM-like Variable Latency I/O (VLIO) • PCMCIA expansion memory • Compact Flash
Memory types are programmable through the memory interface configuration registers.
Intel® PXA255 Processor Design Guide 2-7 System Memory Interface
Six chip selects control the static memory interface, nCS<5:0>. All are configurable for nonburst ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices. The variable latency I/O interface differs from SRAM in that it allows the data ready input signal (RDY) to insert a variable number of memory-cycle wait states. The data bus width for each chip select region may be programmed to be 16-bit or 32-bit. nCS<3:0> are also configurable for Synchronous Static Memory.
Note: Chip selects CS[5:1] should have external 10K pull up resistors.
For SRAM and variable latency I/O implementations, DQM<3:0> signals are used for the write byte enables, where DQM<3> corresponds to the MSB. The processor supplies 26-bits of byte address for access of up to 64 Mbytes per chip select. However, when the address is sent out on the MA pins, MA reflects the actual address, not the byte address. The lower one or two internal address bits are truncated appropriately.
2.6.2 Boot Time Defaults
Table 2-5 shows valid booting configurations for the PXA255 processor, while Table 2-6 shows boot selection definitions. See Section 6.10.2 “Boot Time Defaults” in the Intel® PXA255 Processor Developer’s Manual for more detailed descriptions of these Boot Time Configurations.
Table 2-5. Valid Booting Configurations Based for the PXA255 processor
Valid Booting Configurations
000 001 100 101 110 111
Table 2-6. BOOT_SEL Definitions
BOOT_SEL Boot From . . . 210
0 0 0 Asynchronous 32-bit ROM 0 0 1 Asynchronous 16-bit ROM 1 32-bit Synchronous Mask ROM (64 Mbits) 100 2 16-bit Synchronous Mask ROMs = 32-bits (32 Mbits each) 1 0 1 1 16-bit Synchronous Mask ROM (64 Mbits) 1 1 0 2 16-bit Synchronous Mask ROMs = 32-bits (64 Mbits each) 1 1 1 1 16-bit Synchronous Mask ROM (32 Mbits)
2-8 Intel® PXA255 Processor Design Guide System Memory Interface
2.6.3 Flash Memory
The PXA255 processor supports Flash memory on all six static chip selects and synchronous operation on nCS[3:0]. If synchronous Flash memory is used in the system, the traces for SDCLK0, address, data and control should be limited to 3 inches. If the traces must exceed 3 inches, 47 ohm series termination resistors must be included.
2.6.3.1 Synchronous Intel® StrataFlash® Memory Reset
The PXA250 nRESET_OUT pin must be connected to the K3 #RST pin for Hardware reset, Watchdog reset and sleep mode to work properly. GPIO reset however does not reset the contents of the memory controller configuration register. If GPIO reset operation is required, a state machine is necessary between nRESET, nRESET_OUT, GPIO[1], and #RST to ensure that #RST is asserted during Hardware reset, Watchdog reset, and sleep mode, and not asserted during GPIO reset. Figure 2-3, “Flash Memory Reset Using State Machine” on page 2-9 shows the required logic. GPIO_a is an unused GPIO that is driven low by software during the initialization sequence and left high during normal operation. After this is completed, then enable GPIO Reset. Figure 2-3. Flash Memory Reset Using State Machine
K3 Flash GPIO[1] nS Q
#RST nRESET_OUT nRESET GPIO_a nR
If Watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using the equation #RST = nRESET & (nRESET_OUT | GPIO_a). This allows sleep mode entry to reset the flash memory while keeping it in synchronous mode during a GPIO reset. Figure 2-4, “Flash Memory Reset Logic if Watchdog Reset is Not Necessary” on page 2-9 shows the required logic. GPIO_a is an unused GPIO that is kept high during normal operation and driven low before sleep mode entry. Figure 2-4. Flash Memory Reset Logic if Watchdog Reset is Not Necessary
K3 Flash GPIO_a
#RST nRESET_OUT nRESET
2.6.4 SRAM / ROM / Flash / Synchronous Fast Flash Memory Options
Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash.
Intel® PXA255 Processor Design Guide 2-9 System Memory Interface
Table 2-7. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
MEMCKLK Units Symbol Description Notes 99.5 118.0 132.7 147.5 165.9
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous) MA(25:0) setup to nOE, nSDCAS (as tromAS 10 8.5 7.5 6.8 6 ns, 1 nADV) asserted MA(25:0) hold after nCS, nOE, tromAH 10 8.5 7.5 6.8 6 ns, 1 nSDCAS (as nADV) de-asserted tromASW MA(25:0) setup to nWE asserted 30 25.5 22.5 20.4 18 ns, 3 tromAHW MA(25:0) hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1 tromCES nCS setup to nWE asserted 20 17 15 13.6 12 ns, 2 tromCEH nCS hold after nWE de-asserted 10 8.5 7.5 6.8 6 ns, 1 MD(31:0), DQM(3:0) write data setup to tromDS 10 8.5 7.5 6.8 6 ns, 1 nWE asserted MD(31:0), DQM(3:0) write data setup to tromDSWH 20 17 15 13.6 12 ns, 2 nWE de-asserted MD(31:0), DQM(3:0) write data hold tromDH 10 8.5 7.5 6.8 6 ns, 1 after nWE de-asserted nWE high time between beats of write tromNWE 20 17 15 13.6 12 ns, 2 data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods
2.6.5 Variable Latency I/O Interface Overview
Both reads and writes for VLIO differ from SRAM in that the PXA255 processor samples the data- ready input, RDY. The RDY signal is level sensitive and goes through a two-stage synchronizer on input. When the internal RDY signal is high, the I/O device is ready for data transfer. This means that for a transaction to complete at the minimum assertion time for either nOE or nPWE (RDF+1), the RDY signal must be high two clocks prior to the minimum assertion time for either nOE or nPWE (RDF-1). Data will be latched on the rising edge of MEMCLK once the internal RDY signal is high and the minimum assertion time of RDF+1 has been reached. Once the data has been latched, the address may change on the next rising edge of MEMCLK or any cycles thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final nOE or nPWE deassertion. Refer to Figure 2-5 for 32-Bit Variable Latency I/O read timing and Figure 2-8 for Variable Latency I/O Interface AC Specifications
2-10 Intel® PXA255 Processor Design Guide System Memory Interface
Figure 2-5. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)
0ns 100ns 200ns 300ns
memlk nCS[0]
tAS MA[25:2] 0123
MA[1:0] "00"
tASRW0 tASWN tAH tCEH tCES RDN+1 RDF+1+Waits RRR+1 nOE
nPWE
RDnWR RDY
MD[31:0]
DQM[3:0] "0000"
nCS[1]
A8867-01
Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2)
MEMCKLK Units Symbol Description Notes 99.5 118.0 132.7 147.5 165.9
Variable Latency IO Interface (VLIO) (Asynchronous) tvlioAS MA(25:0) setup to nCS asserted 10 8.5 7.5 6.8 6 ns, 1 MA(25:0) setup to nOE or nPWE tvlioASRW 10 8.5 7.5 6.8 6 ns, 1 asserted MA(25:0) hold after nOE or nPWE de- tvlioAH 10 8.5 7.5 6.8 6 ns, 1 asserted tvlioCES nCS setup to nOE or nPWE asserted 20 17 15 13.6 12 ns, 2 nCS hold after nOE or nPWE de- tvlioCEH 10 8.5 7.5 6.8 6 ns, 1 asserted MD(31:0), DQM(3:0) write data setup to tvlioDSW 10 8.5 7.5 6.8 6 ns, 1 nPWE asserted MD(31:0), DQM(3:0) write data setup to tvlioDSWH 20 17 15 13.6 12 ns, 2 nPWE de-asserted MD(31:0), DQM(3:0) hold after nPWE tvlioDHW 10 8.5 7.5 6.8 6 ns, 1 de-asserted
Intel® PXA255 Processor Design Guide 2-11 System Memory Interface
Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2)
MEMCKLK Units Symbol Description Notes 99.5 118.0 132.7 147.5 165.9
MD(31:0) read data hold after nOE de- tvlioDHR 00000ns asserted RDY hold after nOE, nPWE de- tvlioRDYH 00000ns asserted nPWE, nOE high time between beats of tvlioNPWE 20 17 15 13.6 12 ns, 2 write or read data NOTES: 1. This number represents 1 MEMCLK period 2. This number represents 2 MEMCLK periods
2.6.6 External Logic for PCMCIA Implementation
The PXA255 processor requires external glue logic to complete the PCMCIA socket interface. Figure 2-6, “Expansion Card External Logic for a Two-Socket Configuration” on page 2-13 and Figure 2-7, “Expansion Card External Logic for a One-Socket Configuration” on page 2-14 show general solutions for one and two socket configurations. Use GPIO or memory-mapped external registers to control the PCMCIA interface’s reset, power selection (VCC and VPP), and drive enables. These diagrams show the logical connections necessary to support hot insertion capability. For dual-voltage support, level shifting buffers are required for all the processor input signals. Hot insertion capability requires each socket be electrically isolated from the other and from the remainder of the memory system. If one or both of these features are not required, you may eliminate some of the logic shown in these diagrams. The processor allows either 1-socket or 2- socket solutions. In the 1-socket solution, only minimal glue logic is required (typically for the data transceivers, address buffers, and level shifting buffers.) To achieve this some of the signals are routed through dual-duty GPIO pins. The nOE of the transceivers is driven through the PSKTSEL pin, which is not needed in the one-socket solution. The DIR pin of the transceiver is driven through the RDnWR pin. A GPIO is used for the three-state signal of the address and nPWE lines. These signals are used for memories other than the card interface and must be three-stated.
Note: For 2.5 V VCCN, 5 V to 2.5 V level shifters are required.
In the 2-socket solution, all pins assume their normal duties and glue logic is necessary for proper operation of the system. The pull-ups shown are included for compliance with PC Card Standard - Volume 2 - Electrical Specification. Remove power from these pull-ups during sleep to avoid unnecessary power consumption. Refer to Table 2-9 for the PCMCIA or compact Flash card interface AC specifications.
2-12 Intel® PXA255 Processor Design Guide System Memory Interface
Figure 2-6. Expansion Card External Logic for a Two-Socket Configuration
PXA255 Processor Socket 0
D(15:0) D(15:0)
DIR OE# nPCEx Socket 1
D(15:0)
DIR OE# nPOE nPIOR nPCEx
CD1# GPIO(w) CD2#
CD1# GPIO(x) CD2#
GPIO(y) RDY/BSY#
GPIO(z) RDY/BSY# PSKTSEL
MA(25:0) A(25:0) nPREG REG# A(25:0) nPCE(1:2) CE(1:2)# REG# nPOE, OE# 6 6 nPWE WE# nPIOW, IOR# CE(1:2)# IOW# nPIOR 6 OE# WE# IOR# IOW# WAIT# nPWAIT WAIT#
IOIS1616#
nPIOIS16 IOIS1616#
Intel® PXA255 Processor Design Guide 2-13 System Memory Interface
Figure 2-7. Expansion Card External Logic for a One-Socket Configuration
PXA255 Processor Socket 0 MD<15:0> D<15:0>
DIR nOE
RD/nWR
GPIO
GPIO
nPWE nWE
nPREG nREG nPCE<2:1> nCE<2:1> nPOE nOE nPIOR nIOR nPIOW nIOW 5V to 3.3V nPWAIT nWAIT
5V to 3.3V nIOIS16 nIOIS16
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 1 of 2)
MEMCKLK Units Symbol Description Notes 99.5 118.0 132.7 147.5 165.9
Card Interface (PCMCIA or Compact Flash) (Asynchronous) MA(25:0), nPREG, PSKTSEL, nPCE tcardAS setup to nPWE, nPOE, nPIOW, or 20 17 15 13.6 12 ns, 1 nPIOR asserted MA(25:0), nPREG, PSKTSEL, nPCE tcardAH hold after nPWE, nPOE, nPIOW, or 10 8.5 7.5 6.8 6 ns, 1 nPIOR de-asserted MD(31:0) setup to nPWE, nPOE, tcardDS 10 8.5 7.5 6.8 6 ns, 1 nPIOW, or NPIOR asserted
2-14 Intel® PXA255 Processor Design Guide System Memory Interface
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 2 of 2)
MEMCKLK Units Symbol Description Notes 99.5 118.0 132.7 147.5 165.9
MD(31:0) hold after nPWE, nPOE, tcardDH 10 8.5 7.5 6.8 6 ns, 1 nPIOW, or NPIOR de-asserted nPWE, nPOE, nPIOW, or nPIOR tcardCMD 30 25.5 22.5 20.4 18 ns, 1 command assertion NOTE: 1. These numbers are minmums. They can be much larger based on the programmable Card Interface timing registers.
2.6.7 DMA / Companion Chip Interface
Connect a companion chip to the processor via: • Alternate Bus Master Mode • Variable Latency I/O • Flow through DMA
These connections are illustrated in Figure 2-8 and Figure 2-9.
Intel® PXA255 Processor Design Guide 2-15 System Memory Interface
Figure 2-8. Alternate Bus Master Mode
EXTERNAL SYSTEM PXA255
SDCKE<1>
SDCLK<1> PXA255 nSDCS(0) External Memory nSDRAS SDRAM Controller nSDCAS Bank 0 nWE
MA<25:0>
DQM<3:0>
MD<31:0> MBREQ MBGNT
Companion PXA255 Chip GPIO Block GPIO<13> (MBGNT) GPIO<14> (MBREQ)
2-16 Intel® PXA255 Processor Design Guide System Memory Interface
Figure 2-9. Variable Latency I/O
EXTERNAL SYSTEM PXA255 nCS(0,1,2,3,4,5)
nOE
nPWE
PXA255 MA<25:0> Companion Memory Controller DQM<3:0> Chip
MD<31:0>
RDY
Intel® PXA255 Processor Design Guide 2-17 System Memory Interface
2.7 System Memory Layout Guidelines
2.7.1 System Memory Topologies (Min and Max Simulated Loading)
Figure 2-10, Figure 2-11, Figure 2-12, and Figure 2-13 are the topologies that where simulated to develop the trace length recommendations in Section 2.7.2. These topologies are for reference only. Figure 2-10. CS, CKE, DQM, CLK, MA minimum loading topology
CS, CKE, DQM, SDRAM CLK, MA
Figure 2-11. CS, CKE, DQM, CLK, MA Maximum Loading Topology
SDRAM
SDRAM CS, CKE, DQM, CLK, MA SDRAM
SDRAM
Figure 2-12. MD Minimum Loading Topology
MD SDRAM
2-18 Intel® PXA255 Processor Design Guide System Memory Interface
Figure 2-13. MD maximum loading topology
SDRAM SDRAM
MD
AUX AUX AUX AUX
2.7.2 System Memory Recommended Trace Lengths
Table 2-10 details the minimum and maximum trace lengths that were simulated for the processor. These trace lengths are not the absolute trace lengths that will work given the loading conditions. The trace lengths in Table 2-10 are measured from the processor to the individual component pins. The board impedance for the simulations was 60ohm +/- 10%.
Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
Min Max Signal Trace Length Trace Length
CS, CKE, DQM 0.75 in 4.5 in CLK 1.0 in 4.25 in MA 1.0 in 4.5 in MD 1.0 in 4.25 in
Intel® PXA255 Processor Design Guide 2-19 System Memory Interface
2-20 Intel® PXA255 Processor Design Guide LCD Display Controller 3
This chapter describes sample hardware connections from the PXA255 processor to various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed as well as single and dual panel displays. These should not be considered the only possible ways to connect an LCD panel to the PXA255 processor, but should serve as a reference to assist with hardware design considerations. Other panels, for example panels without L_FCLK or L_LCLK, have been successfully connected to the PXA255 processor.
3.1 LCD Display Overview
The PXA255 processor supports both active and passive LCD displays. Active displays generally produce better looking images, but at a higher cost. Passive displays are generally less expensive, but their displays are inferior to active displays. However, recent advances in dithering technology are closing the quality gap between passive and active displays.
Note: Names used for “LCD Panel Pin” are representative names and may not match those on all LCD panels. Refer to the LCD panel reference documentation for the actual name.
3.2 Passive (DSTN) Displays
Several different types of passive displays are available in both color and monochrome. These may be single or dual panel displays. Additionally, some monochrome displays use double-pixel data mode (twice the number of pixels as a normal monochrome display). With the exception of the number of data pins required, all of these choices affect the software configuration and support, not the system hardware design. In fact, most passive displays use a single interconnection scheme. For information on the software changes and performance considerations of the various display options, refer to the Intel® PXA255 Processor Developer’s Manual.
Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle a single data line drives an ON/OFF signal for one color of a single pixel.
Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as well as which LCD data pins are used for which panel (upper or lower).
Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2)
Color/ Single/ Double-Pixel Monochrome Screen Portion Pins Dual Panel Mode Panel
Monochrome Single No Whole L_DD<3:0> Monochrome Single Yes Whole L_DD<7:0>1 Top L_DD<3:0> Monochrome Dual No Bottom L_DD<7:4> Color Single N/A Whole L_DD<7:0>
Intel® PXA255 Processor Design Guide 3-1 LCD Display Controller
Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2)
Color/ Single/ Double-Pixel Monochrome Screen Portion Pins Dual Panel Mode Panel
Top L_DD<7:0> Color Dual N/A Bottom L_DD<15:8> NOTE: 1. Double pixel data mode (DPD) = 1.
For passive displays, the pins described in Table 3-2 are required connections between the PXA255 processor and your LCD panel.
Table 3-2. Passive Display Pins Required
PXA255 LCD Panel Pin PIn Type1 Definition processor Pin
Data lines used to transmit either four or eight data values at a time to the LCD display. For monochrome displays, each pin value represents a single pixel; for passive color, groupings of three pin values represent L_DD DU_x, DL_x Output one pixel (red, green, and blue data values). Either the bottom four pins (L_DD<3:0>), the bottom 8 pins (L_DD<7:0>) or all 16 pixel data pins (L_DD<15:0>)will be used as shown in Table 3-1 Pixel Clock - used by the LCD display to clock the pixel data into the L_PCLK Pixel_Clock Output line shift register. Line Clock - used by the LCD display to signal the end of a line of pixels L_LCLK Line_Clock Output that transfers the line data from the shift register to the screen and increment the line pointers. Frame Clock - used by the LCD displays to signal the start of a new L_FCLK Frame_Clock Output frame of pixels that resets the line pointers to the top of the screen. AC bias used to signal the LCD display to switch the polarity of the L_BIAS Bias Output power supplies to the row and column axis of the screen to counteract DC offset. Contrast Voltage - Adjustable voltage input to LCD panel - external N/A Vcon2 N/A voltage circuitry is required (no pin available on PXA255 processor). NOTES: 1. “Pin Type” is in reference to the PXA255 processor. Therefore, outputs are pins that drive a signal from the processor to another device. 2. Vcon is a signal external to the PXA255 processor. Please refer to “Contrast Voltage” on page 8
3.2.1 Typical Connections for Passive Panel Displays
The following diagrams are typical connections and serve as a guide for designing systems which contain passive LCD displays. Panels differ on which is the panel’s least significant bit (Refer to the LCD panel reference documentation for the least significant bit.) Each figure indicates the top- left pixel (1,1) bit. Dual panels indicate the top-left pixel (1,n/2) of the upper and lower panels and color passive panels show the top-left-pixel color bits.
3.2.1.1 Passive Monochrome Single Panel Displays
Figure 3-1 is a typical single-panel monochrome passive display connection.
3-2 Intel® PXA255 Processor Design Guide LCD Display Controller
Figure 3-1. Single Panel Monochrome Passive Display Typical Connection
L_DD0 - Top left D0 L_DD1 D1 L_DD2 D2 L_DD3 D3
PXA255 Processor LCD Display
L_PCLK Pixel_Clock L_LCLK Line_Clock L_FCLK Frame_Clock L_BIAS Bias
3.2.1.2 Passive Monochrome Single Panel Displays, Double-Pixel Data
Figure 3-2 shows typical connections for a single-panel monochrome passive display using double- pixel data mode. Figure 3-2. Passive Monochrome Single Panel Displays, Double-Pixel Data Typical Connection
L_DD0 - Top left D0 L_DD1 D1 L_DD2 D2 L_DD3 D3 L_DD4 D4 L_DD5 D5 PXA255 Processor L_DD6 D6 LCD Display L_DD7 D7
L_PCLK Pixel_Clock L_LCLK Line_Clock L_FCLK Frame_Clock L_BIAS Bias
3.2.1.3 Passive Monochrome Dual Panel Displays
Figure 3-3 is a typical dual-panel monochrome passive display connection.
Intel® PXA255 Processor Design Guide 3-3 LCD Display Controller
Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection
L_DD0 - Top left for upper panel DU_0 L_DD1 DU_1 L_DD2 DU_2 L_DD3 DU_3 Upper Panel
L_PCLK Pixel_Clock PXA255 Processor L_LCLK Line_Clock L_FCLK Frame_Clock LCD Display L_BIAS Bias
L_DD4 - Top left for lower panel DL_0 L_DD5 DL_1 Lower Panel L_DD6 DL_2 L_DD7 DL_3
3.2.1.4 Passive Color Single Panel Displays
Figure 3-4 is a typical single-panel color passive display connection. Figure 3-4. Passive Color Single Panel Displays Typical Connection
L_DD0 D0 L_DD1 D1 L_DD2 D2 L_DD3 D3 L_DD4 D4 D5 L_DD5 - Top left Blue LCD Display PXA255 Processor L_DD6 - Top left Green D6 L_DD7 - Top left Red D7
L_PCLK Pixel_Clock L_LCLK Line_Clock L_FCLK Frame_Clock L_BIAS Bias
3.2.1.5 Passive Color Dual Panel Displays
Figure 3-5 is a typical dual-panel color passive display connection.
3-4 Intel® PXA255 Processor Design Guide LCD Display Controller
Figure 3-5. Passive Color Dual Panel Displays Typical Connection
L_DD0 DU_0 L_DD1 DU_1 L_DD2 DU_2 L_DD3 DU_3 L_DD4 DU_4 Upper Panel L_DD5 - Top left Blue for upper panel DU_5 L_DD6 - Top left Green for upper panel DU_6 L_DD7 - Top left Red for upper panel DU_7 PXA255 Processor L_PCLK Pixel_Clock L_LCLK Line_Clock L_FCLK Frame_Clock LCD Display L_BIAS Bias
L_DD8 DL_0 L_DD9 DL_1 L_DD10 DL_2 L_DD11 DL_3 Lower Panel L_DD12 DL_4 L_DD13 - Top left Blue for lower panel DL_5 L_DD14 - Top left Green for lower panel DL_6 L_DD15 - Top left Red for lower panel DL_7
3.3 Active (TFT) Displays
Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in order to transfer the pixel data from the controller. All 16 data lines are also required to drive one pixel value. The 16 bits of data describe the intensity level of the red, green, and blue for each pixel. Typically, this is formatted as 5 bits for red, 6 bits for green, and 5 bits for blue, but this can vary by display and is controlled by the software writing to the frame buffer. Refer to the display datasheet to ensure that the correct the PXA255 processor LCD data lines are connected to the correct LCD panel data lines.
Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these panels it is recommended that the most significant lines of the panel lines are connected to the data lines from the PXA255 processor. This maintains the panel’s full range of colors but increases the granularity of the color spectrum with an insufficient number of data lines. All unused panel data lines can be tied either high or low. Other options include tying the LSB of red and blue to the next bit, R1 or B1.
For active displays, connect the pins described in Table 3-3 between the PXA255 processor and the LCD panel.
Intel® PXA255 Processor Design Guide 3-5 LCD Display Controller
Table 3-3. Active Display Pins Required
PXA255 LCD Panel Pin PIn Type1 Definition processor Pin
R<4:0>,G<5:0>, L_DD<15:0> Output Data lines used to transmit the 16 bit data values to the LCD display. B<4:0> Pixel Clock - used by the LCD display to clock the pixel data into the L_PCLK Clock Output line shift register. In active mode this clock transitions constantly. Line Clock - used by the LCD display to signal the end of a line of pixels L_LCLK Horizontal Sync Output that transfers the line data from the shift register to the screen and increment the line pointers. Also signals the panel to start a new line. Frame Clock - used by the LCD displays to signal the start of a new L_FCLK Vertical Sync Output frame of pixels that resets the line pointers to the top of the screen. DE (Data AC biases used in active mode as a data enable signal when data L_BIAS Output Enable) should be latched by the pixel clock from the data lines. Contrast Voltage - Adjustable voltage input to LCD panel - external N/A Vcon2 N/A voltage circuitry is required (no pin available on the PXA255 processor). NOTES: 1. In reference to the PXA255 processor. Therefore, outputs are pins that drive a signal from the PXA255 processor to another device. 2. Vcon is a signal external to the PXA255 processor. Please refer to Section 3.5.1, “Contrast Voltage” on page 8.
3.3.1 Typical connections for Active Panel Displays
Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for an active panel display and should serve as a guide for designing systems which contain active LCD displays. The MSB of each color is indicated. The panel is 18-bit, with the LSB of red and blue tied to ground.
3-6 Intel® PXA255 Processor Design Guide LCD Display Controller
Note: This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active display panels might have more or different data lines. Consult the LCD panel manufacturer’s datasheet for the actual data lines. Figure 3-6. Active Color Display Typical Connection
B0 L_DD0 B1 L_DD1 B2 L_DD2 B3 L_DD3 B4 L_DD4 - MSB of Blue B5 L_DD5 G0 L_DD6 G1 L_DD7 G2 L_DD8 G3 L_DD9 G4 L_DD10 - MSB of Green G5 PXA255 Processor R0 LCD Panel L_DD11 R1 L_DD12 R2 L_DD13 R3 L_DD14 R4 L_DD15 - MSB of Red R5
L_PCLK Clock L_LCLK Horizontal Sync L_FCLK Vertical Sync L_BIAS Data Enable
3.4 PXA255 processor Pinout
Table 3-4 describes the ball positions for the LCD controller on the PXA255 processor.
Table 3-4. PXA255 processor LCD Controller Ball Positions (Sheet 1 of 2)
Pin Name Ball Position
L_DD0 E7 L_DD1 D7 L_DD2 C7 L_DD3 B7 L_DD4 E6 L_DD5 D6 L_DD6 E5 L_DD7 A6 L_DD8 C5 L_DD9 A5 L_DD10 D5 L_DD11 A4 L_DD12 A3
Intel® PXA255 Processor Design Guide 3-7 LCD Display Controller
Table 3-4. PXA255 processor LCD Controller Ball Positions (Sheet 2 of 2)
Pin Name Ball Position
L_DD13 A2 L_DD14 C3 L_DD15 B3 L_FCLK E8 L_LCLK D8 L_PCLK B8 Bias A8
3.5 Additional Design Considerations
3.5.1 Contrast Voltage
Many displays, both active and passive, include a pin for adjusting the display contrast voltage. This is a variable analog voltage that is supplied to the panel via a voltage source on the system board. The contrast voltage is adjusted via a variable resistor on the circuit board.
The required voltage range and current capabilities vary between panel manufacturers. Consult the datasheet for your panel to determine the variable voltage circuit design. Ensure that the contrast voltage is stable, otherwise visual artifacts might result. Possible contrast voltage circuits are often suggested by the panel manufacturers.
3.5.2 Backlight Inverter
One potential source of noise for the LCD panel can be the backlight inverter. Since this is a high voltage device with frequent voltage inversions, it has the potential to inject spurious noise onto the LCD panel lines. To minimize noise: • Use a shielded backlight inverter • Physically locate the inverter as far away from the LCD data lines and system board as possible, usually located with the LCD panel
If power consumption is an issue, chose a backlight inverter that can be disabled through software. This lets you save power by automatically disabling the backlight if no activity occurs within a preset period of time
3.5.3 Signal Routing and Buffering
Signal transmission rates between the LCD controller and the LCD panel are moderate, which helps to simplify the design of the LCD system. The minimum Pixel Clock Divider (PCD) value results in a pixel clock rate of one half of the LCLK (this is not the L_LCLK of the LCD controller.) The maximum LCLK for the PXA255 processor is 166 MHz, resulting in a maximum pixel clock rate of 83 MHz. Thus, use of 100 MHz design considerations are sufficient to ensure LCD panel signal integrity.
3-8 Intel® PXA255 Processor Design Guide LCD Display Controller
However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined this, calculate the number of pixels (800 x 600 = 480,000) and multiply by the screen refresh rate (75 Hz). Since active panels replace 1 pixel of data with every clock cycle this determines the final transfer rate. Active displays normally do not require refresh rates as high as 75 Hz, so you may use a lower refresh rate to reduce transmission rates even more.
Passive displays often do require refresh rates greater than 75 Hz, which transfers more pixels each clock cycle. For instance, a color passive display with 8 data lines transfers 2 2/3 pixels’ worth of data each clock cycle. This divides the transmission rate by 2 2/3. Further reductions in the transfer rate come by using dual panel displays which use twice as many data lines to transfer data - halving the rate again.
Generally, this gives you lower transfer rates to even large displays and thus simpler design considerations and fewer layout constraints.
When laying out your design, minimize trace length of the LCD panel signals and allow sufficient spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the data line signals.
LCD system design is not considered to be critical as infrequent or single bit errors are, typically, not noticed by the user. Also, the errors are transitory, as the old data is constantly being replaced with new data. Slower panel refresh rates increase the likelihood that a single error is noticed by the user. However, there is a counteracting effect in that slower refresh rates relax LCD timing and therefore result in fewer screen transmission errors. There are other factors related to choosing a refresh rate for an LCD system, most significant is the impact on system bandwidth.
If you must use excessively long or poorly routed signals, one possible solution is to add buffers between the PXA255 processor and the LCD panel. This helps strengthen the LCD panel signal levels and synchronizes signal timing. However, this is usually not required as the LCD panel timings are fairly relaxed. Since the LCD display essentially operates asynchronously from the processor, the propagation delay of the buffers is not a major concern.
When mounting the LCD panel, it is critical to shield the touchscreen control lines, if present. Noise from the LCD panel and its control signals can become injected into the touchscreen control lines, causing spurious touch interrupts or loss of resolution.
3.5.4 Panel Connector
Most LCD panels are connected to the system board via a connector, instead of being directly mounted on the system board. This increases flexibility and ease of manufacture. Typically the manufacturer of the panel recommends a particular connector for the panel. Follow the panel manufacturer’s recommendation.
Intel® PXA255 Processor Design Guide 3-9 LCD Display Controller
3-10 Intel® PXA255 Processor Design Guide USB Interface 4
4.1 Self Powered Device
Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your board to compensate for minor differences between the USB cable and your board trace impedance.
The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This voltage divider can be implemented in a number of ways. The most robust and expensive solution is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V tolerant inputs. This solution does not reduce signal bounce, so software must compensate by reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.
Note: If GPIOn and GPIOx are the same pin, never put the device to sleep while the USB cable is connected to the device. During sleep, the USB controller is in reset and will not respond to the host; after sleep, the device will not respond to its host-assigned address. Figure 4-1. Self Powered Device
USB 5V 5V to 3.3V GPIOn 470K GPIOx 1.5K USB UDC+ UDC+ 0 ohm (optional) USB UDC- UDC- 0 ohm (optional) USB GND Board GND
4.1.1 Operation if GPIOn and GPIOx are Different Pins
Any GPIO pins can be defined as GPIOn and GPIOx. GPIOn should be a GPIO which can bring the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB
Intel® PXA255 Processor Design Guide 4-1 USB Interface
connect is detected, then software enables the UDC peripheral and drives a 1 onto the GPIOx pin to indicate to the host PC a fast USB device is connected. If a USB disconnect is detected, then software must configure the GPIOx pin as an input, configure the GPIOn pin to detect a wakeup event, and then put the part into sleep mode.
Also, at any time, you may use software to put the part into sleep mode. Before entering sleep mode, configure the GPIOx pin as an input to cause the UDC+ line to float. This looks like a disconnect to the host PC. The device can then be put into sleep mode. When the device becomes active, software must drive a 1 onto the GPIOx pin to indicate to the host PC a fast USB device has been connected.
4.1.2 Operation if GPIOn and GPIOx are the Same Pin
Out of reset, GPIOn is configured as an input and configured to cause an interrupt whenever a rising or falling edge is detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is connected or not. This pin is 1 if the cable is connected or 0 if the cable is disconnected. If the USB cable is connected, then software must enable the UDC peripheral before the host sends the first USB command. If the USB cable is not connected, then software must configure the GPIOn pin to detect a wakeup event, and then put the part into sleep mode.
4.2 Bus Powered Device
The processor cannot support a bus powered device model. When the host sends a suspend, the device is required to consume less than 500 µA (Section 7.2.3 of the USB spec version 1.1). The processor cannot limit its current consumption to 500 uA unless it enters sleep mode. If it enters sleep mode, all USB registers are reset and it does not respond to its host-assigned address.
4-2 Intel® PXA255 Processor Design Guide MultiMediaCard (MMC) 5
The MultiMediaCard (MMC) is a low cost data storage and communication media. The MMC supports the translation protocol from a standard MMC or Serial Peripheral Interface (SPI) bus to an application bus.
The MMC controller in the processor is compliant with The MultiMediaCard System Specification, Version 2.1. The only exception is one and three byte data transfers are not supported. The MMC controller is capable of communicating with a card in MMC or SPI mode. Your application is responsible for specifying the MMC controller communication mode.
5.1 Schematics
The MultiMediaCard (MMC) controller on the processor supports MMC and SDCard devices. (The MMC controller does not support SDCard nibble mode.) This section presents several options on how to connect each type of device to the controller.
5.1.1 Signal Description
MMC controller signal functions are described in Table 5-1.
Table 5-1. MMC Signal Description
Signal Name Input/Output Description
MMCLK Output Clock signal to MMC MMCMD BiDirectional Command line MMDAT BiDirectional Data line MMCCS0 Output Chip Select 0 MMCCS1 Output Chip Select 1
The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the processor general purpose input/output (GPIO) module. Each of these signals can be programmed to a particular GPIO pin.
The signals defined in The MultiMediaCard System Specification for an MMC device are CLK, CMD, and DAT which correspond to the MMCLK, MMCMD, and MMDAT in the processor, respectively. The two chip selects in the controller are for the MMC SPI mode and correspond to the reserved pin of two different devices, defined in the specification.
The signals defined in the Physical Layer Specification of the SD Memory Card Specifications for an SDCard device are CLK, CMD, and DAT0-DAT3. The obvious difference is the number of DAT signals. In addition, the socket for an SDCard contains mechanical switches for write protect (WP) and card detect (CD). For an SDCard to be connected to the MMC controller, only one data line, DAT0, is used. Otherwise the signal mapping remains the same as an MMC device. The WP and CD switches on the socket are discussed in Section 5.1.2, “How to Wire” on page 5-2.
Intel® PXA255 Processor Design Guide 5-1 MultiMediaCard (MMC)
5.1.2 How to Wire
Notice in the example schematic (Figure 5-1, “Processor MMC and SDCard Signal Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in Table 5-2.
Table 5-2. SDCard Socket Signals
Signal Name Pin #
DAT3 1 CMD 2 VSS1 3 VDD 4 CLK 5 VSS2 6 DAT0 7 DAT1 8 DAT2 9
As stated previously, the PXA255 processor MMC controller can be connected to either an MMC device or an SDCard device, but you are limited to which device installs in which socket. Refer to Table 5-3 for information on sockets and device supported by the MMC controller.
Table 5-3. MMC Controller Supported Sockets and Devices
Sockets Devices Supported
SDCard device SDCard socket MMC device MMC socket MMC device
Figure 5-1 is a schematic that supports both MMC and SDCard devices. In the schematic, the signals SA_MMCLK, SA_MMCMD, and SA_DAT correspond to the processor signals MMCLK, MMCMD, and MMDAT, respectively. These three signals are also directly connected to the socket.
5-2 Intel® PXA255 Processor Design Guide MultiMediaCard (MMC)
Figure 5-1. Processor MMC and SDCard Signal Connections
DC3P3V J10
R147 10K Bottom Mount DAT2 0 SA_MMCMD CD_DAT3 1 MMC_C50 CMD 2 C91 0.1uF VSS1 3 VDD 4 MMC_PWR CLK 5 SA_MMCCLK DNI IF MMC R225 VSS2 6 7 0K DAT0 SA_MMDAT DAT1 8 DC3P3V DC3P3V R150 DNI
0K IF CHECK II 47.5K R226 SD DNI WP COMM CD IF R227 100K SD 10 11 12 nMMC_DETECT DC3P3V CARD Selection Resistors and Values DNI Resistors SDCard MMC IF R228 R226 DNI 0 100K MMC MMC_WP R227 DNI 100K R225 0 DNI R228 100K DNI R229 100K
U27 DC5P5V MIC5207- 3.38M5 3.3V LDO REG 180ns 5 VOUT MMC_PWR 1 VIN 2 GND 1 3 BYP 4 MMC_ON EN
LE33 C92 4.7uF 2
A8698-01
MMC_CS0, which corresponds to the processor MMCCS0 signal, is connected to the socket at pin 1. This connection is the SPI mode chip select and is available on both MMC and SDCard. This pin is also labeled DAT3. DAT3 is only used with an SDCard in SDCard mode and not available on the processor MMC controller.
The signals DAT1 and DAT2 are not connected because these are specific to SDCard operation in SDCard mode.
Intel® PXA255 Processor Design Guide 5-3 MultiMediaCard (MMC)
Three other signals shown on the connector are COMM and the mechanical switches write protect (WP) and card detect (CD). When a device is inserted in the example schematic (Figure 5-1), WP may be and CD is connected to COMM via a mechanical switch inside the socket
SDCard devices have a write protect tab. Depending on the position of the tab, the WP signal may or may not be connected to the COMM signal. Connect the WP signal to a CPLD or other device capable of indicating to the driver software that the card is write protected. In this example, COMM is tied to a VCC and WP has a pull-down resistor. This causes a rising edge when the tab is in the write protect position and the WP signal remains low when the tab is in the read/write position.
The CD signal, MMC_DETECT, indicates to the MMC controller when a card is installed. It is used for both an SDCard socket and an MMC socket. Since the MMC socket does not have the mechanical CD switch, other measures must be taken to produce a card detect. Thus, the SDCard and MMC cases are discussed separately.
Note: While this schematic shows two ways to create a card detect, it is recommended that an SDCard socket be used if a card detect and write protection signal are desired even if only MMC devices are being used.
5.1.2.1 SDCard Socket
When using Figure 5-1, “Processor MMC and SDCard Signal Connections” on page 5-3 as a template for your SDCard circuit design, all resistors labeled “DNI IF SD” should not be installed and all resistors labeled “DNI IF MMC” should be installed in the circuit. Removing R226 and inserting R225 causes the VSS2 signal on pin 6 to be tied to ground. Also, the SDCard needs a pull-down resistor in position R228.
SDCard sockets have a card detect switch internal to the socket. The CD signal is physically connected to the COMM signal. Connect the CD signal to a CPLD or other device capable of indicating to the driver software that a card has been inserted in the socket. In this example, COMM is tied to a VCC and CD has a pull-down resistor. This causes a rising edge on CD when a card is inserted while the CD signal remains low if no card is in the socket.
5.1.2.2 MMC Socket
When using Figure 5-1, “Processor MMC and SDCard Signal Connections” on page 5-3 as a template for your MMC circuit design, all resistors labeled “DNI IF MMC” should not be installed and all resistors labeled “DNI IF SD” should be installed in the circuit. This causes the VSS2 signal on pin 6 to be pulled-up through resistor R227.
Unlike SDCard sockets, MMC sockets do not have a card detect or write protect switch. In order to implement this, a pull-up is placed on the VSS2 signal (pin 6 of the socket.) Since VSS2 and VSS1 are connected internally on the MMC device, the signal called nMMC_DETECT on the schematic is driven low when the MMC device is inserted.
5-4 Intel® PXA255 Processor Design Guide MultiMediaCard (MMC)
Warning: Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard System Specification, Version 2.1. Because the MMC specification does not state that VSS1 and VSS2 must be connected internal to the MMC device, the design in Figure 5-1 may not work with all MMC devices. Use caution when using the card detection method shown in Figure 5-1.
5.1.3 Simplified Schematic
Figure 5-2 shows another SDCard socket. In this case, all processor signals are connected to the socket. This socket does not have a common signal for the write protect and card detect and are connected to the two tabs shown on the left side of the diagram. Inserting a card into the socket may cause the write protect signal and will cause the card detect signal to change states and must be interpreted by the CPLD software. Figure 5-2. Processor MMC to SDCard Simplified Signal Connection
+3.3V
Jx Rx Rx Rx Rx ESD 10K Ω 10K Ω 10K Ω 10K Ω 5% 0.1W 5% 0.1W 5% 0.1W 5% 0.1W 11 SD_WP WP SD_CD CD 10 DAT1 8 MMDAT DAT0 7 VSS2 6 MMCLK CLK 5 VDD 4 VSS1 3 2 MMCMD CMD MMCCS0 CD/DAT3 1 DAT2 9
GND
5638 SDMC_NORMAL_SPRG_EJCT 12Kyoc 10 5638 009 353 833 13
A8699-01
5.1.4 Pull-up and Pull-down
Table 5-4 and Table 5-5 show the pull-up and pull-down resistors required for SDCard and MMC devices according to their respective specifications.
Intel® PXA255 Processor Design Guide 5-5 MultiMediaCard (MMC)
Table 5-4. SDCard Pull-up and Pull-down Resistors
Signal Pull-up or Pull-down Min Max Remark
CMD pull-up 10kΩ 100kΩ Prevents bus floating DAT0-DAT3 pull-up 10kΩ 100kΩ Prevents bus floating WP1 pull-up — — Any value sufficient to prevent bus floating NOTE: 1. This resistor is shown in the specification but the value is not specified
Table 5-5. MMC Pull-up and Pull-down Resistors
Signal Pull-up or Pull-down Min Max Remark
CMD pull-up 4.7kΩ 100kΩ Prevents bus floating DAT pull-up 50kΩ 100kΩ Prevents bus floating
5.2 Utilized Features
The processor MultiMediaCard controller has these features: • Data transfer rates as fast as 20 Mbps • A16 bit response FIFO • Dual receive data FIFOs • Dual transmit FIFOs • Support for two MMCs in either MMC or SPI mode
The sample schematics in this section support MMC and SDCard and are configured to use MMC or SPI mode.
The processor MultiMediaCard controller and the MMC device have the same maximum data rate, 20 Mbps, so their communication rates are compatible. However, because the maximum processor MultiMediaCard controller data rate is 20 Mbps and the maximum SDCard data rate is 25 Mbps, SDCard devices are not utilized to their fullest extent.
The circuit designs presented in this guide (Figure 5-1 and Figure 5-2) only show support for one SDCard or MMC device, but the processor MultiMediaCard controller handles as many as two devices.
5-6 Intel® PXA255 Processor Design Guide AC97 6
The AC97 controller unit (ACUNIT) connects audio chips and codecs to the processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs may be connected to the ACUNIT.
6.1 Schematics
The schematics for an AC97 connection are shown in Figure 6-1. The primary codec supplies the 12.288 MHz clock to the AC97. This clock is then driven into the ACUNIT on the processor and the AC97 Secondary Codec. Figure 6-1. AC97 connection
nACRESET SDATA_OUT SYNC (48 KHz) AC97 PXA255 Primary AC97 SDATA_IN_0 CODEC Controller SDATA_IN_1 BITCLK (12.288MHz)
AC97 Secondary Codec
Intel® PXA255 Processor Design Guide 6-1 AC97
6.2 Layout
Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout procedures be followed. Intel recommends you follow the layout recommendations given in your Codec datasheet. Some general recommendations are: • Use a separate power supply for the analog audio portion of the design. • Place a digital power/ground plane keep-out underneath the analog portion. Use a separate analog ground plane. You can create an island inside the keep-out. Connect the digital ground pins of the codec to the digital ground. Keep the two ground planes on the same layer, with at least 1/8 of an inch separation between them. • Connect the two ground planes underneath your codec with a 0 ohm jumper. Add optional Do Not Populate 0 ohm jumpers between analog and digital ground at the power supply. Excessive noise on the board may be reduced by installing the 0 ohm resistor. • Do not route digital signals underneath the analog portion. Digital traces must go over the digital ground plane, analog traces over the analog plane. • Buffer any digital signals to or from the codec that go off the board, for example, if your codec is on a daughter card. • Fill the areas between analog traces with copper tied to the analog ground. Fill the regions between digital traces with copper tied to the digital ground. • Locate the decoupling capacitors for the analog portion as close to the codec as possible.
6-2 Intel® PXA255 Processor Design Guide I2C 7
The Inter-Integrated Circuit (I2C) bus interface unit lets the PXA255 processor serve as a master and slave device residing on the I2C bus. The I2C bus is a serial bus developed by Philips Corporation consisting of a two-pin interface. SDA is the serial data line and SCL is the serial clock line.
Using the I2C bus lets the processor interface to other I2C peripherals and microcontrollers for system management functions. The serial bus requires a minimum of hardware for an economical system to relay status and reliability information to an external device.
The I2C bus interface unit is a peripheral device that resides on the processor internal bus. Data is transmitted to and received from the I2C bus via a buffered interface. Control and status information is relayed through a set of memory-mapped registers. Refer to the I2C Bus Specification for complete details on I2C bus operation.
7.1 Schematics
The I2C bus is used by many different applications. This reference guide presents two possible methods for using the I2C bus interface. The first method controls a digital-to-analog converter (DAC) to vary the DC voltage to the processor core. The second method expands the capabilities of an existing compact flash socket.
7.1.1 Signal Description
The I2C bus interface unit signals are SDA and SCL. Table 7-1 describes the function of each signal.
Table 7-1. I2C Signal Description
Signal Name Input/Output Description
SDA BiDirectional Serial data SCL BiDirectional Serial clock
The I2C bus serial operation uses an open-drain, wired-AND bus structure, which allows multiple devices to drive the bus lines and to communicate status about events such as arbitration, wait states, error conditions and so on. For example, when a master drives the clock (SCL) line during a data transfer, it transfers a bit on every instance that the clock is high. When the slave is unable to accept or drive data at the rate that the master is requesting, the slave can hold the clock line low between the high states to insert a wait interval. The master’s clock can only be altered by a slow slave peripheral keeping the clock line low or by another master during arbitration.
The I2C bus lets you design a multi-master system; meaning more than one device can initiate data transfers at the same time. To support this feature, the I2C bus arbitration relies on the wired-AND connection of all I2C interfaces to the I2C bus. Two masters can drive the bus simultaneously provided they are driving identical data. The first master to drive SDA high while another master drives SDA low loses the arbitration. The SCL line consists of a synchronized combination of clocks generated by the masters using the wired-AND connection to the SCL line.
Intel® PXA255 Processor Design Guide 7-1 I2C
7.1.2 Digital-to-Analog Converter (DAC)
Figure 7-1 shows the schematic for connecting the I2C interface to a Linear Technology micropower DAC. The DAC output is connected to the buck converter feedback path and is controlled by the I2C bus interface unit. The DAC can modify the voltage of the feedback path, which effects the processor core voltage. Figure 7-1. Linear Technology DAC with I2C Interface
DC3P3V R165 1.00M
U30 LTC1663 4 VCC VOUT 3 1 SA_I2C_SDA SDA
5 SA_I2C_SCL SCL GND 2
LTEP LTC1663C35
A8752-01
The signals SA_I2C_SDA and SA_I2C_SCL correspond to the processor signals SDA and SCL, respectively.
7.1.3 Other Uses of I2C
Figure 7-2 shows the I2C signals passing through an analog switch to a compact flash socket. Since the CF socket has all of the signals to support two CF cards, and this design only uses one CF card, the signals meant for a second card are being used for alternate functions. If you decide not to use a CF card, a different application using a CF card socket could be designed to utilize the I2C bus interface unit. If this alternate function is used, the I2C bus can be enabled to the CF socket by asserting the signal SA_I2C_ENAB shown in the diagram. If the user decides to use a CF Card, negate the SA_I2C_ENAB signal so the I2C bus traffic does not interfere with the CF card.
Note: The CF card socket is disabled if a device is inserted in the expansion bus.
7-2 Intel® PXA255 Processor Design Guide I2C
. Figure 7-2. Using an Analog Switch to Allow a Second CF Card
DC3P3V
U26 MAX4547 V* 2
8 SA_I2C_SCL COM_1 1 NC_1 CF_I2C_SCL 7 IN_7
NC_2 5 CI_I2C_SDA 4 SA_I2C_SDA COM_7 3 SA_I2C_ENAB IN_2 GND 6
AAAF
A8750-01
7.1.4 Pull-Ups and Pull-Downs
The I2C Bus Specification, available from Philips Corporation, states: The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to 200 pF, the pull-up device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device can be a current source (3 mA max.) or a switched resistor circuit.
The design presented in this guide is not intended for loads larger than 200pF, so the pull-up device is a resistor as shown in Figure 7-3. Figure 7-3. I2C Pull-Ups and Pull-Downs
DC3P3V
R4 SA_I2C_SCL 4.99K
R5 SA_I2C_SDA 4.99K
A8751-01
Intel® PXA255 Processor Design Guide 7-3 I2C
The actual value of the pull-up is system dependant and a guide is presented in the I2C Bus Specification on determining the maximum and minimum resistors to use when the system is intended for standard or fast-mode I2C bus devices.
7.2 Utilized Features
The processor I2C bus interface unit is compatible with the two pin interface developed by Phillips Corporation. A complete list of features and capabilities can be found in the I2C Bus Specification.
7-4 Intel® PXA255 Processor Design Guide Power and Clocking 8
8.1 Operating Conditions
Table 8-1 shows voltage, frequency, and temperature specifications for the PXA255 processor for four different ranges. The temperature specification for each range is constant; the frequency range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should have a range from 0.95 V to 1.65 V. PLL_VCC and VCC must be connected together on the board or driven by the same supply.
Table 8-1. Voltage, Temperature, and Frequency Electrical Specifications
Symbol Description Min Typical Max
tCE Extended Case Temperature -40° C — 100° C
tCC Commercial Case Temperature 0° C — 85° C
VVSS VSS, VSSN, VSSQ Voltage -0.3 V 0 V 0.3 V
VVCCQ VCCQ 3.0 V 3.3 V 3.6V
VVCCN_H VCCN @ 3.3V 3.0 V 3.3 V 3.6V Low Voltage Range
VVCC_L VCC, PLL_VCC Voltage, Low Range 0.95 V 1.0 V 1.32 V
fTURBO_L Turbo Mode Frequency, Low Range 99.5 MHz — 132.7 MHz
fSDRAM_L External Synchronous Memory Frequency, Low Range — — 66.4 MHz Medium Voltage Range
VVCC_M VCC, PLL_VCC Voltage, Mid Range 0.95 V 1.0 V 1.32 V
fTURBO_M Turbo Mode Frequency, Mid Range 99.5 MHz — 199.1 MHz
fSDRAM_M External Synchronous Memory Frequency, Mid Range — — 99.5 MHz High Voltage Range
VVCC_H VCC, PLL_VCC Voltage, High Range 1.045 V 1.1 V 1.43 V
fTURBO_H Turbo Mode Frequency, High Range 99.5 MHz — 298.7 MHz
fSDRAM_H External Synchronous Memory Frequency, High Range — — 99.5 MHz Peak Voltage Range
VVCC_P VCC, PLL_VCC Voltage, Peak Range 1.235 V 1.3 V 1.65 V
fTURBO_P Turbo Mode Frequency, Peak Range 99.5 MHz — 398.2 MHz
fSDRAM_P External Synchronous Memory Frequency, Peak Range — — 99.5 MHz NOTE: When VCCN=2.5 V, the I/O signals that are supplied by VCCN are 2.5 V tolerant only. Do not apply 3.3 V to any pin supplied by VCCN in this case.
Intel® PXA255 Processor Design Guide 8-1 Power and Clocking
8.2 Electrical Specifications
Table 8-2 provides the Absolute Maximum ratings for the processor. These parameters may not be exceeded or the part may be permanently damaged. Operation at absolute maximum ratings is not guaranteed.
Table 8-2. Absolute Maximum Ratings
Symbol Description Min Max
TS Storage Temperature -40° C 125° C Offset Voltage between any two VSS pins V -0.3 V 0.3 V SS_O (VSS, VSSQ, VSSN) Offset Voltage between any of the following pins: V -0.3 V 0.3 V CC_O VCCQ, VCCN Voltage Applied to High Voltage Supplies V VSS-0.3 V VSS+4.0 V CC_HV (VCCQ, VCCN) Voltage Applied to Low Voltage Supplies V VSS-0.3 V VSS+1.45 V CC_LV (VCC, PLL_VCC) max of VIP Voltage Applied to non-Supply pins except XTAL pins VSS-0.3 V VCCQ+0.3 V, VSS+4.0 V max of Voltage Applied to XTAL pins V VSS-0.3 V VCC+0.3 V, IP_X (PXTAL, PEXTAL, TXTAL, TEXTAL) VSS+1.45 V Maximum ESD stress voltage, Human Body Model; Any pin to any supply pin, either polarity, or V 2000 V ESD Any pin to all non-supply pins together, either polarity. Three stresses maximum.
IEOS Maximum DC Input Current (Electrical Overstress) for any non-supply pin 5mA
8.2.1 Power Supply Connectivity
The PXA255 processor requires two or three externally-supplied voltage levels. VCCQ requires high voltage, VCCN requires high or medium voltage, and VCC and PLL_VCC require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on the availability of independent regulator outputs and the desired memory voltage, VCCQ may have to be separated from VCCN. VCCN does not have to be separated at the board level.
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 1 of 6)
Pin Power Pin Signal Description and Comments Count Supply
MA(25:0) 26 Main Memory Address Bus VCCN
MD(31:0) 16 Main Memory Data Bus VCCN
nOE 1 Main Memory Bus Output Enable VCCN
nWE 1 Main Memory Bus Write Enable VCCN
nSDRAS 1 Main Memory Bus RAS VCCN
nSDCAS 1 Main Memory Bus CAS VCCN
8-2 Intel® PXA255 Processor Design Guide Power and Clocking
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 2 of 6)
Pin Power Pin Signal Description and Comments Count Supply
Main Memory Bus SDRAM byte DQM(3:0) 2 VCCN selects
Main Memory Bus SDRAM chip nSDCS(3:0) 2 VCCN selects
Main Memory Bus SDRAM clock SDCKE(1:0) 2 VCCN enable
SDCLK(2:0) 1 Main Memory Bus SDRAM clocks VCCN
RD/nWR 1 CC Steering Signal VCCN
CS(0) 1 Static chip select VCCN
GP15 1 Active low chip select 1 VCCN
GP18 1 External Bus Ready VCCN
GP19 1 External Bus Master Request VCCN
GP20 1 External Bus Master Request VCCN
GP21 1 General Purpose I/O pin VCCN
GP22 1 General Purpose I/O pin VCCN
GP33 1 Active low chip select 5 VCCN
Output Enable for Card Space GP48 1 VCCN HWUART transmit
Write Enable for Card Space GP49 1 VCCN HWUART receive
I/O Read for Card Space GP50 1 VCCN HWUART clear to send
I/O Write for Card Space GP51 1 VCCN HWUART request to send
GP52 1 Card Enable for Card Space VCCN
Card Enable for Card Space GP53 1 VCCN MMC CLock
MMC CLock GP54 1 VCCN Socket Select for Card Space
GP55 1 Card Address bit 26 VCCN
GP56 1 Wait signal for Card Space VCCN
GP57 1 Bus Width select for I/O Card Space VCCN
GP78 1 Active low chip select 2 VCCN
GP79 1 Active low chip select 3 VCCN
Intel® PXA255 Processor Design Guide 8-3 Power and Clocking
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 3 of 6)
Pin Power Pin Signal Description and Comments Count Supply
GP80 1 Active low chip select 4 VCCN
GP81 1 Network SSP Clock VCCQ
GP82 1 Network SSP Frame VCCQ
GP83 1 Network SSP TXD/RXD VCCQ
GP84 1 Network SSP TXD/RXD VCCQ
MMCMD 1 MMC Command VCCQ
MMDAT 1 MMC Data VCCQ
AC_RESET_n 1 ac97 RESET VCCQ
UDC+ 1 USB client high differential signal VCCQ
UDC- 1 USB client low differential signal VCCQ
SCL 1 I2C Clock VCCQ
SDA 1 I2C Bidirectional Data VCCQ
nRESET 1 Hardware reset VCCQ
nRESET_OUT 1 Reset output VCCQ
BOOT_SEL[2:0] 3 ROM Width Select (16/32) VCCQ
PWR_EN 1 power enable VCCQ
nBATT_FAULT 1 Battery Fault VCCQ
nVDD_FAULT 1 VDD Fault VCCQ
nTRST 1 JTAG Reset VCCQ
TDI 1 JTAG Data In VCCQ
TDO 1 JTAG Data Out VCCQ
TMS 1 JTAG Mode Select VCCQ
TCK 1 JTAG Clock VCCQ
TESTCLK 1 TEST Clock VCCQ
TEST 1 TEST mode VCCQ
GP0 1 Reserved for sleep wakeup VCCQ
GP1 1 Active low GP_reset VCCQ
GP2 1 General Purpose I/O pin VCCQ
GP3 1 General Purpose I/O pin VCCQ
GP4 1 General Purpose I/O pin VCCQ
GP5 1 General Purpose I/O pin VCCQ
GP6 1 MMC Clock VCCQ
8-4 Intel® PXA255 Processor Design Guide Power and Clocking
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 4 of 6)
Pin Power Pin Signal Description and Comments Count Supply
GP7 1 48 mhz clock output VCCQ
GP8 1 MMC Chip Select 0 VCCQ
GP9 1 MMC Chip Select 1 VCCQ
GP10 1 real time clock (1Hz) VCCQ
GP11 1 3.6 MHz oscillator out VCCQ
GP12 1 32 KHz out VCCQ
GP13 1 memory controller grant VCCQ
GP14 1 Alternate Bus Master Request VCCQ
GP16 1 PWM0 output VCCQ
GP17 1 PWM1 output VCCQ
GP23 1 SSP clock VCCQ
GP24 1 SSP Frame VCCQ
GP25 1 SSP transmit VCCQ
GP26 1 SSP receive VCCQ
GP27 1 SSP ext_clk VCCQ
AC97 bit_clk
I2S bit_clk GP28 1 VCCQ I2S bit_clk
AC97 bit_clk
AC97 Sdata_in0 GP29 1 VCCQ I2S Sdata_in
I2S Sdata_out GP30 1 VCCQ AC97 Sdata_out
I2S sync GP31 1 VCCQ AC97 sync
I2S sysclk GP32 1 VCCQ AC97 Sdata_in1
FFUART receive GP34 1 VCCQ MMC Chip Select 0
GP35 1 FFUART Clear to send VCCQ
GP36 1 FFUART Data carrier detect VCCQ
GP37 1 FFUART data set ready VCCQ
Intel® PXA255 Processor Design Guide 8-5 Power and Clocking
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 5 of 6)
Pin Power Pin Signal Description and Comments Count Supply
GP38 1 FFUART Ring Indicator VCCQ
MMC Chip Select 1 GP39 1 VCCQ FFUART transmit data
GP40 1 FFUART data terminal Ready VCCQ
GP41 1 FFUART request to send VCCQ
BTUART receive data GP42 1 VCCQ HWUART receive data
BTUART transmit data GP43 1 VCCQ HWUART transmit data
BTUART clear to send GP44 1 VCCQ HWUART clear to send
BTUART request to send GP45 1 VCCQ HWUART request to send
ICP receive data GP46 1 VCCQ STD_UART receive data
STD_UART transmit data GP47 1 VCCQ ICP transmit data
GP58 1 LCD data pin 0 VCCQ
GP59 1 LCD data pin 1 VCCQ
GP60 1 LCD data pin 2 VCCQ
GP61 1 LCD data pin 3 VCCQ
GP62 1 LCD data pin 4 VCCQ
GP63 1 LCD data pin 5 VCCQ
GP64 1 LCD data pin 6 VCCQ
GP65 1 LCD data pin 7 VCCQ
LCD data pin 8 GP66 1 VCCQ Alternate Bus Master Request
LCD data pin 9 GP67 1 VCCQ MMC Chip Select 0
MMC Chip Select 1 GP68 1 VCCQ LCD data pin 10
8-6 Intel® PXA255 Processor Design Guide Power and Clocking
Table 8-3. PXA255 Processor VCCN vs. VCCQ (Sheet 6 of 6)
Pin Power Pin Signal Description and Comments Count Supply
MMC_CLK GP69 1 VCCQ LCD data pin 11
Real Time clock (1Hz) GP70 1 VCCQ LCD data pin 12
3.6MHz Oscillator clock GP71 1 VCCQ LCD data pin 13
32 KHz clock GP72 1 VCCQ LCD data pin 14
LCD data pin 15 GP73 1 VCCQ memory controller grant
GP74 1 LCD Frame clock VCCQ
GP75 1 LCD line clock VCCQ
GP76 1 LCD Pixel clock VCCQ
GP77 1 LCD AC Bias VCCQ
PXTAL 1 3.6Mhz Crystal input 0.8 * VCC
PEXTAL 1 3.6Mhz Crystal output 0.8 * VCC
TXTAL 1 32khz Crystal input 0.8 * VCC
TEXTAL 1 32khz Crystal output 0.8 * VCC
8.3 Example Form Factor Reference Design Power Delivery Example
8.3.1 Power System
Features of the example form factor reference design power system (example in Figure 8-1, “Example Form Factor Reference Design Power System Design” on page 8-8) are: • A standard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity • Battery temperature monitoring thermistor during charge cycles • Battery voltage monitoring • Charger supply voltage fault monitoring • Low battery interrupt signal to the microprocessor. • Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio amplifier subsystems • Provide a high-efficiency 5.5 V supply rail for LCD and other devices
Intel® PXA255 Processor Design Guide 8-7 Power and Clocking
• Provide a high-efficiency 3.3 V supply rail for I/O and general system power • Provide a high-efficiency 1.0 V – 1.3 V Core/PLL supply for the microprocessor • Provide separate, clean power rails for the LCD and Audio subsystems • A small, low-cost, low-heat dissipation pulse-charge method for the battery
8.3.1.1 Power System Configuration
The example form factor reference design power system design is described in Figure 8-1, “Example Form Factor Reference Design Power System Design” on page 8-8. Note that there are four main power rails in the system: • 3.3 V I/O power • 1.0-1.3 V Core/PLL power • 5.5 V power Figure 8-1. Example Form Factor Reference Design Power System Design
LDO ON/OFF Audio AMP
LDO Audio_DC3P3V ON/OFF
LDO ON/OFF MMC_VDD LDO LCD_DC3P3V 3.3V ON/OFF
LDO ON/OFF LCD_DC5V LDO ON/OFF 3.2V
LDO LCD_DC4V ON/OFF
LDO LCD_DC15V ON/OFF CF_VDD 3.3V Boost LCD_DC14V- Converter MAX633 LCD_DC11P7V- Boost Converter LTC1308A DC_5P5V
LDO 3.2 V
LDO DC_3P3V 3.3 V
DC_CORE Buck Converter 0.8 - 1.3 V LTC1878
Wall Battery Input DC_PLL Charger Current LDO LTC1730 1.3 V Limited battery
8-8 Intel® PXA255 Processor Design Guide Power and Clocking
8.3.2 CORE Power
The example form factor reference design has a variable 1.0 V – 1.3 V core power supply for the processor. This voltage varies depending on the performance required by the application. A Linear Technologies LTC1878 buck converter is chosen for this application. The power is drawn directly from the Li+ battery. This device operates at 550 kHz and can supply up to 1 A at 1.0 V and 800 mA at 1.3 V with up to 95% efficiency. The device is turned on/off by the SA_PWR_EN signal directly from the processor.
The required output voltage is statically adjusted by selecting the value of the feed-back resistor. Ultimately, output voltage can be changed using software control of the Linear Technologies LTC1663 DAC. This DAC is controllable via the standard I2C bus, and can modify the voltage of the feedback path of the buck converter, which effects a change in the output voltage.
8.3.3 PLL Power
DC_PLL supplies power to the three PLLs within the processor. This pin requires a 1.0 V to 1.3 V nominal supply at an expected 20 mA load.
8.3.4 I/O 3.3 V Power
A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+ battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for the Li+ battery: • 4.1 – 3.8 V zone 10% of the time; • 3.7 – 3.6 V zone at 70% of the time; • 3.5 – 3.4 V at 10% of the time; and • 3.4 – 3.1 V at 10% of the time.
The ADP3335 operates in zone 1,2, 3, and cutoffs in zone 4.
The overall efficiency is: 0.1(3.3/4.0) + 0.7(3.3/3.6) + 0.1(3.3/3.4) = 0.0825 + 0.642 + 0.097 = 0.82
To access the energy in zone 4 use the second LDO linear regulator in a parallel configuration with the ADP3335 and set it to output 3.2 V. Input to this regulator is 5.5 V from the boost converter. When the battery voltage drops below 3.5 V, the ADP3335 drops-out and the second regulator takes over.
8.3.5 Peripheral 5.5 V Power
The example form factor reference design provides a 5.5 V rail to supply power to LCD, Audio amplifier and Radio modules. An LT1308A boost converter is used. This device supplies up to 1 A at 5.5 V while operating at 600 kHz with up to 90% efficiency at rated load and 3.6 V input.
Intel® PXA255 Processor Design Guide 8-9 Power and Clocking
In addition, a low battery voltage detect circuit has an open-drain output. The detect voltage is set at 3.45 V by a resistor divider circuit. When the battery drops below 3.45 V the output transitions to a logic low. This output signal is used as a processor interrupt.
8-10 Intel® PXA255 Processor Design Guide JTAG/Debug Port 9
9.1 Description
The JTAG/Debug port is essentially several shift registers, with the destination controlled by the TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash programming. JTAG is also a hardware debug port.
9.2 Schematics
All JTAG pins, except for nTRST and TCK, are directly connected. TCK is not driven internally and so you must add an external pull-up or pull-down resistor. Intel recommends adding a 1.5 k pull-down resistor to TCK. nTRST must be asserted during power-on. Asserting nRESET or nTRST must not cause the other reset signal to assert. Also, use an external pull-up resistor on nTRST to prevent spurious resets of the JTAG port when disconnected. The circuit in Figure 9-1 drives nTRST. It uses a reset IC on nTRST to ensure that nTRST is reset at power-on. nRESET must be directly connected to the CPU nRESET. Do not connect pins 17 and 19 – they are special purpose functions and not used. Figure 9-1. JTAG/Debug Port Wiring Diagram
3.3 V
1 2 RESET nTRST MR 3 4 MAX823 TDI 5 6 TMS 7 8 TCK 9 10 1.5K GND 11 12 TDO 13 14 nRESET 15 16 17 18 19 20
If you are not utilizing either JTAG or the hardware debug functions, it is highly recommended that you design in a JTAG/debug port on your system anyway. This greatly facilitates board debug, startup, and software development. During final production you would not have to populate the JTAG connector.
Intel® PXA255 Processor Design Guide 9-1 JTAG/Debug Port
9.3 Layout
Use the JTAG/Debug the port layout recommendations given in ARM’s application note, Multi- ICE System Design Considerations, Application Note 72. The recommended connector is a 2x10- way, 2.54 mm pitch pin header, shown in Figure 9-1.
If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end and the smaller pitch connector on the other.
Place the JTAG/Debug connector as close as possible to the PXA255 processor to minimize signal degradation.
If you follow these design recommendations, a JTAG bridge board is not required. Essentially, the JTAG bridge board for the example form factor reference design uses a 220 ohm resistor to tie nTRST high so that the JTAG logic can be brought out of reset (otherwise it would not come out of reset since nTRST is open-drain).
9-2 Intel® PXA255 Processor Design Guide SA-1110/Processor Migration A
The PXA255 processor represents the next generation follow-on to Intel® StrongARM* SA-1110 product. This appendix highlights the migration path needed to change an SA-1110 design to one that uses the processor.
The majority of application code running on the SA-1110 will directly run on the processor, but there are substantial differences in hardware implementation and low-level coding, especially device configuration, that need to be noted.
The processor has numerous new hardware and software features that substantially benefit a handheld product design. The processor can be considered a superset of the SA-1110, but with so many new features direct socket compatibility is impractical.
For a detailed analysis of the differences between these products, refer to the full specifications of each device: • SA-1110 Advanced Developers Manual, Order# 278240 [http://developer.intel.com] • Intel® PXA255 Processor Developer’s Manual, Order# 278693 • ARM* Architecture Reference Manual, Order# ARM DDI 0100D-10 • Intel 80200 Developers' manual, Order# 273411-002 [http://developer.intel.com]
Or later updated versions of any of the above.
This appendix is separated into sections that focus on three different issues: 1. SA-1110 hardware migration issues — Hardware Compatibility — Signal Changes —Power Delivery — Package —Clocks — UCB1300 2. SA-1110 software migration issues — Software Compatibility — Address space — Page Table Changes — Configuration registers —DMA 3. Using new features in the processor — Intel® XScale™ microarchitecture — Debugging
Intel® PXA255 Processor Design Guide A-1 SA-1110/Processor Migration
- Cache attributes - Other Features - Conclusion
A.1 SA-1110 Hardware Migration Issues
A.1.1 Hardware Compatibility
The majority of the features provided in the SA-1110 are also provided in the PXA255 processor. However, with the additional functionality of the PXA255 processor, the two devices are not pin compatible and cannot occupy the same socket.
There has been an effort to ensure Companion Devices that take advantage of SA-1110 memory interface access works with the PXA255 processor. The memory controls for taking over the memory bus such as those exercised by the SA-1111, are included in the PXA255 processor memory bus interface however, there are some issues.
One difference in particular is the way PXA255 processor toggles the A1 and A0 address lines. The SA-1110 toggled A1 and A0 regardless of the size of the data bus. With PXA255 processor, if the data bus is set to 16-bit, then A0 does not toggle and if the data bus is set to 32-bit, then neither A1 nor A0 toggles.
There is a big difference in manufacturing technology between the SA-1110 and the PXA255 processor. The most significant change being from a 0.35 micron CMOS technology to a finer lithography of 0.18 microns. Aside from a potential impact to signal edge rates this allows for lower processor voltage operation.
A.1.2 Signal Changes
There are two pins that control SA-1110 boot-up: • ROM select pin that selects a 16 or 32-bit interface • Synchronous Mask ROM enable pin that selects a synchronous or asynchronous ROM access
The PXA255 processor has three pins that select eight different boot select options (see Table A-1. The subset of these options that are SA-1110 equivalent are not compatible with the PXA255 processor pin polarities, so these pins must be selected afresh when designing with the PXA255 processor.
Table A-1. PXA255 Processor Boot Select Options (Sheet 1 of 2)
Boot Select Pins Boot Location 210
0 0 0 Asynchronous 32-bit ROM 0 0 1 Asynchronous 16-bit ROM 0 1 0 Synchronous 32-bit Flash 0 1 1 Synchronous 16-bit Flash
A-2 Intel® PXA255 Processor Design Guide SA-1110/Processor Migration
Table A-1. PXA255 Processor Boot Select Options (Sheet 2 of 2)
Boot Select Pins Boot Location 210
(1) Synchronous 32-bit Mask ROM (64 Mbit) 100 (2) Synchronous 16-bit Mask ROM = 32bits (32 Mbit) 1 0 1 (1) Synchronous 16-bit Mask ROM (64 Mbit) 1 1 0 (2) Synchronous 16-bit Mask ROM = 32bits (64 Mbit) 1 1 1 (1) Synchronous 16-bit Mask ROM (32 Mbit)
The power fault (VDD_FAULT) and battery fault (BATT_FAULT) pins that drive the SA-1110 sleep mode are negated with respect to the PXA255 processor. You must invert these signals or change the design to make sure that these signals are negated with respect to the SA-1110 design.
The PXA255 processor treats variable latency IO differently than the SA-1110. The difference occurs only when a static chip select is configured to support variable latency IO, i.e. the bus cycle is to be extended by a value on the RDY pin. In this configuration, the SDRAM refresh cycle retains the use of the nWE pin to allow the memory bus to be held for an indeterminate time. During any variable latency IO cycle, the PCMCIA pin nPWE is used to write to an external device instead of the nWE pin.
Note: Holding the bus for extended periods is not recommended because it interferes with the LCD DMA and prevents an LCD panel refresh.
This change in write enables only causes an issue if an external companion bus master device has a single write enable pin and requires variable latency IO to be accessed. As shown in Figure A-1, the write enable to the companion master has to be gated to differentiate between a case where the PXA255 processor uses the WE to write to the companion and a case where the companion uses the WE to write into SDRAM memory. Gating the WE pin with the Bus Grant signal (as shown) segregates the two different memory bus cycle types. If the companion bus master has both a WE input pin and a WE output pin to SDRAM, this logic is unnecessary. Figure A-1. Write Enable Control Pins
SDRAM
~MBGNT
nWE WE# SA-1110 PXA255 nPWE Companion Device MBGNT
Intel® PXA255 Processor Design Guide A-3 SA-1110/Processor Migration
A.1.3 Power Delivery
Although both products are tolerant to 3.3 V inputs and outputs, there is a difference in the supply voltage that drives the transistors of the microprocessor megacell. The PXA255 processor takes advantage of lower supply voltages to offer substantial power consumption savings. A design using SA-1110 has a supply voltage of 1.55 V to 1.75 V. The PXA255 processor is rated to 1.4 V maximum.
Drive the PXA255 processor core voltage pins at a lower voltage than the SA-1110 to reduce overall power consumption. The choice of voltage impacts the maximum upper frequency of operation so check the PXA255 processor documentation for the correct voltages as they are application dependent.
Also notice that the PXA255 processor supports independent power sources for Core, IO, Memory Bus, phase lock loops (PLLs), and a backup battery. It is recommended that these be independent power sources.
A.1.4 Package
The SA-1110 and the PXA255 processors are similar but not identical. The ball pitch of 1 mm is the same and the body outlines are both 17x17 mm but the heights are different. The PXA255 processor contains 4-layers within the package making it fractionally thicker than the SA-1110 2- layer package.
A.1.5 Clocks
The crystal inputs for the PXA255 processor are at the same frequency as those for the SA-1110: • High frequency input of 3.6864 MHz • Slow real-time clock source of 32.768 KHz.
The input frequency requirements are relatively low, such that any crystal that is an AT-cut style with a certain amount of shunt capacitance will work for both products.
The actual PLL design and process technology is different between the two products, such that a marginal SA-1110 design may not work with the PXA255 processor. Please refer to the product specifications of each device for further details.
You can program GPIO pins to generate various clocks in both the SA-1110 and the PXA255 processors. For example, these are often used in audio codec designs to generate clocks. The inter- relationships of some of these clocks have changed from the SA-1110 to the PXA255 processor. You may need to select different GPIO pins and program different configuration registers to provide similar functionality.
A.1.6 UCB1300
The SA-1110 supports a unique serial protocol for communication with the Philip's UCB product family: UCB1100, 1200 and 1300. This serial interface is not available on the PXA255 processor. Instead the PXA255 processor supports several industry standard Audio codec Interfaces. You may also use I2S/I2C combinations and an AC'97 interface.
A-4 Intel® PXA255 Processor Design Guide SA-1110/Processor Migration
If an SA-1110 design utilizes this UCB interface then an alternative choice of components is necessary for the PXA255 processor.
A.2 SA-1110 to PXA255 Processor Software Migration Issues
The difficulty of migrating software from the SA-1110 to the PXA255 processor depends on the amount of hardware and software interaction. SA-1110 applications running under an Operating System, which use device driver interfaces, should move seamlessly between the two devices.
There is one exception; any application that explicitly uses the Read Buffer to prefetch external memory data into the SA-1110. This buffer does not exist on the PXA255 processor and register #9 in Coprocessor #15 that was used to access it are not compatible to software.
As the Read Buffer prefetching activity was deemed to be a hint rather than an instruction, applications can simply delete all references to the Read Buffer and still function correctly. They may not even suffer a performance penalty, as the PXA255 processor 'hit-under-miss' cache feature can turn the entire data space into a prefetchable region without any explicit software direction.
Alternately, as a patch for software that cannot be modified, all applications must be limited to User Mode execution, whereupon an Exception can be generated for all Coprocessor activity. Such an exception manager needs to filter out the Read Buffer coprocessor calls, or convert them to PXA255 processor PLD instructions that can preload a data cache value.
There are major software difference within the device initialization/configuration software and device drivers, such as low-level code that controls the hardware.
The PXA255 processor has enhanced functionality and extra instructions not found in the SA- 1110. The PXA255 processor software is not backward compatibility to the SA-1110. Once code is compiled for the PXA255 processor it is unlikely to run on the SA-1110.
A.2.1 Software Compatibility
Because the PXA255 processor uses Intel® XScale™ microarchitecture, the PXA255 processor has a different pipeline length relative to the SA-1110. This effects code performance when migrating between the two devices varies because of the number of clock cycles needed for execution. Any application that relies on specific cycle counts, or has specific timing components, will show a difference in performance.
The PXA255 processor features: larger caches, Branch target buffering, and faster multiplication, and so many applications run faster than the SA-1110 when running at the same clock frequency.
A.2.2 Address space
The physical address mapping of gross memory regions is not compatible between the PXA255 processor and SA-1110. For example, on the PXA255 processor, static chip selects 4 and 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the memory space.
Intel® PXA255 Processor Design Guide A-5 SA-1110/Processor Migration
Changes of this kind could be managed by the Operating System remapping virtual memory pages to new physical addresses. This assumes that the Operating System has basic support for virtual memory, but not if this could be managed by initialization code modifications effecting the same change.
More significantly, memory-mapped registers may have different names, new addresses and different functionality. This impacts all device drivers and register-level firmware, that at a minimum, requires re-mapping register address and changing the default configuration.
A.2.3 Page Table Changes
There are differences in the virtual memory Page Table Descriptors between the SA-1110 and the PXA255 processors that impact software execution speed. A new bit has been added to differentiate ARM* compliant operation modes from some features Intel includes such as access to the Mini-Data-Cache.
If any software attempts to explicitly control page table modifications, normally the domain of the Operating System, then that software may need annotation to allow for the extra opportunities the PXA255 processor offers.
Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to utilize a different cache is lost without a page table bit being changed. The impact here is performance not functionality.
A.2.4 Configuration registers
There are numerous device configuration changes in the PXA255 processor. You must now select the configuration options for clock speeds such as Turbo Mode. This requirement is not found on the SA-1110.
You must choose memory clocks, LCD clock rates, audio clocks and interfaces, which GPIOs are actually connected to hardware, and many more. There are no easy solutions here, the device space of the PXA255 processor is very diverse and a number of selections must be made in software to select your particular hardware functionality.
All software that controls registers will need to be updated. If a switch is connected to a GPIO, then the software that reads the switch register will differ between the PXA255 processor and SA-1110. This applies to software that controls Configuration registers in Coprocessor space and also to a number of the memory-mapped registers. Many functions such as memory timing configuration are done through these registers. For example the registers to access USB have a different name, address and function. Any code that directly accesses the USB hardware registers will need to be rewritten.
A.2.5 DMA
The SA-1110 contains a 6-channel DMA controller that pipes data between the serial channels and memory. The PXA255 processor provides a far more substantial 16-channel chained DMA controller that can be configured to do much more than the SA-1110, including memory-to- memory block moves.
A-6 Intel® PXA255 Processor Design Guide SA-1110/Processor Migration
Clearly there are changes in software required to take advantage of this new asset. However this also implies changes necessary to maintain similar functionality to the SA-1110. To configure a DMA channel you no longer set it to a specific serial port, instead you map it to the specific source or destination address of the serial port FIFO. You must configure other parameters for address incrementing and memory width that differ between the PXA255 processor and SA-1110.
Any device driver using the SA-1110 DMA controller, or application that takes direct advantage of DMA, will need to be modified. The impact of this varies as some Operating Systems and many device drivers have ignored the SA-1110 DMA in favor of programmed I/O.
Some have argued to remove the required interrupt management code as they only move small blocks. Operating systems have excluded DMA to guarantee they can manage the real-time behavior of different threads. Other software providers saw the serial ports as so slow that DMA performance was unnecessarily complex.
The performance benefit of the PXA255 processor DMA controller is one of the most significant improvements over the SA-1110, particularly in the area of memory-to-memory moves. Changing code on the PXA255 processor to utilize the new DMA functionality will significantly enhance applications.
A.3 Using New PXA255 Processor Features
This appendix doesn't attempt to discuss all the differences between the PXA255 processor and the SA-1110 or it would become quite substantial. There are numerous significant advantages that the PXA255 processor has to offer, all of which potentially require changes in hardware, firmware or software development tools. This section lists just a few of the chief additional benefits of the PXA255 processor. However, refer to the product specifications for further details. This list is not comprehensive.
A.3.1 Intel® XScale™ Microarchitecture
The PXA255 processor is a system on a chip that includes Intel's new microprocessor megacell. This includes Intel® Superpipelined Technology and a new optimized cache architecture that allows program execution to continue despite data cache misses.
The PXA255 processor supports: • ARM* Architecture v5 instructions, including ARM's Thumb extensions • DSP Extensions but not ARM's optional Vector Floating Point instructions
Appendix A in the Intel 80200 Developers' manual, Order# 273411-002 [http:// developer.intel.com], is the best guide to the new capabilities available in the Intel® XScale™ Megacell's Instruction Set.
Using a software development toolset that takes specific advantage of Intel® XScale™ microarchitecture, and Intel® Media Processing Technology could give you substantial performance benefits.
The PXA255 processor offers increased performance at similar clock rates, and also a wider range of operating clock rates at lower voltages. The overall benefit is more work done for less battery power.
Intel® PXA255 Processor Design Guide A-7 SA-1110/Processor Migration
A.3.2 Debugging
New PXA255 processor hardware creates new debugging possibilities. You can use the JTAG test port to download programs into a dedicated memory area to act as a debug monitor. Applications can be inspected and performance data, such as cache hit rates, can be measured via a dialog over JTAG. These features offer developers far more visibility inside a PXA255 processor system improving time to market.
A.3.3 Cache Attributes
The PXA255 processor has twice the instruction cache and four times the data cache of the SA- 1110. The Caches can be locked for optimized code or data and for reliability the caches are now covered by parity protection.
To take advantage of cache locking software, data must be selected and specifically loaded and locked into cache.
To take advantage of new features such as Write-Through mode for external IO buffers, page tables will need to be revisited in boot software.
A.3.4 Other features
As mentioned before, the PXA255 processor DMA controller is highly versatile. With 16 channels it can be utilized as: • Several serial ports in parallel • A general-purpose memory move capability • A fast interface for external companion devices
Additional software is required to access these benefits.
A similar story is true for AC'97, I2C, GPIOs, MMC and others. The benefits are substantial, but new hardware and software will be necessary to effectively use the PXA255 processor.
A.3.5 Conclusion
Although most application software will migrate unchanged between SA-1110 and the PXA255 processors, the underlying microarchitectures are radically different. The PXA255 processor being considerably more ornate and capable than the SA-1110. The majority of hardware and low-level software from any SA-1110 design will need to be redesigned. with a view to taking full advantage of the new features that the PXA255 processor brings to the handheld market.
A-8 Intel® PXA255 Processor Design Guide Example Form Factor Reference Design Schematic Diagrams B
B.1 Notes
The example form factor reference design schematics in this appendix have known issues and assumptions that need to be assessed for each board design. This appendix documents the issues that have been discovered and provides revision data for the schematics. This appendix also points out some of the design specific assumptions that were made in designing this board.
Page 4: The schematic supports the SA1110 legacy mode for addressing the SDRAM. See SDRAM section of the design guidelines to explain normal vs. legacy addressing modes.
Page 10: U26 allows the CF card to access the I2C interface.
Page 11: The MMC slot has resistor jumpers to select SDCARD and/or MMC card support. If the users wants to support both SCARD and MMC, populate the resistor values in the SD column of the CARD selection table. If MMC card support only populate the resistors under the MMC column in the table.
Page 11: The JTAG port on this board assumes that it is connected to a specific JTAG bridge board. If you follow this design guide, you should not need the bridge board. See the JTAG section of this document for more details on this bridge board implementation.
Page 11: J19 pin 9 requires a 1.5 k pull down.
Page 13: U33, U34, U35, U40, and surrounding circuits are to support a legacy sharp LCD. Refer to that vendor's design guidelines if you are integrating a different LCD display.
Page 14: U36, U37, U39, J13, and surrounding circuits including the resistor divider network in the upper left hand corner support a legacy Sharp LCD. Refer to that vendor's design guidelines if you are integrating a different LCD display.
Page 14: J14 is the Toshiba LCD connector. Confirm the pinout before layout.
B.2 Schematic Diagrams
The example form factor reference design schematics for the PXA255 processor are on the following pages. The PXA255 processor is a drop in replacement and is fully compatible with these schematics.
Intel® PXA255 Processor Design Guide B-1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg.1
D D
Example Form Factor Reference Design for PXA250
Page Description C C 1 Cover Sheet 2-3 PXA250 Processor 4 SDRAM, System Configuration Register 5 Intel Flash Memory (BGA) 6 Buffer, CPLD, Board Control Register 7 Transceivers 8 Audio Codec, Audio AMP 9 Headset Jack, Microphone, Stereo Jack, Speaker, Dual Axis Accelerometer, IrDA, USB B 10 Basestation Hdr, RS232 Xcvr, CF Socket, Function Switches B 11 SD socket, Radio Header, JTAG Port 12 Boost Buck Power , Battery Header, Battery On Jumper 13 LCD CPLD, LCD Power, Back Light Connector 14 LCD Connectors, 9 Channel Buffer, Touch Screen Connector 15 Bus Connectors, 2-140 Pin 16 Schematic Revision Page
A A Rev 2.07 PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 1 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation DC3P3V R205 Pg.2 {6} SA_A0 R237 22.1 U1A {6} SA_A1 R1 22.1 R238 {6,15} SA_nPWAIT {5,6} SA_A2 Intel PXA250 Processor 100K R239 22.1 G1 N4 {5,6} SA_A3 A_0 D_0 SA_D0 {4,5,6,7} H2 M5 R2 A_1 D_1 SA_D1 {4,5,6,7} {6,15} SA_nIOIS16 22.1 R240 H1 L5 {5,7} SA_A4 A_2 D_2 SA_D2 {4,5,6,7} 100K H6 T6 D A_3 D_3 SA_D3 {4,5,6,7} D R241 22.1 J6 N6 {5,7} SA_A5 A_4 D_4 SA_D4 {4,5,6,7} R3 J5 A_5 D_5 T7 SA_D5 {4,5,6,7} {15} SA_RDY 22.1 R242 J3 M6 {5,7} SA_A6 A_6 D_6 SA_D6 {4,5,6,7} 100K J1 Address and Data Buses M7 SA_D7 {4,5,6,7} R243 22.1 A_7 D_7 R4 {5,7} SA_A7 K1 A_8 D_8 M9 SA_D8 {4,5,6,7} K2 T10 A_9 D_9 SA_D9 {4,5,6,7} {10,12,15} SA_I2C_SCL 22.1 R244 K5 R9 4.99K {5,7} SA_A8 A_10 D_10 SA_D10 {4,5,6,7} K6 A_11 D_11 T11 SA_D11 {4,5,6,7} R245 22.1 L1 P11 R5 {5,7} SA_A9 A_12 D_12 SA_D12 {4,5,6,7} L3 N10 22.1 R246 A_13 D_13 SA_D13 {4,5,6,7} {10,12,15} SA_I2C_SDA M1 T12 SA_D14 {4,5,6,7} {4,5,7} SA_A10 A_14 D_14 4.99K M3 A_15 D_15 M10 SA_D15 {4,5,6,7} R247 22.1 N3 H3 {4,5,7} SA_A11 A_16 D_16 SA_D16 {4,5,7} P1 H5 R137 22.1 R248 A_17 D_17 SA_D17 {4,5,7} {6} SA_nCS_1 {4,5,7} SA_A12 R1 A_18 D_18 J4 SA_D18 {4,5,7} 100K P2 A_19 D_19 K3 SA_D19 {4,5,7} R249 22.1 R3 L4 {4,5,7} SA_A13 A_20 D_20 SA_D20 {4,5,7} T4 M2 R263 A_21 D_21 SA_D21 {4,5,7} {6} SA_nCS_2 22.1 R250 R5 N1 {4,5,7} SA_A14 A_22 D_22 SA_D22 {4,5,7} 100K P5 A_23 D_23 T3 SA_D23 {4,5,7} R251 22.1 T5 P6 {4,5,7} SA_A15 A_24 D_24 SA_D24 {4,5,7} P4 R7 R264 A_25 D_25 SA_D25 {4,5,7} {6,15} SA_nCS_3 22.1 R252 P7 {4,5,7} SA_A16 D_26 SA_D26 {4,5,7} 100K P8 C R253 22.1 D_27 SA_D27 {4,5,7} C {4,5,7} SA_A17 D_28 L8 SA_D28 {4,5,7} P10 R265 D_29 SA_D29 {4,5,7} {6,15} SA_nCS_4 22.1 R254 R11 {4,5,7} SA_A18 D_30 SA_D30 {4,5,7} 10K D11 P12 {10,12,15} SA_I2C_SCL SCL D_31 SA_D31 {4,5,7} R255 22.1 A11 I2C {4,5,7} SA_A19 {10,12,15} SA_I2C_SDA SDA R266 {6,15} SA_nCS_5 22.1 R256 C12 {4,5,7} SA_A20 {9} SA_UDCP UDCP 10K B12 USB Ch N8 {9} SA_UDCN UDCN nCS_0 SA_nCS_0 {6,15} R257 22.1 T8 {4,5,7} SA_A21 nCS_1_GPIO15 SA_nCS_1 {6} C15 P9 R267 {9} IR_TXD IR_TXD_GPIO47 nCS_2_GPIO78 SA_nCS_2 {6} {6,15} SA_nPCE_1 22.1 R258 B15 IrDA Ch T9 {4,5,7} SA_A22 {9} IR_RXD IR_RXD_GPIO46 nCS_3_GPIO79 SA_nCS_3 {6,15} 100K nCS_4_GPIO80 R13 SA_nCS_4 {6,15} R259 22.1 B14 T13 {4,5,7} SA_A23 {11} SA_BT_RTS BT_RTS_GPIO45 nCS_5_GPIO33 SA_nCS_5 {6,15} A15 R268 {11} SA_BT_CTS BT_CTS_GPIO44 {6,15} SA_nPCE_2 22.1 R260 D13 BT Ch {4,5,7} SA_A24 {11,15} SA_BT_TXD BT_TXD_GPIO43 100K {11,15} SA_BT_RXD B13 BT_RXD_GPIO42 DQM_0 M8 SA_DQM_0 {4,7} R261 22.1 B1 {6,7} SA_A25 DQM_1 SA_DQM_1 {4,7} B9 B2 R269 EXTCLK_GPIO27 DQM_2 SA_DQM_2 {4,7} {6,15} SA_RD_nWR 22.1 E9 L7 R10 SFRM_C_GPIO24 DQM_3 SA_DQM_3 {4,7} 100K F9 {11} RADIO_RI SCLK_C_GPIO23 D9 F1 0 R9 TXD_C_GPIO25 nSDCS_0 SA_nSDCS_0{4,7} A9 SSP Ch G6 R281 {11} RADIO_DTR RXD_C_GPIO26 nSDCS_1 {3,12} nCHRGR_PRESENT G3 R8 0 nSDCS_2 SA_nSDCS_2{6} 100K B D14 F2 B {11} RADIO_DSR MMCCMD nSDCS_3 0 B16 MMC R7 MMCDAT R272 {11} RADIO_DCD H14 MMCCLK_GPIO6 SDCKE_0 E4 SA_SDCKE_0{15} F14 E3 R6 0 MMCCS0_GPIO8 SDCKE_1 SA_SDCKE_1{4,6} {3,6,15} MBGNT_CF_IRQ B6 {11} MMC_WP nMMCCD_GPIO12 4.99K 0 SDCLK_0 D2 SA_SDCLK_0{5,15} B10 F5 {10} SA_FF_RI FF_RI_GPIO38 SDCLK_1 SA_SDCLK_1{4,7} A12 FF Ch D1
R148 {10} SA_FF_DCD FF_DCD_GPIO36 rol SDCLK_2 SA_SDCLK_2{6} B11 {11} RADIO_RXD_C {10} SA_FF_DSR FF_DSR_GPIO37 F10 E1 0 {10} SA_FF_DTR FF_DTR_GPIO40 nSDRAS SA_nSDRAS{4,6,7} DNI F8 F3 {10} SA_FF_RTS FF_RTS_GPIO41 nSDCAS SA_nSDCAS{4,5,6,7} A14 {10} SA_FF_CTS FF_CTS_GPIO35 R11 {10,15} SA_FF_TXD E13 FF_TXD_GPIO39 nOE G5 SA_nOE {5,7} A13 G4 {11} SA_MMCMD {10,15} SA_FF_RXD FF_RXD_GPIO34 nWE SA_nWE {4,5,6,7,10}
R12 Memory Cont 47.5 P13 D3 {11} SA_MMDAT {6,15} SA_nPOE nPOE_GPIO48 RD_nWR SA_RD_nWR{6,15} T14 C1 47.5 R13 {6,15} SA_nPWE nPWE_GPIO49 RDY_GPIO18 SA_RDY {15} {11} SA_MMCCLK {6,15} SA_nPIOR T15 nPIOR_GPIO50 R15 N15 {6,15} SA_nPIOW nPIOW_GPIO51 DVAL_0_GPIO21 GPIO_21 {10,11} 47.5 P14 M12 {11} MMC_CS0 {6,15} SA_nPCE_1 nPCE_1_GPIO52 DVAL_1_GPIO22 GPIO_22 {10,11} {6,15} SA_nPCE_2 R16 nPCE_2_GPIO53 DREQ_0_GPIO20 N12 GPIO_20 {10,11} P16 N14 {11,13} nMMC_DETECT {15} SA_PSKTSEL PSKTSEL_GPIO54 DREQ_1_GPIO19 GPIO_19 {10,11} M13
{6,15} SA_nPREG nPREG_GPIO55 CARD Interface N16 A {6,15} SA_nPWAIT nPWAIT_GPIO56 A M16 D10 SA_nAC97_RESET{8} {6,15} SA_nIOIS16 nI0IS16_GPIO57 AC97 nAC97_RESET SYNC_GPIO31 E11 SA_SYNC {8} F15 NC1 SDATA_OUT_GPIO30 A10 SA_SDATA_OUT{8} D16 NC2 SDATA_IN0_GPIO29 E10 SA_SDATA_IN{8} E15 C9 SA_BITCLK {8} NC3 BITCLK_GPIO28 PXA250 Processor Reference Design E16 NC4 F16 NC5 PWM_0_GPIO16 E12 SA_PWM_0{13} Pulse Width Size Rev B 2.07 PXA250_MBGA256 Date: Tuesday, February 05, 2002 Sheet 2 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation U1B Pg.3 Intel PXA250 Processor DC3P3V DC3P3V DC3P3V L_DD_0_GPIO58 E7 L_DD_0 {13} L10 D7 {10,15} GPIO_0 GPIO_0 L_DD_1_GPIO59 L_DD_1 {13} L12 C7 {9,15} USB_WAKE GPIO_1 L_DD_2_GPIO60 L_DD_2 {13} L13 B7 {10} SA_I2C_ENAB GPIO_2 L_DD_3_GPIO61 L_DD_3 {13} K14 E6 {10,15} GFX_IRQ_CF_BVD2 GPIO_3 L_DD_4_GPIO62 L_DD_4 {13} J12 D6 D {10} RS232_VALID GPIO_4 L_DD_5_GPIO63 L_DD_5 {13} D J11 E5 DNI DNI DNI {2,12} nCHRGR_PRESENT GPIO_5 L_DD_6_GPIO64 L_DD_6 {13} G15 A6 R18 R19 R20 {8} AC97_IRQ GPIO_7 L_DD_7_GPIO65 L_DD_7 {13} 100K 100K 100K F12 C5 {10,15} SA1111_IRQ_CF_BVD1 GPIO_9 L_DD_8_GPIO66 L_DD_8 {4,13} F7 A5 {12,15} nVBATT_LOW_IRQ GPIO_10 L_DD_9_GPIO67 L_DD_9 {4,13} {13} GPIO_11 A7 GPIO_11 L_DD_10_GPIO68 D5 L_DD_10 {4,13} {6,15} MBGNT_CF_IRQ B5 GPIO_13 L_DD_11_GPIO69 A4 L_DD_11 {4,13} B4 A3 {13,15} MBREQ_CF_DETECT GPIO_14 L_DD_12_GPIO70 L_DD_12 {4,13} D12 A2 {10} GPIO_17 GPIO_17 L_DD_13_GPIO71 L_DD_13 {4,13} {15} BOOT_SEL_0 {15} BOOT_SEL_1 BOOT_SEL_2 {10} GPIO_32 A16 GPIO_32 L_DD_14_GPIO72 C3 L_DD_14 {4,13} L_DD_15_GPIO73 B3 L_DD_15 {4,13} LCD Port L_FCLK_GPIO74 E8 L_FCLK {13} L_LCLK_GPIO75 D8 L_LCLK {13} B8 R23 R24 R25 L_PCLK {13} 10K 10K 10K GPIO Port L_PCLK_GPIO76 L_BIAS_GPIO77 A8 L_BIAS {13} H12 {6,10,11,13} JTAG_TCK TCK LAYOUT: Keep Close in DC3P3V H15 {13} CPLD2_TDO TDI a Matrix and in an H16 JTAG Y4 DNI {10,11} SA_TDO TDO Accessible location. {6,10,11,13} JTAG_TMS H13 TMS 1 4 H11 Y1 {11} JTAG_nTRST nTRST Add Silk screen Box. R271 2 3 2 1 J13 K11 {10,11,15} nRESET_IN nRESET nRESET_OUT nRESET_OUT{6,11,13,15} C 681 C 3.6864Mhz 3.6864MHZ {15} BOOT_SEL_0 G16 BOOT_SEL_0 G13 {15} BOOT_SEL_1 BOOT_SEL_1 F13 DC3P3V BOOT_SEL_2 BOOT_SEL_2 K15 PXTAL 3.6Mhz K16 PEXTAL
L16 TXTAL L15 32Khz Y2 TEXTAL R48 2 1 R21 R22
100K 100K 0 32.768KHZ L11 {12,13} SA_PWR_EN PWR_EN K12 G11 nBATT_FAULT TESTCLK R51 DC_CORE K13 nVDD_FAULT TEST G12 0 F11 C16 {13} nVDD_FAULT {8,10,11,12,13,14} VBATT DC_CORE VDD_1 VSS_1 G7 VDD_2 VSS_2 H8 G9 H9 U2 VDD_3 VSS_3 H10 VDD_4 VSS_4 J8 J7 J9
0 VDD_5 VSS_5 K8 T1 R200 MAX6328 VDD_6 VSS_6 1 K10 GND VDD_7 L6 VDD_8 VSSN_1 C2 B C10 C11 C12 C13 C14 B L9 VDD_9 VSSN_2 E2 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 3 G2 DC3P3V VIN VSSN_3 VSSN_4 J2 2 RESET A1 VDDN_1 VSSN_5 L2 D4 N2 Capacitors for Core U3 DC3P3V VDDN_2 VSSN_6 F4 VDDN_3 VSSN_7 R2 MAX6328XR27-T-SC H4 R4 MAX811TEUS-T VDDN_4 VSSN_8 K4 VDDN_5 VSSN_9 R6 4 M4 R8 DC3P3V VCC {12} PLL_SENSE VDDN_6 VSSN_10 M14 VDDN_7 VSSN_11 R10 2 N5 R12 RESET nRESET_IN{10,11,15} VDDN_8 VSSN_12 3 N7 R14 MR VDDN_9 VSSN_13 1 N9 M15 GND {12} DC_PLL DC3P3V VDDN_10 VSSN_14 N11 VDDN_11 VSSN_15 P15 N13 VDDN_12 DC3P3V P3 C4 2 3 VDDN_13 VSSQ_1 T16 C8
0 VDDN_14 VSSQ_2 R27
1_Ohm C11 S1 R277 VSSQ_3 7A J15 C14 PLL_VCC VSSQ_4 C6 C7 C8 C9 0.1UF 0.1UF 0.1UF 0.1UF J16 F6 0.1UF PLL_SENSE VSSQ_5 C123 R26 Top RESET 1_Ohm T2 VCCKP VSSQ_6 G8 B D15 ADC_VCC VSSQ_7 G10 M11 BATT_VCC VSSQ_8 H7 VSSQ_9 J10 A 1 4 DC3P3V A C6 VDDQ_1 VSSQ_10 J14 Capacitors for VDDX C10 VDDQ_2 VSSQ_11 K7 C13 VDDQ_3 VSSQ_12 K9 C15 C16 0.1UF 0.1UF E14 VDDQ_4 VSSQ_13 L14 G14
0 VDDQ_5 BALL 12-11-00 PXA250 Processor Reference Design R262
PXA250_MBGA256 Size Rev 0.1UF C125 B 2.07
Date: Tuesday, February 05, 2002 Sheet 3 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 4 U4 SDRAM SYSTEM CONFIGURATION REGISTER 23 {2,5,7} SA_A10 A0 {2,5,7} SA_A11 24 A1 25 4M x 4 x 16 DC3P3V {2,5,7} SA_A12 A2 26 SDRAM {2,5,7} SA_A13 A3 29 {2,5,7} SA_A14 A4 SDRAM Bank Addressing: 30 {2,5,7} SA_A15 A5 31 D {2,5,7} SA_A16 A6 D 32 SDRAM Address Bus wired for
{2,5,7} SA_A17 A7 10K 33 R28 DNI {2,5,7} SA_A18 A8 SA1110 legacy compatibility mode 34 {2,5,7} SA_A19 A9 22 for SDRAM Bank Addressing. {2,5,7} SA_A20 A10 R29 SD_SZ_0 {2,5,7} SA_A21 35 A11 NC 40 {3,13} L_DD_8 36 {2,5,7} SA_A24 A12 100K 2 DC3P3V D0 SA_D0 {2,5,6,7} D1 4 SA_D1 {2,5,6,7} 0 19 5 R30 {2,7} SA_nSDCS_0 nCS D2 SA_D2 {2,5,6,7} 16 7 {2,5,6,7,10} SA_nWE nWE D3 SA_D3 {2,5,6,7} 17 8 SA_D4 {2,5,6,7}
{2,5,6,7} SA_nSDCAS nCAS D4 10K 18 10 R31 DNI {2,6,7} SA_nSDRAS nRAS D5 SA_D5 {2,5,6,7} D6 11 SA_D6 {2,5,6,7} 13 R32 SD_SZ_1 D7 SA_D7 {2,5,6,7} {3,13} L_DD_9 38 42 {2,7} SA_SDCLK_1 CLK D8 SA_D8 {2,5,6,7} 100K 37 44 DC3P3V {2,6} SA_SDCKE_1 CKE D9 SA_D9 {2,5,6,7} 20 45 SA_D10 {2,5,6,7}
{2,5,7} SA_A23 BS_0 D10 0 21 47 R33 {2,5,7} SA_A22 BS_1 D11 SA_D11 {2,5,6,7} 15 48 DC3P3V {2,7} SA_DQM_0 LDQM D12 SA_D12 {2,5,6,7} {2,7} SA_DQM_1 39 UDMQ D13 50 SA_D13 {2,5,6,7} 51 SA_D14 {2,5,6,7}
D14 10K R34 DNI D15 53 SA_D15 {2,5,6,7} 1 VDD_1 14 28 R35 FLASH_SZ_0 C VDD_2 VSS_1 {3,13} L_DD_10 C 27 41 VDD_3 VSS_2 100K DC3P3V VSS_3 54 3 6
VDD_Q1 VSSQ_1 0 9 VDD_Q2 VSSQ_2 12 R36 C17 C18 0.1UF 0.1UF 43 VDD_Q3 VSSQ_3 46 49 52
VDD_Q4 VSSQ_4 10K R37 DNI
R38 FLASH_SZ_1 {3,13} L_DD_11 100K
DC3P3V 0 R39 U5
{2,5,7} SA_A10 23 A0 24
{2,5,7} SA_A11 A1 10K 25 4M x 4 x 16 R40 DNI {2,5,7} SA_A12 A2 26 SDRAM {2,5,7} SA_A13 A3 29 R41 FLASH_TYPE {2,5,7} SA_A14 A4 {3,13} L_DD_12 30 {2,5,7} SA_A15 A5 100K 31 DC3P3V {2,5,7} SA_A16 A6 32
{2,5,7} SA_A17 A7 0 B 33 R42 B {2,5,7} SA_A18 A8 34 {2,5,7} SA_A19 A9 22
{2,5,7} SA_A20 A10 10K 35 40 R43 DNI {2,5,7} SA_A21 A11 NC 36 {2,5,7} SA_A24 A12 2 R44 D0 SA_D16 {2,5,7} {3,13} L_DD_13 LCD_TYPE {13} 4 D1 SA_D17 {2,5,7} 100K 19 5 DC3P3V {2,7} SA_nSDCS_0 nCS D2 SA_D18 {2,5,7} 16 7 SA_D19 {2,5,7}
{2,5,6,7,10} SA_nWE nWE D3 0 17 8 R45 {2,5,6,7} SA_nSDCAS nCAS D4 SA_D20 {2,5,7} 18 10 {2,6,7} SA_nSDRAS nRAS D5 SA_D21 {2,5,7} D6 11 SA_D22 {2,5,7} 13 SA_D23 {2,5,7}
D7 10K 38 42 R46 {2,7} SA_SDCLK_1 CLK D8 SA_D24 {2,5,7} 37 44 {2,6} SA_SDCKE_1 CKE D9 SA_D25 {2,5,7} 20 45 R47 {2,5,7} SA_A23 BS_0 D10 SA_D26 {2,5,7} {3,13} L_DD_14 nGFX_PRESENT{13,15} 21 47 SA_D27 {2,5,7} {2,5,7} SA_A22 BS_1 D11 100K DC3P3V {2,7} SA_DQM_2 15 LDQM D12 48 SA_D28 {2,5,7} DC3P3V 39 50 {2,7} SA_DQM_3 UDMQ D13 SA_D29 {2,5,7} D14 51 SA_D30 {2,5,7} D15 53 SA_D31 {2,5,7} 1
VDD_1 10K 14 VDD_2 VSS_1 28 R49 27 VDD_3 VSS_2 41 A 54 R50 A VSS_3 {3,13} L_DD_15 nNEP_PRESENT{13,15} 3 6 VDD_Q1 VSSQ_1 100K 9 VDD_Q2 VSSQ_2 12 C19 C20 0.1UF 0.1UF 43 VDD_Q3 VSSQ_3 46 49 52 VDD_Q4 VSSQ_4 PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 4 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation U6 Pg. 5 Intel StrataFlash 16M x 16 Flash Memory G2 F2 A0 DQ0 SA_D0 {2,4,6,7} A1 E2 {2,6} SA_A2 A1 DQ1 SA_D1 {2,4,6,7} B1 G3 {2,6} SA_A3 A2 DQ2 SA_D2 {2,4,6,7} C1 E4 {2,7} SA_A4 A3 DQ3 SA_D3 {2,4,6,7} D1 E5 {2,7} SA_A5 A4 DQ4 SA_D4 {2,4,6,7} D2 G5 {2,7} SA_A6 A5 DQ5 SA_D5 {2,4,6,7} A2 G6 D {2,7} SA_A7 A6 DQ6 SA_D6 {2,4,6,7} Resistor StrataFlash Synchronous D C2 H7 {2,7} SA_A8 A7 DQ7 SA_D7 {2,4,6,7} A3 E1 StrataFlash {2,7} SA_A9 A8 DQ8 SA_D8 {2,4,6,7} B3 E3 {2,4,7} SA_A10 A9 DQ9 SA_D9 {2,4,6,7} C3 F3 {2,4,7} SA_A11 A10 DQ10 SA_D10 {2,4,6,7} R52 DNI IN {2,4,7} SA_A12 D3 A11 DQ11 F4 SA_D11 {2,4,6,7} C4 F5 {2,4,7} SA_A13 A12 DQ12 SA_D12 {2,4,6,7} R53 IN DNI A5 H5 {2,4,7} SA_A14 A13 DQ13 SA_D13 {2,4,6,7} B5 G7 {2,4,7} SA_A15 A14 DQ14 SA_D14 {2,4,6,7} R54 DNI IN C5 E7 {2,4,7} SA_A16 A15 DQ15 SA_D15 {2,4,6,7} DC3P3V D7 {2,4,7} SA_A17 A16 R56 DNI IN D8 E8 DNI {2,4,7} SA_A18 A17 STS A7 DC3P3V {2,4,7} SA_A19 A18 R212 R57 DNI IN B7 B6 {2,4,7} SA_A20 A19 DU1 / NC C7 C6 {2,4,7} SA_A21 A20 DU2 / nWP 0 R52 R212 DNI IN C8 D5 {2,4,7} SA_A22 A21 DU3 / VDDQ A8 D6 0
0 {2,4,7} SA_A23 A22 DU4 / VDDQ R53 G1 {2,4,7} SA_A24 A23 H8 A24 C1 C2 DC3P3V 0.1UF 0.1UF H2 DU8 / VSSQ DNI D4 {13} FLASH_nRP nRP F1 R54 nBYTE E6 G4 {2,15} SA_SDCLK_0 DU5 / CLK V_DDQ R55 F6 A4 C 0 DU6 / ADV V_PEN C F7 DU7 / WAIT 0 A6 R56 VDD_1 F8 H3 {2,4,6,7} SA_nSDCAS {2,7} SA_nOE nOE VDD_2 G8 0 {2,4,6,7,10} SA_nWE nWE B2 VSS_1 C21 C22
B4 H4 0.1UF 0.1UF {6} nFLASH_BOOT_CS nCE_0 VSS_2 B8 H6 nCE_1 VSS_3 CS_AWS H1 nCE_2 BGA 10K R58
DNI 0 U7 R57
Intel StrataFlash 16M x 16 G2 F2 A0 DQ0 SA_D16 {2,4,7} A1 E2 {2,6} SA_A2 A1 DQ1 SA_D17 {2,4,7} B1 G3 {2,6} SA_A3 A2 DQ2 SA_D18 {2,4,7} C1 E4 {2,7} SA_A4 A3 DQ3 SA_D19 {2,4,7} D1 E5 {2,7} SA_A5 A4 DQ4 SA_D20 {2,4,7} D2 G5 {2,7} SA_A6 A5 DQ5 SA_D21 {2,4,7} A2 G6 {2,7} SA_A7 A6 DQ6 SA_D22 {2,4,7} B C2 H7 B {2,7} SA_A8 A7 DQ7 SA_D23 {2,4,7} A3 E1 {2,7} SA_A9 A8 DQ8 SA_D24 {2,4,7} {2,4,7} SA_A10 B3 A9 DQ9 E3 SA_D25 {2,4,7} C3 F3 {2,4,7} SA_A11 A10 DQ10 SA_D26 {2,4,7} D3 F4 {2,4,7} SA_A12 A11 DQ11 SA_D27 {2,4,7} C4 F5 {2,4,7} SA_A13 A12 DQ12 SA_D28 {2,4,7} A5 H5 {2,4,7} SA_A14 A13 DQ13 SA_D29 {2,4,7} {2,4,7} SA_A15 B5 A14 DQ14 G7 SA_D30 {2,4,7} C5 E7 {2,4,7} SA_A16 A15 DQ15 SA_D31 {2,4,7} D7 {2,4,7} SA_A17 A16 D8 E8 {2,4,7} SA_A18 A17 STS A7 {2,4,7} SA_A19 A18 B7 B6 {2,4,7} SA_A20 A19 DU1 / NC C7 C6 {2,4,7} SA_A21 A20 DU2 / nWP C8 D5 {2,4,7} SA_A22 A21 DU3 / VDDQ A8 D6 {2,4,7} SA_A23 A22 DU4 / VDDQ G1 {2,4,7} SA_A24 A23 H8 A24
H2 DU8 / VSSQ D4 nRP F1 DC3P3V nBYTE E6 G4 DU5 / CLK V_DDQ F6 A4 A DU6 / ADV V_PEN A F7 DU7 / WAIT A6 VDD_1 F8 H3 nOE VDD_2 G8 nWE B2 VSS_1 C23 C24 PXA250 Processor Reference Design
B4 H4 0.1UF 0.1UF nCE_0 VSS_2 B8 H6 nCE_1 VSS_3 H1 nCE_2 BGA Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 5 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation U8 Pg. 6 CF_PWR_ON {13} 16_Bit Buffer/Line Buffer Driver R59 74LVCH162244A 100K 47 2 R60 {2,15} SA_nPIOW 1A1 1Y1 CF_nPIOW {10} 46 3 {2,15} SA_nPOE 1A2 1Y2 CF_nPOE {10} 100K 44 5 D SA_nPWE 1A3 1Y3 CF_nPWE {10} D {2,15} 43 6 Board Control {2,15} SA_nPIOR 1A4 1Y4 CF_nPIOR {10} CF_GFX_RESET {10,15} IRDA_FSEL {9} 41 8 Register {2} SA_nSDCS_2 2A1 2Y1 VX_nSDCS_2 {15} IRDA_MD0 {9} DC3P3V {2,15} SA_nPCE_2 40 2A2 2Y2 9 CF_nPCE_2 {10} IRDA_MD1 {9} {2,4} SA_SDCKE_1 38 2A3 2Y3 11 VX_SDCKE_1 {15} CF_nBUS_ON 37 12 VX_SDCLK_2 {2} SA_SDCLK_2 2A4 2Y4 {15} U9 R61 {10} CF_nPWAIT 36 3A1 3Y1 13 SA_nPWAIT {2,15} 35 14 {10} CF_nIOIS16 3A2 3Y2 SA_nIOIS16 {2,15} 100K {2,15} SA_nPREG 33 3A3 3Y3 16 CF_nPREG {10} 74LVCH16374A 32 17 R62 {2,15} SA_nPCE_1 3A4 3Y4 CF_nPCE_1 {10} 16-Bit Edge Triggered 100K 30 19 {2,5} SA_A3 4A1 4Y1 VX_A3 {10,15} D-Type Flip Flop 29 20 47 2 {2,5} SA_A2 4A2 4Y2 VX_A2 {10,15} {2,4,5,7} SA_D0 1D1 1Q1 AUDIO_PWR_ON {8} 27 22 46 3 {2} SA_A1 4A3 4Y3 VX_A1 {10,15} {2,4,5,7} SA_D1 1D2 1Q2 26 23 44 5 SA_A0 4A4 4Y4 VX_A0 {10,15} {2,4,5,7} SA_D2 1D3 1Q3 LIGHT_PWR_ON {13} {2} 43 6 {2,4,5,7} SA_D3 1D4 1Q4 1 4 41 8 {7} nVX_CF_OE 1nOE VSS_1 {2,4,5,7} SA_D4 1D5 1Q5 48 10 40 9 R63 2nOE VSS_2 {2,4,5,7} SA_D5 1D6 1Q6 CF_nBUS_ON 25 3nOE VSS_3 15 {2,4,5,7} SA_D6 38 1D7 1Q7 11 100K DC3P3V 24 21 37 12 4nOE VSS_4 {2,4,5,7} SA_D7 1D8 1Q8 VSS_5 28 7 34 36 13 VDD_1 VSS_6 {2,4,5,7} SA_D8 2D1 2Q1 LCD_PWR_ON {13,14} 18 39 35 14 C VDD_2 VSS_7 {2,4,5,7} SA_D9 2D2 2Q2 C 31 VDD_3 VSS_8 45 {2,4,5,7} SA_D10 33 2D3 2Q3 16 42 32 17 R64 VDD_4 {2,4,5,7} SA_D11 2D4 2Q4 30 19 {2,4,5,7} SA_D12 2D5 2Q5 100K {2,4,5,7} SA_D13 29 2D6 2Q6 20 C25 C26 0.1UF 0.1UF {2,4,5,7} SA_D14 27 22 RS232_ON {10} 74LVCH162244APF 2D7 2Q7 {2,4,5,7} SA_D15 26 2D8 2Q8 23 nBCR_OE R65 1 1nOE nBCR_WR 48 1CLK 100K VSS_1 4 DC3P3V 24 10 2nOE VSS_2 25 15 2CLK VSS_3 RADIO_PWR_ON {11} VSS_4 21 7 28 VDD_1 VSS_5 R66 18 VDD_2 VSS_6 34 31 VDD_3 VSS_7 39 100K 42 VDD_4 VSS_8 45
RADIO_WAKE {11} C27 C28 0.1UF 0.1UF U10 74LVCH16374A DC3P3V CPLD nRED_LED B XCR3032XL-10VQ44C B Xilinx CPLD D1 {2} SA_SDCLK_2 42 A0_CLK B0 35 CF_nBUS_ON R67 {15} nNEP_FLASH_CS 43 A1 B1 34 nXCV_ADD_OE {7,13} 2 1 44 33 {7} XCV_DATA_DIR A2 B2 SA_nCS_5 {2,15} 1.5K 1 32 RED DC3P3V {10,11} CPLD1_TDI A3_TDI B3_TDO CPLD1_TDO {11,13} 2 31 nGREEN_LED {3,15} MBGNT_CF_IRQ nBCR_OE A4 B4 SA_nCS_4 {2,15} 3 A5 B5 30 SA_nCS_3 {2,15} nBCR_WR 5 28 D2 A6 B6 SA_nCS_2 {2} R68 6 27 2 1 {7} nVX_CF_OE A7 B7 SA_nCS_1 {2} 7 26 {3,10,11,13} JTAG_TMS A8_TMS B8_TCK JTAG_TCK {3,10,11,13} GRN 1.5K 8 25 {10,15} nNEP_REG_CS A9 B9 SA_nCS_0 {2,15} {2,4,5,7,10} SA_nWE 10 A10 B10 23 SA_A25 {2,7} 11 22 {7} nXCV_DATA_OE A11 B11 VX_nOE {7,15} SPKR_OFF {8} 12 21 DC3P3V {7} XCV_ADD_DIR A12 B12 13 20 {10,15} CF_IRQ_LVL2OE A13 B13 SA_nPCE_2 {2,15} 14 19 DC3P3V {3,11,13,15} nRESET_OUT A14 B14 SA_nPCE_1 {2,15} R69 {5} nFLASH_BOOT_CS 15 A15 B15 18 SA_RD_nWR{2,15} 100K VDD_1 9 VDD_2 17 VDD_3 29 37 41 {15} SWAP_FLASH IN0 VDD_4 R70 39 {2,4,7} SA_nSDRAS IN1 MMC_PWR_ON{13} A 38 4 A {2} SA_nSDCS_2 IN2 VSS_1 0 C29 C30 C31 C32
40 16 0.1UF 0.1UF 0.1UF 0.1UF {2,4,5,7} SA_nSDCAS IN3 VSS_2 VSS_3 24 VSS_4 36 PXA250 Processor Reference Design
XCR3032XL Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 6 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 7 DC3P3V
NOTE: NOTE: U11 Transceivers DIR H = A -> B U12 DIR L = A <- B nXCV_ADD_OE is Low when
R230 100K Neponset or Graphics 74LVCH16245A 74LVCH16245A boards are present. D XCVR XCVR D 1 1 1DIR XCV_ADD_DIR{6} {6} XCV_DATA_DIR 1DIR 48 48 1nOE nXCV_ADD_OE{6,13} {6} nXCV_DATA_OE 1nOE 2 47 47 2 {2,4,5} SA_A18 1B1 1A1 VX_A18 {15} {2,4,5,6} SA_D0 1A1 1B1 VX_D0 {10,15} 3 46 46 3 {2,4,5} SA_A17 1B2 1A2 VX_A17 {15} {2,4,5,6} SA_D1 1A2 1B2 VX_D1 {10,15} 5 44 44 5 {2,4,5} SA_A16 1B3 1A3 VX_A16 {15} {2,4,5,6} SA_D2 1A3 1B3 VX_D2 {10,15} 6 43 43 6 {2,4,5} SA_A15 1B4 1A4 VX_A15 {15} {2,4,5,6} SA_D3 1A4 1B4 VX_D3 {10,15} 8 41 41 8 {2,4,5} SA_A14 1B5 1A5 VX_A14 {15} {2,4,5,6} SA_D4 1A5 1B5 VX_D4 {10,15} 9 40 40 9 {2,4,5} SA_A13 1B6 1A6 VX_A13 {15} {2,4,5,6} SA_D5 1A6 1B6 VX_D5 {10,15} 11 38 38 11 {2,4,5} SA_A12 1B7 1A7 VX_A12 {15} {2,4,5,6} SA_D6 1A7 1B7 VX_D6 {10,15} 12 37 37 12 {2,4,5} SA_A11 1B8 1A8 VX_A11 {15} {2,4,5,6} SA_D7 1A8 1B8 VX_D7 {10,15}
{2,5} SA_nOE 13 2B1 2A1 36 VX_nOE {6,15} {2,4,5,6} SA_D8 36 2A1 2B1 13 VX_D8 {10,15} 14 35 35 14 {2,4,5} SA_A10 2B2 2A2 VX_A10 {10,15} {2,4,5,6} SA_D9 2A2 2B2 VX_D9 {10,15} 16 33 33 16 {2,5} SA_A9 2B3 2A3 VX_A9 {10,15} {2,4,5,6} SA_D10 2A3 2B3 VX_D10 {10,15} 17 32 32 17 {2,5} SA_A8 2B4 2A4 VX_A8 {10,15} {2,4,5,6} SA_D11 2A4 2B4 VX_D11 {10,15} 19 30 30 19 {2,5} SA_A7 2B5 2A5 VX_A7 {10,15} {2,4,5,6} SA_D12 2A5 2B5 VX_D12 {10,15} {2,5} SA_A6 20 2B6 2A6 29 VX_A6 {10,15} {2,4,5,6} SA_D13 29 2A6 2B6 20 VX_D13 {10,15} 22 27 27 22 {2,5} SA_A5 2B7 2A7 VX_A5 {10,15} {2,4,5,6} SA_D14 2A7 2B7 VX_D14 {10,15} 23 26 26 23 {2,5} SA_A4 2B8 2A8 VX_A4 {10,15} {2,4,5,6} SA_D15 2A8 2B8 VX_D15 {10,15}
C 4 VSS_1 2DIR 24 24 2DIR VSS_1 4 C 10 VSS_2 VSS_2 10 15 VSS_3 2nOE 25 nVX_CF_OE{6} 25 2nOE VSS_3 15 21 21 VSS_4 DC3P3V DC3P3V VSS_4 28 VSS_5 VDD_1 7 7 VDD_1 VSS_5 28 34 VSS_6 VDD_2 18 18 VDD_2 VSS_6 34 39 VSS_7 VDD_3 31 31 VDD_3 VSS_7 39 45 VSS_8 VDD_4 42 42 VDD_4 VSS_8 45
74LVCH16245APF 74LVCH16245APF C33 C34 C35 C36 0.1UF 0.1UF 0.1UF 0.1UF U13 U14
74LVCH16245A 74LVCH16245A XCVR XCVR 1DIR 1 1 1DIR 48 48 1nOE {6} nXCV_DATA_OE 1nOE 2 47 47 2 {2,4,5,6,10} SA_nWE 1B1 1A1 VX_nWE {15} {2,4,5} SA_D16 1A1 1B1 VX_D16 {15} 3 46 46 3 {2,4} SA_DQM_0 1B2 1A2 VX_DQM_0 {15} {2,4,5} SA_D17 1A2 1B2 VX_D17 {15} B 5 44 44 5 B {2,4} SA_DQM_1 1B3 1A3 VX_DQM_1 {15} {2,4,5} SA_D18 1A3 1B3 VX_D18 {15} 6 43 43 6 {2,4} SA_DQM_2 1B4 1A4 VX_DQM_2 {15} {2,4,5} SA_D19 1A4 1B4 VX_D19 {15} {2,4,6} SA_nSDRAS 8 1B5 1A5 41 VX_nSDRAS{15} {2,4,5} SA_D20 41 1A5 1B5 8 VX_D20 {15} {2,4} SA_DQM_3 9 1B6 1A6 40 VX_DQM_3 {15} {2,4,5} SA_D21 40 1A6 1B6 9 VX_D21 {15} 11 38 38 11 {2,4,5,6} SA_nSDCAS 1B7 1A7 VX_nSDCAS{15} {2,4,5} SA_D22 1A7 1B7 VX_D22 {15} 12 37 37 12 {2,4} SA_nSDCS_0 1B8 1A8 VX_nSDCS_0{15} {2,4,5} SA_D23 1A8 1B8 VX_D23 {15}
{2,4} SA_SDCLK_1 13 2B1 2A1 36 VX_SDCLK_1{15} {2,4,5} SA_D24 36 2A1 2B1 13 VX_D24 {15} {2,6} SA_A25 14 2B2 2A2 35 VX_A25 {15} {2,4,5} SA_D25 35 2A2 2B2 14 VX_D25 {15} {2,4,5} SA_A24 16 2B3 2A3 33 VX_A24 {15} {2,4,5} SA_D26 33 2A3 2B3 16 VX_D26 {15} {2,4,5} SA_A23 17 2B4 2A4 32 VX_A23 {15} {2,4,5} SA_D27 32 2A4 2B4 17 VX_D27 {15} {2,4,5} SA_A22 19 2B5 2A5 30 VX_A22 {15} {2,4,5} SA_D28 30 2A5 2B5 19 VX_D28 {15} {2,4,5} SA_A21 20 2B6 2A6 29 VX_A21 {15} {2,4,5} SA_D29 29 2A6 2B6 20 VX_D29 {15} {2,4,5} SA_A20 22 2B7 2A7 27 VX_A20 {15} {2,4,5} SA_D30 27 2A7 2B7 22 VX_D30 {15} {2,4,5} SA_A19 23 2B8 2A8 26 VX_A19 {15} {2,4,5} SA_D31 26 2A8 2B8 23 VX_D31 {15} 4 24 24 4 VSS_1 2DIR {6} XCV_DATA_DIR 2DIR VSS_1 10 VSS_2 VSS_2 10 15 25 25 15 VSS_3 2nOE DC3P3V DC3P3V 2nOE VSS_3 21 VSS_4 VSS_4 21 28 VSS_5 VDD_1 7 7 VDD_1 VSS_5 28 34 VSS_6 VDD_2 18 18 VDD_2 VSS_6 34 39 VSS_7 VDD_3 31 31 VDD_3 VSS_7 39 45 42 42 45 A VSS_8 VDD_4 VDD_4 VSS_8 A
74LVCH16245APF 74LVCH16245APF C37 C38 C39 C40 0.1UF 0.1UF 0.1UF 0.1UF PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 7 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 8 Y3 XTAL_IN 2 1 XTAL_OUT U15 Audio CODEC
24.576MHZ + 1 UCB1400 C41 C42 10UF Modem / Audio 0.1UF C43 C44 R72 33PF 22pF R71 47.5 XTAL_IN 2 12 XTL_IN ADCSYNC 2 0 DNI XTAL_OUT 3 34 D XTL_OUT VREFDRV D 27 VREF {13,15} SYSCLK 8 29 DNI {2} SA_SDATA_IN SDATA_IN IRQOUT AC97_IRQ {3} R73 R74 6 37 Audio Amp {2} SA_BITCLK BIT_CLK GPIO_0 AC97_GPIO_0{11} R75 0 47.5 5 39 {2} SA_SDATA_OUT SDATA_OUT GPIO_1 AC97_GPIO_1{11} R76 0 R77 10 40 {2} SA_SYNC SYNC GPIO_2 AC97_GPIO_2{11} 20K R78 0 R79 11 41 {2} SA_nAC97_RESET RESET GPIO_3 AC97_GPIO_3{11} C46 0 R80 LINE_OUT_L{11} 20K 43 + C141 GPIO_4 AC97_GPIO_4{11} L_OUT_A{9} 21 0 R14 {9} MICIN MICP R82 U16 100UF 2 + 1 44 {10} CF_AUD R83 GPIO_5 LINE_OUT_R{11} 22 10K {9,11} MICGND MICGND 100K 4.7UF 45 R84 C50 {11} RADIO_SPKRP 0 GPIO_6 LM4881
J1 C45 + 100K R81 Dual Audio Pwr R_OUT {9} 2 1 23 46 R86 Amp w/shutdwn 2 LINE_IN_L GPIO_7 100UF
100K R87 20K + C131 2 1 24 47 0.1UF 8 7 LINE_IN_R GPIO_8 C47 IN_A OUT_A 4.7UF 100K R85 1 J2 48 R124 4 5 C GPIO_9 IN_B OUT_B C R88 100K 20K R89 20 0.1UF 1 6 AMP5V {14} TSPY TSPY BYPASS VDD R90 0 1 18 35 3 2 {14} TSMX TSMX LINE_OUT_L {6} SPKR_OFF SHDN GND 0 R91 19 36 R92 {14} TSMY TSMY LINE_OUT_R DC_CORE + R93 0 AUDIO3P3V{9} 17 LM4881MM 1UF {14} TSPX TSPX C51 1 0 R94 DNI AD_3 13 VBATT {3,10,11,12,13,14} C52 0 R96 0.1UF 14 C54 C56 C53 C55 AD_2 0.01UF 0.01UF 0.01UF 0.01UF 0 15 XFILT {9} AD_1 DC5P5V U17 {9} AUDIO3P3V 16 YFILT {9} AD_0 MIC5207-3.3BM5 1 DVDD1 9 4 3.3V LDO REG DVDD2 DVSS1 7 1 5 DVSS2 VIN180ma VOUT AUDIO3P3V{9} 25 AVDD1 32 26 2 AVDD2 AVSS1 GND 1 C57 + 0.1UF 38 AVDD3 AVSS2 33 42 3 4 C64 C59 4.7UF AVSS3 0.01UF 0.01UF EN BYP B C61 B
LE33 2
R99 C62
28 0.1UF VADCP C63 0 10 C58 270PF 0.1UF R282
R100 U18 C66 0.1UF 1 MIC5207-4.0BM5 4.0V LDO REG 1 + AMP5V 1 VIN180ma VOUT 5 C67
R101 0.1UF 30
4.7UF TEST C68 31 2 VADCN GND 2
1 1 3 4 + {6} AUDIO_PWR_ON EN BYP 1 4.7UF + LE40 C69 C70 0.1UF 0 0 2 R102 R103 4.7UF C71 C72 0.1UF C73 2 R104 270PF A A 1
1 + C74 0.1UF 4.7UF C75 PXA250 Processor Reference Design 2
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 8 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Stereo Headphone Jack Pg. 9 DC3P3V J3 R105 MIC_PWR C76 IrDA Transceiver {8} AUDIO3P3V U19 10 Headset Jack 1 0.1UF VCC AGND 2 C77
1.5K J4 0.1UF 1 3 3 D R106 R_OUT {8} FIR_SEL IRDA_FSEL{6} D MD_0 4 IRDA_MD0 {6} 11 GND MD_1 5 IRDA_MD1 {6} 6 Microphone L_OUT_B NC 2 GND 7 RXD 8 IR_RXD {2} 1 9 IR_TXD {2} GND TXD DC3P3V LEDA 10 4 Speaker 1 SHA L_OUT_B STEREO HDSL-3600 # 007 SHB 5 R107 J5 JACK 2 TIP 10
3.5mm C78
3 0.1UF RING L_OUT_A {8} 2 4 R108 1 MICGND {8,11} HEADSET J6 10 JACK R109 2.5mm 2 0 10 R110 C79 R111 USB_5V 1 + 2 MICIN {8} 10 C R112 C 4.7UF {2} SA_UDCN R149 0 RADIO_MICP{11} Mini USB Jack 0 DC3P3V DNI R113 475K 1.5K R114
1 J7
2 1 R115 3 {2} SA_UDCP 0 4 5
12-54819-78 DNI {8} AUDIO3P3V Dual Axis Acelerometer R116 475K
B B U20
ADXL202E C80
0.1UF Dual Axis Accelerometer DC3P3V DC3P3V 8 VDD XCAP 7
1 ST YCAP 6
2 T2 XOUT 5 2 3 4 10K R118 R119 100K C81 C82 COM YOUT 0.01UF 0.01UF U21
R117 237K MAX6348 LCC8 2 RESET USB_WAKE{3,15} 1 R123 USB_5V R121 XFILT {8} 3 VIN 100K 1K 1 R120 GND YFILT {8} C84 100K 0.1UF A + + MAX6348XR40-T A 1uF C3 1uF C4
PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 9 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation J8 U23 Pg. 10 DC5P5V CF_TYPE_II Momentary Switches MIC5219BM5 Compact Flash Type II Socket 50 GND2 ADJ LDO REG 25 nCD2 1 5 DC3P3V S2 {13} CF_nCD2 VIN500ma VOUT 49 D10 {7,15} VX_D10 nIOIS16 24 2 1 S 2 GPIO_0 {3,15}
{6} CF_nIOIS16 GND 953 48 D09 4 3 {7,15} VX_D9 R126 23 D02 3 4 D {7,15} VX_D2 {13} CF_PWR EN ADJ D 47 D08 {7,15} VX_D8 R127 100K 22 D01 LGAA R129 {7,15} VX_D1 S3 46 BVD1 1.5K DC3P3V {3,15} SA1111_IRQ_CF_BVD1 R128 21 D00 U24 10K {7,15} VX_D0 R130 BVD2 S {3,15} GFX_IRQ_CF_BVD2 45 1 2 GPIO_32 {3} 20 A00 MIC5219-3.3BM5 4 3 10K {6,15} VX_A0 44 nREG 3.3V LDO REG {6} CF_nPREG 19 A01 1 5 CF_VDD {6,15} VX_A1 {3,8,11,12,13,14} VBATT VIN500ma VOUT R131 100K 43 nINPACK CF_I2C_SDA 18 A02 2 DC3P3V S4 {6,15} VX_A2 GND 1 42 nWAIT + {6} CF_nPWAIT 17 A03 3 4 1 S 2 R132 {6,15} VX_A3 EN BYP GPIO_17 {3} RESET C85
41 4.7UF 4 3 {6,15} CF_GFX_RESET K 16 A04 LG33 2 1K {7,15} VX_A4 40 nVS2 CF_I2C_SCL R133 100 15 A05 {7,15} VX_A5 39 nCSE DC3P3V S5 {6,15} nNEP_REG_CS 14 A06 {7,15} VX_A6 R15 38 VCC2 1 S 2 CF_VDD GPIO_22 {2,11} 13 VCC1 J9 4 3 0 37 IREQ Base Station Connector K {6,15} CF_IRQ_LVL2OE 12 A07 {7,15} VX_A7 R134 100 36 nWE {6} CF_nPWE C 11 A08 DC3P3V C {7,15} VX_A8 nIOWR {6} CF_nPIOW 35 10 A09 {7,15} VX_A9 DC3P3V 34 nIORD 20 Three Position Switch {6} CF_nPIOR 9 nOE 19 {6} CF_nPOE 33 nVS1 18 {8} CF_AUD A10 {7,15} VX_A10 8 17 R135 32 nCE2 R138 {13} CF_nCD1 {6} CF_nPCE_2 {2,14} GPIO_21 7 nCE1 100K {6} CF_nPCE_1 100K 31 D15 16 15 RS_RI {7,15} VX_D15 6 D07 R140 R136 {7,15} VX_D7 D14 RS_DCD 30 14 13 SA_nWE {2,4,5,6,7}
{13} CF_nCD2 {7,15} VX_D14 0 5 D06 R16 100K {7,15} VX_D6 1.5K 29 D13 12 11 DC3P3V {7,15} VX_D13 {3,6,11,13} JTAG_TCK 4 D05 {7,15} VX_D5 R139 28 D12 RS_TX 10 9 RS_RX {6} CF_nIOIS16 {7,15} VX_D12 3 D04 S6 100K {7,15} VX_D4 4 5 6 27 D11 RS_RTS 8 7
{7,15} VX_D11 0 2 D03 CCW {7,15} VX_D3 R122 R142 R141 26 nCD1 RS_CTS 6 5 {6} CF_nPWAIT {13} CF_nCD1 nRESET_IN {3,11,15} 1 GND1 100K 0 RS_DTR 4 3 DNI PUSH
RS_DSR 2 1 B JTAG_TMS {3,6,11,13} B CW 22 CPLD1_TDI{6,11} U25 1 2 3 R144 C86 21 SA_TDO {3,11} C87 {12,15} IN_PWR
75 0 MAX3244ECAI R17 0.1UF 0.1UF RS-232 XCVR 28 27 C88 0 C1+ V+ R153 24 3 C89 C1- V- DC3P3V 0.1UF {2,14} GPIO_20 1 C2+ 2 0.1UF C2- {2,14} GPIO_19 14 9 RS_TX {2,15} SA_FF_TXD T1 IN T1OUT 13 10 RS_RTS U26 DC3P3V {2} SA_FF_RTS T2 IN T2OUT 12 11 RS_DTR {2} SA_FF_DTR T3 IN T3OUT R145 100K R146 100K 19 4 RS_RX MAX4542 {2,15} SA_FF_RXD R1OUT R1 IN 18 5 RS_DCD 2 {2} SA_FF_DCD R2OUT R2 IN V+ 17 6 RS_DSR {2} SA_FF_DSR R3OUT R3 IN RS_RI {2} SA_FF_RI 16 R4OUT R4 IN 7 {2,12,15} SA_I2C_SCL 8 COM_1 15 8 RS_CTS {2} SA_FF_CTS R5OUT R5 IN A 7 1 A IN_1 NC_1 CF_I2C_SCL
20 R2OUTB INVLD 21 RS232_VALID {3} {6} RS232_ON 22 FORCEOFF VCC 26 {2,12,15} SA_I2C_SDA 4 COM_2 NC_2 5 CF_I2C_SDA 23 FORCEON GND 25 3 PXA250 Processor Reference Design
C90 {3} SA_I2C_ENAB IN_2 0.1UF 6 GND Size Rev AAAF B 2.07
Date: Tuesday, February 05, 2002 Sheet 10 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 11
DC3P3V SD Socket
J10 R147 10K D D
Bottom Mount SA_MMCMD {2} 9 LAYOUT NOTE: Place close to DAT2 Battery Header and Codec UCB 1 CD_DAT3 MMC_CS0 {2} 1400 2 CMD C91
3 0.1UF Radio VSS1 C132 4 MMC_PWR Baseband VDD {8} LINE_OUT_L 5 DNI IF MMC 0.1UF J20 Connector CLK SA_MMCCLK {2} C140 R225 6 1 2 VSS2 {8} LINE_OUT_R 0 7 DC3P3V 0.1UF 3 4 DAT0 SA_MMDAT{2} RADIO_DSR {2} 8 5 6 CHECK !! SA_BT_CTS {2} DAT1 DC3P3V DNI {2} RADIO_DTR 0 7 8
R226 IF
WP COMM CD R150 {2} SA_BT_RTS SA_BT_RXD {2,15} SD DNI 9 10 C IF R227 100K {2,15} SA_BT_TXD RADIO_RI {2} C 10 11 12 SD 47.5K {6} RADIO_PWR_ON 11 12 RADIO_RXD_C{2} nMMC_DETECT{2,13} DC3P3V 13 14 nRESET_IN {3,10,15} DC3P3V {6} RADIO_WAKE CARD Selection Resistors RADIO_SPKRN {2} RADIO_DCD 15 16 and Values DNI 17 18 RES SD MMC IF {8,9} MICGND RADIO_SPKRP {8}
R226 DNI 0 MMC R228 100K 19 20 MMC_WP {2} R227 DNI 100K {9} RADIO_MICP R225 0 DNI 21 22 {3,6,13,15} nRESET_OUT R228 100K DNI DC5P5V 23 24 {3,8,10,12,13,14} VBATT AC97_GPIO_0{8} R229 100K DC5P5V 25 26 AC97_GPIO_1{8} U27 {3,8,10,12,13,14} VBATT R198 27 28 AC97_GPIO_2{8} MIC5207-3.3BM5 0 3.3V LDO REG 29 30 {8} AC97_GPIO_4 AC97_GPIO_3{8} 1 5 MMC_PWR VIN180ma VOUT 2 GND 1 B + B 3 4 {13} MMC_ON EN BYP C92 4.7UF
LE33 2
DC3P3V DC3P3V JTAG ICE Connector
DNI J19 R236 {2,10} GPIO_22 0
10K R221 R219 1 2 R270 {3,6,10,13} JTAG_TMS DVAL_1 {15} 0 R233 0 3 4 {3} JTAG_nTRST {2,10} GPIO_21 0 R218 5 6 {6,10} CPLD1_TDI {6,10} CPLD1_TDI DVAL_0 {15} R234 0 7 8 DNI {3,6,10,13} JTAG_TMS {2,10} GPIO_19 R232 R222 100K 0 9 10 {3,6,10,13} JTAG_TCK {3,6,10,13} JTAG_TCK DREQ_1 {15} R235 0 11 12 {2,10} GPIO_20 0 R231 R223 13 14 A {3,10} SA_TDO {3,10} SA_TDO DREQ_0 {15} A R224 0 75 15 16 {3,10,15} nRESET_IN 0 17 18
19 20 PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 11 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation DC5P5V Pg. 12 5.5 Volt Supply D3 Processor Core Voltage Supply
1 U28 L1 11-TM104-NP
4.7uH K LTC1878 R154 357 VBATT {3,8,10,11,13,14} + Battery Connector 8 LPF 1 D {3,13} SA_PWR_EN RUN R220 100K D 2 C94 C95 100UF and Jumper Post + 0.1UF U29 7
{3,8,10,11,13,14} VBATT SYNC-MODE C97 K J18 2 22UF DC_CORE Ith DC3P3V 1 R155 100 {3,8,10,11,13,14} VBATT + LT1308A 6 VIN 6 5 BATTERY 2 3
C96 VIN SW FB L2 22UF C98
K J17
4 2 220pF 4 5 1 2 R157 150K GND FB GND SW R156 100 1 LTNX 10uH 1K R159 1 3 8 2 BATT_IN_POS + {3,13} SA_PWR_EN SHDN LBO nVBATT_LOW_IRQ{3,15} R166 3 BATT_IN_NEG LTC1878EMS8 C99 22pF C100 0 1
R158 100UF
4 0.1UF SA_I2C_SDA {2,10,15} R160 196K C101 1 7 5 2 VC LBI SA_I2C_SCL {2,10,15} D4
6 RED R161 100K
47.5K 7 SA_SMB_MODE 2 1308A 8 nBATT_PRESENT R162 R163 9 BATT_TEMP {3,8,10,11,13} VBATT 100PF 10 C102 976K 61.9K DC3P3V U30
53261-1090 LTC1663 R165 887K R164 487K C 4 VCC C VOUT 3 1 {2,10,15} SA_I2C_SDA SDA GND 2 5 {2,10,15} SA_I2C_SCL SCL
LTEP
LTC1663CS5 Battery Charger
IN_PWR{10,15}
D10 3.3 Volt Supply DC3P3V
DC5P5V 12 U31 B B 1K 1K MIC5207-BM5 0.1 + R210 R209 R275 ADJ LDO REG 1uF C144 1 1 8 1 180ma 5 D7 U43 VIN VOUT GRN D8 3 2 1 K
2 RED Vcc GND PLL Voltage Supply 2 2 3 9 R167 100 nCHRG SENSE 3 4 DC_CORE EN BYP R211 10 Q1 {2,3} nCHRGR_PRESENT nACPR LEAA DC3P3V 7 4 0 DRV K U42 4 TIMER R168 160 DC3P3V MIC5207-BM5 0 6 1 BATTERY R206 PROG BAT ADJ LDO REG 5 6 7 8 1 180ma 5 DC_PLL{3} U32 VIN VOUT GND SEL 20K
2 0.1UF C142 C143 R276 1 4.7uF
0 GND R95 DNI LTC1732 {3,8,10,11,13,14} VBATT R201 357K ADP3335 3 4 + 5 2 C137 {3,13} SA_PWR_EN EN BYP 0.33F 1 2 LEAA 33uF
7 5 C138 IN_1 NR + R274 K 8 1 22UF C103 A IN_2 OUT_1 PLL_SENSE{3} A R203 R169 200 4.99K C139
6 2 470PF SHUTDOWN OUT_2 0.1UF C104
K 4 3 PXA250 Processor Reference Design GND OUT_3 DNI DNI R170 100 LFE Size Rev B 2.07 ADP3335ARM-3.3 Date: Tuesday, February 05, 2002 Sheet 12 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation LCD CPLD Pg. 13 D5 U33 2 R216 DCNEG14V {14} U40 1 XCR3128XL-10VQ100C 3 Xilinx CPLD 100K 2 40 MAX633ACSA D6
{14} LCD_G4 A0 E0_CLK1 2 3
1 41 Adj Step-up C121 + {14} LCD_G5 A2 E2 CF_nCD1 {10} 22UF 100 42 Sw Reg D {14} LCD_SPS A4 E4 nNEP_PRESENT{4,15} D 99 44 LCD_DC5V 1 8 ZENER_3P3V {14} LCD_CLS A5 E5 CF_PWR_ON{6} LBI COMP 98 45 1 {14} LCD_LP A7 E7 CF_PWR {10} DC_15V {14,15} DCNEG11P7V{14} 97 46 2 7 {14} LCD_SPL A8 E8 GPIO_11 {3} LBO VFB 96 47 {14} LCD_G0 A10 E10 SYSCLK {8,15} 94 48 3 6 {14} LCD_G1 A12 E12 nXCV_ADD_OE{6,7} GND CP 93 49 L3 {14} LCD_G2 A13 E13 92 50 4 5 A15_CLK3 E15 MBREQ_CF_DETECT{3,15} LX VOUT {14} LCD_G3 INDUCTOR 14 52 2
{14} LCD_SPR B0 F0 nGFX_PRESENT{4,15} 470UH +
13 53 + C129 C126 + C127 R202
L_DD_0 {3} 22UF 9.76K REV {4} LCD_TYPE B2 F2 MAX633ACSA 0.1UF 12 54 0.1UF B4 F4 L_DD_1 {3} C128 4.7UF 1 22UF C120
10 55 0.1UF {14} LCD_R2 B5 F5 L_DD_2 {3} C122 9 56 {14} LCD_R3 B7 F7 L_DD_3 {3} 8 57 {14} LCD_R4 B8 F8 L_DD_4 {3} {14} LCD_R5 7 B10 F10 58 L_DD_5 {3} 6 60 {14} LCD_LBR B12 F12 L_DD_6 {3} 5 61 {14} LCD_PS B13 F13 L_DD_7 {3} 4 62 {6} CPLD1_TDO B15_TDI F15_TCK JTAG_TCK {3,6,10,11,14}
{6} MMC_PWR_ON 25 C0 G0 63 L_DD_8 {3,4} 24 64 {2,11} nMMC_DETECT C2 G2 L_DD_9 {3,4} 23 65 {11} MMC_ON C4 G4 L_DD_10 {3,4} 22 67 {14} SHARP_LCD_PWR_ON C5 G5 L_DD_11 {3,4} 21 68 C {14} LCD_R0 C7 G7 L_DD_12 {3,4} C {14} LCD_R1 20 C8 G8 69 L_DD_13 {3,4} 19 70 {14} LCD_B1 C10 G10 L_DD_14 {3,4} 17 71 {14} LCD_B0 C12 G12 L_DD_15 {3,4} 16 72 {14} LCD_CLK C13 G13 L_LCLK {3} 15 73 {3,6,10,11,14} JTAG_TMS C15_TMS G15_TDO CPLD2_TDO{3} R213 37 D0_CLK2 H0 75 L_FCLK {3} 36 76 100K {3} nVDD_FAULT D2 H2 L_BIAS {3} 35 77 LCD_DC5V {15} VDD_FAULT D4 H4 U44 33 D5 H5 78 LCD_PWR_ON{6,14} 32 79 {14} LCD_ENAB D7 H7 SA_PWR_EN{3,12} Note: On 31 80 {14} LCD_NCLK D8 H8 nRESET_OUT{3,6,11,15} R214 30 81 A1 HBL-0204 {14} LCD_B5 D10 H10 FLASH_nRP{5} VCC board Back 29 83 A2 H CN2-1 100K {14} LCD_B2 D12 H12 LCD_MODE{14} {3,8,10,11,12,14} VBATT VIN 28 84 A3 Light Inverter {14} LCD_B3 D13 H13 R207 ON_OFF L CN2-2 {14} LCD_B4 27 D15 H15 85 LCD_UBL {14} {2} SA_PWM_0 A4 GND for Toshiba 0 87 DNI PIEZOELECTRIC INVERTER {3} L_PCLK IN0_CLK0 Display 89
R171 IN1 0 88 IN2 R208 90 100K {10} CF_nCD2 IN3 DC3P3V 3 VDD_1 VSS_1 11 B 18 VDD_2 VSS_2 26 B 34 VDD_3 VSS_3 38 39 43 VDD_4 VSS_4 DNI 0.1UF 0.1UF 51 59 Back Light C105 C106 VDD_5 VSS_5 R151 66 VDD_6 VSS_6 74 82 86 VDD_7 VSS_7 {2} SA_PWM_0 Header for 91 VDD_8 VSS_8 95 4.99K 0.1UF 0.1UF C107 C108 Off Board Sharp Back
XCR3128XL-10VQ100C C93 0.1UF
LCD_DC5V R172 LCD_DC5V Light Inverter
{14} VCOM U35 U34 R173 10 J11 3 DC5P5V {14} PVEE SN74HCT04D SN74HCT04D 10 Hex Inv 1 R175 C109 1 14 2 Hex Inv 5K 1A VDD {6} LIGHT_PWR_ON
1 14 2 + 2 3 1A VDD LCD_DC4V {14} 1Y R152 2 13 REV 4 1Y R174 10K 6A 13 REV 15UF 3 12 nREV 5 6A 1 2A 6Y 0 {3,8,10,11,12,14} VBATT 3 12 + 4 2A 6Y AB_SW {14} 2Y 4 11 R176
2Y 27.4K 5A A 1 Layout Note: A
11 4.7UF C110 10 5A 5Y 10 2 5 VBATT ADD WIDE 53261-0590 5Y 3A 5 6 9 ETCH 3A 3Y 4A 6 9 8 3Y 4A 4Y 8 7 4Y V0 {14} GND 7 PXA250 Processor Reference Design R177 GND 15K C111 SN74HCT04PWR
SN74HCT04PWR + {14} DCNEG14V Size Rev 15UF B 2.07
Date: Tuesday, February 05, 2002 Sheet 13 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 14 LCD Power U41 DC5P5V U37 LCD_DC5V {13} LCD_DC4V DC5P5V MIC5207-BM5 MIC5207-5.0BM5 ADJ LDO REG 5.0V LDO REG 1 5 1 5 VIN180ma VOUT VIN180ma VOUT 1 2 K 2 + + GND GND R179 R180 R181 R199 100 R178 R182 22.6K 34.8K 9.76K 17.4K 42.2K 100UF 4.7UF C115 3 4 3 4 0.1UF D {6,13} LCD_PWR_ON EN BYP {6,13} LCD_PWR_ON EN BYP C114 C116 D L_DC3P3V L_DC3P1V L_DC2P6V L_DC3P6V L_DC2P3V 2 LEAA K LE50 R204 150
U36 R183 R184 R185 R187 R186 30.1K 30.1K 6.19K 13.7K 40.2K MIC5207-3.3BM5 LCD_DC5V U38 3.3V LDO REG L_DC2P1V L_DC1P9V L_DC2P35V L_DC2P0V L_DC1P75V MIC5207-4.0BM5 1 180ma 5 LCD_DC3P3V {3,8,10,11,12,13} VBATT VIN VOUT 4.0V LDO REG 2 1 5 1 180ma LCD_DC4V {13} GND + VIN VOUT R188 R189 R190 R191 R192 23.7K 34.8K 18.7K 27.4K 7.32K
3 4 0.1UF 2 C113 1 EN BYP 4.7UF GND + L_DC1P15V L_DC0P5V L_DC1P6V L_DC0P9V L_DC1P45V C112 LE33 2 3 4 0.1UF {13} SHARP_LCD_PWR_ON EN BYP C117 4.7UF C118
LE40 2 R195 R193 R194 R196 R197 40.2K 28.7K 12.4K 22.6K 36.5K Sharp LCD Connector J13
C C
1 (50) AGND (49) V9 2 V9 3 LCD Grey Scale Touch Screen (48) V8 V8 (47) V7 4 V7 5 Level Buffer (46) V6 V6 Connector U39 (45) V5 6 V5 (44) V4 7 V4 8 LCD_DC5V J21 (43) V3 V3 (42) V2 9 V2 LMC6009 1 10 TSPY {8} (41) V1 V1 9 Ch Buf Amp 2 TSMX {8} (40) V0 11 V0 {13} for TFT-LCD 3 12 4 TSMY {8} (39) VSHA L_DC3P3V A1A 4 13 5 42 TSPX {8} (38) SPR LCD_SPR {13} L_DC0P5V A1B A1 OUT V1 14 6 (37) LBR LCD_LBR {13} L_DC3P1V A2A 15 7 41 (36) DCLK LCD_CLK {13} L_DC0P9V A2B A2 OUT V2 487951-4 16 8 (35) LP LCD_LP {13} L_DC2P6V A3A 17 9 40 (34) PS LCD_PS {13} L_DC1P45V A3B A3 OUT V3 18 10 (33) DGND L_DC2P35V A4A Toshiba LCD Connector 19 11 39 (32) VSHD LCD_DC3P3V L_DC1P75V A4B A4 OUT V4 J14 20 12 (31) B5 LCD_B5 {13} L_DC2P1V A5A 21 13 36 (30) B4 LCD_B4 {13} L_DC2P0V A5B A5 OUT V5 B 22 14 B (29) B3 LCD_B3 {13} L_DC1P9V A6A 1 23 15 35 (28) B2 LCD_B2 {13} L_DC2P3V A6B A6 OUT V6 2 24 16 {13} LCD_NCLK (27) B1 LCD_B1 {13} L_DC1P6V A7A 3 25 17 34 (26) B0 LCD_B0 {13} L_DC2P6V A7B A7 OUT V7 4 26 18 {13} LCD_R0 (25) G5 LCD_G5 {13} L_DC1P15V A8A 5 27 19 33 LCD_R1 {13} (24) G4 LCD_G4 {13} L_DC3P3V A8B A8 OUT V8 6 28 20 {13} LCD_R2 (23) G3 LCD_G3 {13} L_DC0P5V A9A 7 29 21 32 LCD_R3 {13} (22) G2 LCD_G2 {13} L_DC3P6V A9B A9 OUT V9 8 30 {13} LCD_R4 (21) G1 LCD_G1 {13} 9 31 29 LCD_R5 {13} (20) G0 LCD_G0 {13} {13} AB_SW A_B_SWITCH 10 (19) R5 32 LCD_R5 {13} 11 33 1 26 LCD_G0 {13} (18) R4 LCD_R4 {13} NC1 NC8 12 34 2 27 {13} LCD_G1 (17) R3 LCD_R3 {13} NC2 NC9 13 35 3 28 LCD_G2 {13} (16) R2 LCD_R2 {13} NC3 NC10 14 36 22 45 {13} LCD_G3 (15) R1 LCD_R1 {13} NC4 NC11 15 37 23 46 LCD_G4 {13} (14) R0 LCD_R0 {13} NC5 NC12 16 38 24 47 {13} LCD_G5 (13) SPL LCD_SPL {13} NC6 NC13 17 39 25 48 (12) VCOM1 VCOM {13} NC7 NC14 18 40 {13} LCD_B0 (11) VCOM2 VCOM {13} 19 41 44 43 LCD_B1 {13} (10) VEE2 PVEE {13} {13} LCD_DC4V VDD1 GND1 20 42 38 37 {13} LCD_B2 (9) VEE1 PVEE {13} VDD2 GND2 21 43 30 31 LCD_B3 {13} (8) VSS1 DCNEG14V {13} VDD3 GND3 22 44 {13} LCD_B4 (7) CLS LCD_CLS {13} 23 45 LCD_B5 {13} (6) SPS LCD_SPS {13} A 24 46 A {13} LCD_ENAB (5) UL LCD_UBL {13}
25 47 0.1UF (4) MOD2 LCD_MODE{13} C119 26 48 LCD_DC3P3V (3) MOD1 LCD_MODE{13} 27 LCD_DC3P3V (2) VCC1 49 DCNEG11P7V{13} 50 (1) VDD1 DC_15V {13,15} JAE PXA250 Processor Reference Design
IL-FHJ-27S-HF Molex TOP_CONN_50 Size Rev B 2.07
54104-5090 Date: Tuesday, February 05, 2002 Sheet 14 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation J15 RCPT AMP J16 RCPT AMP 2 1 2 1 Pg. 15 4 3 4 3 {6,10} VX_A0 C1 VX_A1 {6,10} {6,10} VX_A0 C1 VX_A1 {6,10} C2 C1 C2 C1 6 5 6 5 {6,10} VX_A2 C2 VX_A3 {6,10} {6,10} VX_A2 C2 VX_A3 {6,10} {7,10} VX_A4 8 7 VX_A5 {7,10} {7,10} VX_A4 8 7 VX_A5 {7,10} 10 9 10 9 {7,10} VX_A6 C3 VX_A7 {7,10} {7,10} VX_A6 C3 VX_A7 {7,10} C4 C3 C4 C3 12 11 12 11 {7,10} VX_A8 C4 VX_A9 {7,10} {7,10} VX_A8 C4 VX_A9 {7,10} 14 13 14 13 {7,10} VX_A10 VX_A11 {7} {7,10} VX_A10 VX_A11 {7} 16 15 16 15 D {7} VX_A12 VX_A13 {7} {7} VX_A12 VX_A13 {7} D DC3P3V 18 17 DC3P3V 18 17 DC3P3V {7} VX_A14 VX_A15 {7} {7} VX_A14 VX_A15 {7} 20 19 DC3P3V 20 19 {7} VX_A16 VX_A17 {7} {7} VX_A16 VX_A17 {7} 22 21 22 21 {7} VX_A18 VX_A19 {7} {7} VX_A18 VX_A19 {7} 24 23 24 23 {7} VX_A20 C5 VX_A21 {7} {7} VX_A20 C5 VX_A21 {7} C6 C5 C6 C5 26 25 26 25 {7} VX_A22 C6 VX_A23 {7} {7} VX_A22 C6 VX_A23 {7} 28 27 28 27 {7} VX_A24 VX_A25 {7} {7} VX_A24 VX_A25 {7} 30 C7 29 30 C7 29 C8 C7 C8 C7 32 31 32 31 {7} VX_nSDCS_0 C8 VX_nSDCS_2{6} {7} VX_nSDCS_0 C8 VX_nSDCS_2 {6} 34 33 34 33 {7} VX_nSDCAS VX_DQM_3 {7} {7} VX_nSDCAS VX_DQM_3 {7} 36 35 36 35 {7} VX_nSDRAS VX_DQM_2 {7} {7} VX_nSDRAS VX_DQM_2 {7} 38 37 38 37 {3} BOOT_SEL_0 VX_DQM_1 {7} {3} BOOT_SEL_0 VX_DQM_1 {7} 40 39 40 39 {2} SA_SDCKE_0 VX_DQM_0 {7} {2} SA_SDCKE_0 VX_DQM_0 {7} {3} BOOT_SEL_1 42 41 {3} BOOT_SEL_1 42 41 {6} VX_SDCKE_1 44 C9 43 SA_SDCLK_0{2,5} {6} VX_SDCKE_1 44 C9 43 SA_SDCLK_0 {2,5} C10 C9 C10 C9 46 C10 45 46 C10 45 48 47 48 47 {7} VX_SDCLK_1 VX_SDCLK_2{6} {7} VX_SDCLK_1 VX_SDCLK_2 {6} 50 C11 49 50 C11 49 C12 C11 C12 C11 {2,6} SA_RD_nWR 52 C12 51 MBREQ_CF_DETECT {3,13} {2,6} SA_RD_nWR 52 C12 51 MBREQ_CF_DETECT{3,13} 54 53 54 53 {4,13} nGFX_PRESENT MBGNT_CF_IRQ {3,6} {4,13} nGFX_PRESENT MBGNT_CF_IRQ {3,6} 56 55 56 55 C {6,10} CF_IRQ_LVL2OE DREQ_1 {11} {6,10} CF_IRQ_LVL2OE DREQ_1 {11} C nJTAG_TRST 58 57 VX_D1 {7,10} nJTAG_TRST 58 57 VX_D1 {7,10} LCD_DC5V 60 59 LCD_DC5V 60 59 LCD_DC5V {7,10} VX_D0 VX_D3 {7,10} {7,10} VX_D0 VX_D3 {7,10} {7,10} VX_D2 62 61 VX_D5 {7,10} {7,10} VX_D2 62 61 VX_D5 {7,10} {7,10} VX_D4 64 C13 63 VX_D7 {7,10} {7,10} VX_D4 64 C13 63 VX_D7 {7,10} C14 C13 LCD_DC5V C14 C13 {7,10} VX_D6 66 C14 65 VX_D9 {7,10} {7,10} VX_D6 66 C14 65 VX_D9 {7,10} 68 67 68 67 DC3P3V {7,10} VX_D8 VX_D11 {7,10} {7,10} VX_D8 VX_D11 {7,10} 70 69 DC3P3V 70 69 {7,10} VX_D10 C15 VX_D13 {7,10} {7,10} VX_D10 C15 VX_D13 {7,10} C16 C15 C16 C15 72 71 72 71 {7,10} VX_D12 C16 VX_D15 {7,10} {7,10} VX_D12 C16 VX_D15 {7,10} 74 73 74 73 {7,10} VX_D14 {7,10} VX_D14 76 75 76 75 {7} VX_D16 VX_D17 {7} VX_D16 VX_D17 {7} 78 77 {7} 78 77 {7} VX_D18 VX_D19 {7} {7} VX_D18 VX_D19 {7} 80 79 80 79 {7} VX_D20 VX_D21 {7} {7} VX_D20 VX_D21 {7} 82 81 82 81 {7} VX_D22 VX_D23 {7} {7} VX_D22 VX_D23 {7} {7} VX_D24 84 C17 83 VX_D25 {7} {7} VX_D24 84 C17 83 VX_D25 {7} C18 C17 C18 C17 86 85 86 85 {7} VX_D26 C18 VX_D27 {7} {7} VX_D26 C18 VX_D27 {7} 88 87 88 87 {7} VX_D28 VX_D29 {7} VX_D28 VX_D29 {7} 90 89 {7} 90 89 {7} VX_D30 C19 VX_D31 {7} {7} VX_D30 C19 VX_D31 {7} C20 C19 C20 C19 {4,13} nNEP_PRESENT 92 C20 91 IN_PWR {10,12} {4,13} nNEP_PRESENT 92 C20 91 IN_PWR {10,12} 94 93 DC3P3V 94 93 {2} SA_RDY SA_nCS_5 {2,6} {2} SA_RDY SA_nCS_5 {2,6} B VX_nWE 96 95 SA_nCS_4 {2,6} {7} VX_nWE 96 95 SA_nCS_4 {2,6} B DC3P3V {7} DC3P3V DC3P3V {6,7} VX_nOE 98 97 SA_nCS_3 {2,6} {6,7} VX_nOE 98 97 SA_nCS_3 {2,6} {13,14} DC_15V 100 99 nNEP_REG_CS {6,10} {13,14} DC_15V 100 99 nNEP_REG_CS {6,10} 102 101 102 101 {3,10,11} nRESET_IN nNEP_FLASH_CS{6} {3,10,11} nRESET_IN nNEP_FLASH_CS {6} 104 103 104 103 {3,6,11,13} nRESET_OUT C21 SA_nCS_0 {2,6} {3,6,11,13} nRESET_OUT C21 SA_nCS_0 {2,6} C22 C21 C22 C21 106 105 106 105 {6,10} CF_GFX_RESET C22 {6,10} CF_GFX_RESET C22 {3,10} GFX_IRQ_CF_BVD2 108 107 SYSCLK {8,13} {3,10} GFX_IRQ_CF_BVD2 108 107 SYSCLK {8,13} 110 109 110 109 VDD_FAULT C23 {13} VDD_FAULT C23 {13} C24 C23 C24 C23 112 111 112 111 {3,10} SA1111_IRQ_CF_BVD1 C24 SA_nPOE {2,6} {3,10} SA1111_IRQ_CF_BVD1 C24 SA_nPOE {2,6} 114 113 114 113 {10,12} IN_PWR SA_nPWE {2,6} {10,12} IN_PWR SA_nPWE {2,6} {2,6} SA_nIOIS16 116 115 SA_nPIOW {2,6} {2,6} SA_nIOIS16 116 115 SA_nPIOW {2,6} 118 117 118 117 {2,6} SA_nPWAIT SA_nPIOR {2,6} {2,6} SA_nPWAIT SA_nPIOR {2,6} 120 119 120 119 {2} SA_PSKTSEL SA_nPCE_1{2,6} {2} SA_PSKTSEL SA_nPCE_1{2,6} 122 121 122 121 {2,6} SA_nPREG SA_nPCE_2{2,6} {2,6} SA_nPREG SA_nPCE_2{2,6} 124 C25 123 124 C25 123 C26 C25 C26 C25 126 125 126 125 DVAL_1 C26 SA_BT_RXD {2,11} {11} DVAL_1 C26 SA_BT_RXD {2,11} {11} 128 127 128 127 {11} DVAL_0 SA_BT_TXD {2,11} {11} DVAL_0 SA_BT_TXD {2,11} 130 129 130 129 {11} DREQ_0 C27 SWAP_FLASH{6} {11} DREQ_0 C27 SWAP_FLASH {6} C28 C27 C28 C27 {3,10} GPIO_0 132 C28 131 SA_FF_TXD {2,10} {3,10} GPIO_0 132 C28 131 SA_FF_TXD {2,10} 134 133 134 133 {3,9} USB_WAKE SA_FF_RXD {2,10} {3,9} USB_WAKE SA_FF_RXD {2,10} A 136 135 136 135 A SA_I2C_SDA {2,10,12} 138 137 {2,10,12} SA_I2C_SDA 138 137 SA_I2C_SCL nVBATT_LOW_IRQ {3,12} SA_I2C_SCL nVBATT_LOW_IRQ {3,12} {2,10,12} 140 139 {2,10,12} 140 139
536279-6 536279-6 PXA250 Processor Reference Design
Expansion Expansion Size Rev Header 1 Header 2 B 2.07 Date: Tuesday, February 05, 2002 Sheet 15 of 16 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
Copyright 2002 Intel Corporation Pg. 16
Revision Tracking Changes R 2.00 - 09-21-01 - Inital Release R 2.01 - 09-25-01 - CHRGR_PRESENT signal changed to nCHRGR_PRESENT to properly represent active low signal - Pages 2, 3 & 12 R 2.01 - 09-25-01 - R281, nCHRGR_PRESENT 100k pull-up added - Page 2 R 2.01 - 09-25-01 - R262, PLL_SENSE pull-down, removed from DNI list - Page 3 R 2.01 - 09-25-01 - C60, C65, R97 & R98 Removed from schematics - Page 8 D R 2.01 - 09-25-01 - C3 & C4 values changed to 1uF - Page 9 D R 2.01 - 09-25-01 - U20 powered from AUDIO3P3V instead of DC3P3V - Page 9 R 2.01 - 09-25-01 - C138 Added to DNI List - Page 12 R 2.02 - 09-28-01 - U10, XCR3032C CPLD, replaced with newer XPLA3 XCR3032XL - Page 6 R 2.02 - 09-28-01 - Changed U43 part description to properly reflect part - Page 12 R 2.02 - 09-28-01 - R276 9.76k resistor replaced with 19.6k resistor - Page 12 R 2.02 - 09-28-01 - R276 .15 ohm resistor replaced with .1 ohm resistor - Page 12 R 2.02 - 09-28-01 - U33, XCR3128 CPLD, replaced with newer XPLA3 XCR3128XL - Page 13 R 2.03 - 10-10-01 - Y4, Changed component vendor - Page 3 R 2.03 - 10-10-01 - R275, Changed component vendor - Page 12 R 2.03 - 10-10-01 - R276, 19.6k resistor, replaced with 20k resistor - Page 12 R 2.04 - 10-12-01 - Q1, P-channel MOSFET, replaced with a higher power dissipating component - Page 12 R 2.05 - 10-16-01 - C53,C54,C55 & C56 Moved to prevent coupling with the UCB1400 - Page 8 R 2.05 - 10-16-01 - R282, 0 ohm resistor, Added UCB1400 power test point- Page 8 R 2.05 - 10-16-01 - R99, 0 ohm resistor, replaced with 10 ohm resistor - Page 8 R 2.05 - 10-16-01 - R99 connected to AUDIO3P3V - Page 8 R 2.06 - 11-09-01 - Y4, Changed component vendor - Page 3 R 2.06 - 11-09-01 - R275, Changed component vendor - Page 12 R 2.06 - 11-09-01 - Changed C143 part description to properly reflect part- Page 12 R 2.07 - 02-05-02 - U2, 3.1V Reset Supervisor, replaced with 2.7V Reset Supervisor - Page 3 R 2.07 - 02-05-02 - R112 & R115, 27.4 ohm resistor, replaced with 0 ohm resistor- Page 9 R 2.07 - 02-05-02 - R168, 150K resistor, replaced with a 160K resistor - Page 12 R 2.07 - 02-05-02 - R170, 100K resistor, added to DNI list - Page 12 C R 2.07 - 02-05-02 - R210, 1K resistor, disconnected from IN_PWR net and connected to DC3P3V instead - Page 12 C
B B
A A
PXA250 Processor Reference Design
Size Rev B 2.07
Date: Tuesday, February 05, 2002 Sheet 16 of 16 8 7 6 5 4 3 2 1 Example Form Factor Reference Design Schematic Diagrams
B-18 Intel® PXA255 Processor Design Guide BBPXA2xx Development Baseboard Schematic Diagram C
C.1 Schematic Diagram
The BBPXA2xx schematic is on the following pages.
Intel® PXA255 Processor Design Guide C-1 BBPXA2xx Table of Contents
Page Function Page Function Page Function
2 Top level block diagram 18 SWITCHES 34 LOGIC ANALYZER
3 Processor Card Connector 19 SPII SPROM 35 RESET & FAULT SWITCHES
4 Data Buffers/Transceivers 20 SA-1111 INTERFACE 36 3.3V & 5V SUPPLY
5 Data Buffers/Transceivers 21 CF & PCMCIA I/O 37 POWER SUPPLY INPUT
6 Address BUFFERS/TRANSCEIVERS 22 CF & PCMCIA PU 38 SPARES
7 SPX ADDRESS BUFFERS 23 SA-1111 USB KB/MS 8 CONTROL BUFFERS/TRANSCEIVERS 24 BUFFER CONTROL LOGIC
9 X ADDRESS BUFFERS 25 LCD BUFFERS
10 BFR ADDRESS BUFFERS 26 IrDA & FF SERIAL & USB 11 SRAM 27 CS4201 CODEC
12 FLASH 28 UCB1400 CODEC
13 ROM 29 BB TOUCH SCREEN & GPIO HEADER
14 REGISTER & CONTROL 30 CODEC MUX & SPII 2.5V
15 HEX DISPLAY HIGH 31 SDCARD & BT SERIAL
16 HEX DISPLAY LOW 32 10Mbps ETHERNET 17 LEDs & HEX SWITCHES 33 XPANSION PORT
BBPXA2xx Development Baseboard Schematic Diagram
C-40 Intel® PXA255 Processor Design Guide PXA250 Processor Card Schematic Diagram D
D.1 Schematic Diagram
The DCPXA250 processor card schematic is on the following pages. The PXA255 processor is a drop in replacement for the Intel® PXA250 processor and is fully compatible with these schematics.
Intel® PXA255 Processor Design Guide D-1 1234
D D Intel(R) DCPXA250 Processor Card 32-bit version
TABLE OF CONTENTS
C C PAGE FUNCTION
1 TITLE PAGE
2 PROCESSOR --- PXA250 3 SDRAM 4 CONNECTOR (MEMORY and I/O SIGNALS)
B 5 CLOCKS B
6 JTAG CONNECTOR & PLL and CORE VOLTAGE REGULATORS 7 BYPASS CAPS 8-10 Bus Terminators 11-12 Data, Address and Control Transceivers 13 CPLD A A 14 FLASH
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 1
REV Project: DCPXA250 Schematic: Title Page
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(01;) Fri Oct 11 10:19:07 2002 1234
VCCN
C139B C195B C202B C134B C157B IXM_ADDR
0.015uF 0.015uF 0.015uF 0.015uF 0.015uF
IXM_DATA D VCCN D IXM_ADDR[7] IXM_ADDR[6] IXM_ADDR[5] IXM_ADDR[4] IXM_ADDR[3] IXM_ADDR[2] IXM_ADDR[1] IXM_ADDR[0] IXM_ADDR[25] IXM_ADDR[24] IXM_ADDR[23] IXM_ADDR[22] IXM_ADDR[21] IXM_ADDR[20] IXM_ADDR[19] IXM_ADDR[18] IXM_ADDR[17] IXM_ADDR[16] IXM_ADDR[15] IXM_ADDR[14] IXM_ADDR[13] IXM_ADDR[12] IXM_ADDR[11] IXM_ADDR[10] IXM_ADDR[9] IXM_ADDR[8] IXM_CNTL 1 IXM_DATA[31] IXM_DATA[30] IXM_DATA[29] IXM_DATA[28] IXM_DATA[27] IXM_DATA[26] IXM_DATA[25] IXM_DATA[24] IXM_DATA[23] IXM_DATA[22] IXM_DATA[21] IXM_DATA[20] IXM_DATA[19] IXM_DATA[18] IXM_DATA[17] IXM_DATA[16] IXM_DATA[15] IXM_DATA[14] IXM_DATA[13] IXM_DATA[12] IXM_DATA[11] IXM_DATA[10] IXM_DATA[9] IXM_DATA[8] IXM_DATA[7] IXM_DATA[6] IXM_DATA[5] IXM_DATA[4] IXM_DATA[3] IXM_DATA[2] IXM_DATA[1] IXM_DATA[0] C190B C166B C174B C188B
0.1uFC161B 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 2 M3 K6 J6 H2 P4 T5 P5 R5 T4 R3 P2 R1 P1 N3 M1 L3 L1 K5 K2 K1 J1 J3 J5 H6 H1 G1 P12 R11 P10 L8 P8 P7 R7 P6 T3 N1 M2 L4 K3 J4 H5 H3 M10 T12 N10 P11 T11 R9 T10 M9 M7 M6 T7 N6 T6 L5 M5 N4 MD1 MD0 MD9 MD8 MD7 MD6 MD5 MD3 MD2 MD4 MA1 MA9 MA8 MA7 MA6 MA5 MA3 MA2 MA0 MA4 MD11 MD31 MD21 MD19 MD18 MD17 MD16 MD15 MD13 MD12 MD10 MD30 MD29 MD28 MD27 MD26 MD25 MD23 MD22 MD20 MD14 MA11 MD24 MA13 MA12 MA10 MA19 MA18 MA17 MA16 MA15 MA21 MA14 MA20 MA25 MA23 MA22 MA24 PLL_VCC J15 PLL_VCC F13 J16 BOOT_SEL2 PLL_SENSE G13 CLOCKS BOOT_SEL1 PXTAL K15 G16 PXTAL BOOT_SEL0 PEXTAL K16 C1 RDY PEXTAL RDY/GP18 R21 R57B R51B TXTAL L16 TXTAL T13 nCS5 0ohms 0ohms 0ohms nCS5/GP33 TEXTAL L15 TEXTAL R13 nCS4 R63B nCS4/GP80 10Kohms G11 T9 nCS3 TESTCLK nCS3/GP79 G12 P9 nCS2 R62B TEST nCS2/GP78
PERIPH_SIGS 0ohms T8 nCS1 TCK H12 nCS1/GP15
TCK N8 nCS0 TDI H15 nCS0 TDI TDO H16 G5 nOE TDO nOE TMS H13 G4 nWE C TMS nWE C nTRST H11 U10 D3 RD/nWR nTRST RD/nWR POWER_SIGS nRESET J13 E3 SDCKE1 nRESET SDCKE1 nRESET_OUT K11 E4 SDCKE0 TP10 nRESET_OUT SDCKE0 D1 SDCLK2 VCCN PWR_EN L11 SDCLK2 YEL PXA250mBGA-256 Socket NP PWR_EN F5 SDCLK1 SDCLK1 PWR_EN nVDD_FAULT K13 R29 nVDD_FAULT D2 SDCLK0 100Kohms nBATT_FAULT K12 SDCLK0 nPWAIT nBATT_FAULT
E1 nSDRAS nSDRAS PXA250 F3 nSDCAS nSDCAS
F2 nSDCS3 nSDCS3 G3 nSDCS2 nSDCS2 G6 nSDCS1 nSDCS1 CORE_VCC = F11, G7, G9, H10, J7, K8, K10, L6, & L9 F1 nSDCS0 nSDCS0
VCCQ = C6, C10, C13, E14, D15, M11 & G14 L7 DQM3 DQM3 L_BIAS A8 B2 DQM2 L_BIAS/GP77 DQM2 VCCN = A1, D4, F4, H4, K4, M4, M14, N5, L_PCLK B8 N7, N9, N11, N13, P3, T2, & T16 B1 DQM1 L_PCLK/GP76 DQM1 L_LCLK D8 M8 DQM0 L_LCLK/GP75 DQM0 VSS = C16, H8, H9, J8, J9, & T1 L_FCLK E8 L_FCLK/GP74 M12 GP22 GP22 L_DD15 B3 VSSQ = C4, C8, C11, C14, D16, E15, E16, F15, F16, F6, G8, G10, L_DD15/GP73 N15 GP21 B H7, J10, J14, K7, K9, & L14 VCCN B L_DD14 C3 GP21 L_DD14/GP72 N14 DREQ1 DREQ1/GP19 L_DD13 A2 VSSN = C2, E2, G2, J2, L2, M15, N2, P15, R50B L_DD13/GP71 N12 R2, R4, R6, R8, R10, R12, & R14 DREQ0 100Kohms L_DD12 A3 DREQ0/GP20 nPIOIS16 L_DD12/GP70 L_DD11 A4 P13 nPOE L_DD11/GP69 nPOE/GP48 VCCQ L_DD10 D5 T14 nPWE L_DD10/GP68 nPWE/GP49 R48B 100Kohms L_DD9 A5 T15 nPIOR GP22 L_DD9/GP67 nPIOR/GP50 L_DD8 C5 R15 nPIOW L_DD8/GP66 nPIOW/GP51
L_DD7 A6 P14 nPCE1 L_DD7/GP65 nPCE1/GP52 R49B C129B C153B 100Kohms L_DD6 E5 R16 nPCE2 GP21 L_DD6/GP64 nPCE2/GP53 0.015uF 0.015uF L_DD5 D6 P16 nPSKTSEL L_DD5/GP63 PSKTSEL/GP54 L_DD4 E6 M13 nPREG L_DD4/GP62 nPREG/GP55 L_DD3 B7 N16 nPWAIT L_DD3/GP61 nPWAIT/GP56
L_DD2 C7 M16 nPIOIS16 L_DD2/GP60 nPIOIS16/GP57 L_DD1 D7 L_DD1/GP59 L_DD0 E7 L_DD0/GP58 FF_DCD/GP36 FF_CTS/GP35 FF_TXD/GP39 FF_RXD/GP34 SCL SDA nAC_RST AC_SYNC/GP31 AC_SDOUT/GP30 AC_SDIN0/GP29 AC_BITCLK/GP28 SSP_EXTCLK/GP27 SSP_RXD/GP26 SSP_TXD/GP25 SSP_SFRM/GP24 SSP_SCLK/GP23 USB_P USB_N MMCMD MMDAT PWM1/GP17 PWM0/GP16 IR_TXD/GP47 IR_RXD/GP46 BT_RTS/GP45 BT_CTS/GP44 BT_TXD/GP43 BT_RXD/GP42 FF_RTS/GP41 FF_DTR/GP40 FF_RI/GP38 FF_DSR/GP37 GP14/MBREQ GP13/MBGNT GP12/32kHz_OUT GP11/3.6MHz_OUT GP10/RTC_CLK GP9/MMC_CS1 GP8/MMC_CS0 GP7/48MHz_OUT GP6/MMC_CLK GP5 GP4 GP3 GP2 GP1/nGP_RST GP0 SYSCLK/AC_SDIN1/GP32
F8 C9 D9 E9 F9 F7 B9 B5 B6 B4 A9 A7 J11 J12 E11 D11 C12 D10 F10 B11 E13 E10 L13 L12 L10 D12 E12 C15 D13 F12 B12 B10 D14 B16 B15 B13 F14 G15 A11 K14 B14 H14 A12 A13 A10 A15 A16 A14 R18 GP3 GP2 GP1 GP0 GP14 GP13 GP12 GP11 GP10 GP9 GP7 GP5 GP4 0ohms R19 GPIO_SIGS R20 R17
0ohms GP32 UDC-
UDC+ MMCMD
A MMDAT A AC_SDIN AC_BITCLK SSP_EXTCLK SSP_RXD SSP_TXD SSP_SFRM SSP_SCLK FF_DCD FF_CTS FF_TXD FF_RXD SCL SDA AC_SYNC IR_TXD IR_RXD BT_RTS BT_CTS BT_TXD BT_RXD FF_RTS FF_DTR FF_RI FF_DSR PWM1 PWM0 MMCCS0 MMCLK 22ohms 22ohms nAC_RST RP9B
1mohms Intel Corp. DCPXA250 Processor Card
R16 Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 2
AC_SOUT 56ohms REV Project: DCPXA250 Schematic: DCPXA250
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(02;) Fri Oct 11 10:19:07 2002 1234
D D
+3.3V +3.3V 1 C117B C96B C65 C107B
0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 2
IXM_ADDRST
U12 U20B SDRAM_4Mx16x4 SDRAM_4Mx16x4 C C IMX_ADDRST[23] 20 IMX_ADDRST[23] 20 BA0 BA0 IMX_ADDRST[22] 21 IMX_ADDRST[22] 21 BA1 BA1
IMX_ADDRST[24] 36 IMX_ADDRST[24] 36 A12 A12 IMX_ADDRST[21] 35 IMX_ADDRST[21] 35 A11 A11 IMX_ADDRST[20] 22 IMX_ADDRST[20] 22 A10 A10 IMX_ADDRST[19] 34 IMX_ADDRST[19] 34 A9 A9 IMX_ADDRST[18] 33 IMX_ADDRST[18] 33 A8 A8 IMX_ADDRST[17] 32 IMX_ADDRST[17] 32 A7 A7 IMX_ADDRST[16] 31 IMX_ADDRST[16] 31 A6 A6 IMX_ADDRST[15] 30 53 IXM_DATAST[15] IMX_ADDRST[15] 30 53 IXM_DATAST[31] A5 DQ15 A5 DQ15 IMX_ADDRST[14] 29 51 IXM_DATAST[14] IMX_ADDRST[14] 29 51 IXM_DATAST[30] A4 DQ14 A4 DQ14 IMX_ADDRST[13] 26 50 IXM_DATAST[13] IMX_ADDRST[13] 26 50 IXM_DATAST[29] A3 DQ13 A3 DQ13 IMX_ADDRST[12] 25 48 IXM_DATAST[12] IMX_ADDRST[12] 25 48 IXM_DATAST[28] A2 DQ12 A2 DQ12 IMX_ADDRST[11] 24 47 IXM_DATAST[11] IMX_ADDRST[11] 24 47 IXM_DATAST[27] A1 DQ11 A1 DQ11 IMX_ADDRST[10] 23 45 IXM_DATAST[10] IMX_ADDRST[10] 23 45 IXM_DATAST[26] A0 DQ10 A0 DQ10 44 IXM_DATAST[9] 44 IXM_DATAST[25] nSDCS0_ST 19 DQ9 nSDCS0_ST 19 DQ9 CS 42 IXM_DATAST[8] CS 42 IXM_DATAST[24] DQ8 DQ8 nSDRAS_ST 18 13 IXM_DATAST[7] nSDRAS_ST 18 13 IXM_DATAST[23] RAS DQ7 RAS DQ7 11 IXM_DATAST[6] 11 IXM_DATAST[22] K4S561632A-TC/L75a K4S561632A-TC/L75a nSDCAS_ST 17 DQ6 nSDCAS_ST 17 DQ6 CAS 10 IXM_DATAST[5] CAS 10 IXM_DATAST[21] DQ5 DQ5 DQM1_ST 39 8 IXM_DATAST[4] DQM3_ST 39 8 IXM_DATAST[20] B DQMH DQ4 DQMH DQ4 B 7 IXM_DATAST[3] 7 IXM_DATAST[19] DQM0_ST 15 DQ3 DQM2_ST 15 DQ3 DQML 5 IXM_DATAST[2] DQML 5 IXM_DATAST[18] DQ2 DQ2 nWE_ST 16 4 IXM_DATAST[1] nWE_ST 16 4 IXM_DATAST[17] WE DQ1 WE DQ1 2 IXM_DATAST[0] 2 IXM_DATAST[16] SDCKE1_ST 37 DQ0 SDCKE1_ST 37 DQ0 CKE CKE 38 38 CLK CLK SDCLK1_ST SDCLK1_ST K4S561632B K4S561632B
IXM_CNTLST
IXM_DATAST
A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 3
REV Project: DCPXA250 Schematic: SDRAM
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(03;) Fri Oct 11 10:19:07 2002 1234
PERIPH_SIGS IXM_CNTL
POWER_SIGS
J10B
VCC +3.3V
1 2 nRESET 115 116 nRESET_OUT D 3 4 D PWR_EN 117 118 nBATT_FAULT J10B 5 6 nVDD_FAULT 119 120 JTAG_CPU_RST# 7 8 121 122 RDY 9 10 nPWAIT 123 124 nPIOIS16 11 12 TP13 TP4 nPSKTSEL 125 126 nPREG 13 14 nPCE1 128 nPCE2 BLK YEL 127 PB11 15 16 PB11 nPIOR 129 130 nPIOW PB12 SDA 17 18 PB12 nPOE_STB 131 132 nPWE_STB PB13 SCL 19 20 PB13 SSP_EXTCLK nCS5_STB 133 134 nCS4_STB PB14 21 22 DREQ1_STB PB14 BLADE 1 nCS3_STB 135 136 nCS2_STB PB15 BLADE4 SSP_EXTCLK 23 24 DREQ0_STB PB15 nCS1_STB 137 138 nCS0_STB SSP_TXD 25 26 SSP_RXD 140 VCC 139 +3.3V SSP_SCLK 27 28 SSP_SFRM 141 142 nAC_RST 29 30 144 143 PB21 AC_SOUT 31 32 AC_SYNC PB21 IXM_DATASTB[31] 145 146 IXM_DATASTB[30] PB22 33 34 AC_SDIN PB22 IXM_DATASTB[29] 147 148 IXM_DATASTB[28] PB23 AC_BITCLK 35 36 MMCCS0 PB23 IXM_DATASTB[27] 149 150 IXM_DATASTB[26] Samtec-MIT-114-03-L-D PB24 37 38 MMCMD PB24 IXM_DATASTB[25] 151 152 IXM_DATASTB[24] PB25 PB25
39 40 PWM1 IXM_DATASTB[23] 153 154 IXM_DATASTB[22] MMCLK 41 42 FF_DTR IXM_DATASTB[21] 155 156 IXM_DATASTB[20] 43 44 FF_DSR C IXM_DATASTB[19] 157 158 IXM_DATASTB[18] PB31 C MMDAT 45 46 FF_CTS PB31 IXM_DATASTB[17] 159 160 IXM_DATASTB[16] PB32 PWM0 47 48 FF_RXD PB32 IXM_DATASTB[15] 161 162 IXM_DATASTB[14] PB33 FF_RTS 49 50 IR_RXD PB33 IXM_DATASTB[13] 163 164 IXM_DATASTB[12] PB34 FF_RI 51 52 BT_CTS PB34 IXM_DATASTB[11] 165 166 IXM_DATASTB[10] PB35 FF_DCD 53 54 BT_RXD PB35 IXM_DATASTB[9] 167 168 IXM_DATASTB[8] FF_TXD 55 56 IXM_DATASTB[7] 169 170 IXM_DATASTB[6] IR_TXD 57 58 UDC- IXM_DATASTB[5] 171 172 IXM_DATASTB[4] BT_RTS 59 60 UDC+ BLADE 5 BLADE 2 IXM_DATASTB[3] 173 174 IXM_DATASTB[2] PB41 BT_TXD 61 62 PB41 IXM_DATASTB[1] 175 176 IXM_DATASTB[0] PB42 PDC_ID[3] 63 64 PB42 177 178 PB43 PDC_ID[2] 65 66 PB43 IMX_ADDRSTB[25] 179 180 IMX_ADDRSTB[24] PB44
PDC_ID[1] 67 68 Samtec-MIT-114-03-L-D PB44
Samtec-MIT-114-03-L-D IMX_ADDRSTB[23] 181 182 IMX_ADDRSTB[22] PB45 PDC_ID[0] 69 70 PB45 Samtec-MIT-114-03-L-D IMX_ADDRSTB[21] 183 184 IMX_ADDRSTB[20]
+3.3V Samtec-MIT-114-03-L-D WHO_ID 71 72 IMX_ADDRSTB[19] 185 186 IMX_ADDRSTB[18] 74 VCC 73 IMX_ADDRSTB[17] 187 188 IMX_ADDRSTB[16] R6 75 76 PDC_ID[3] IMX_ADDRSTB[15] 189 190 IMX_ADDRSTB[14] PB51 PB51 0ohms PB52 L_BIAS 78 L_PCLK 77 PB52 IMX_ADDRSTB[13] 191 192 IMX_ADDRSTB[12] PB53 R7 L_LCLK 79 80 L_FCLK PB53 PDC_ID[2] IMX_ADDRSTB[11] 193 194 IMX_ADDRSTB[10] PB54 L_DD15 81 82 L_DD14 PB54 0ohms IMX_ADDRSTB[9] 195 196 IMX_ADDRSTB[8] PB55 L_DD13 84 L_DD12 83 PB55 B IMX_ADDRSTB[7] 197 198 IMX_ADDRSTB[6] B R9 L_DD11 85 86 L_DD10 PDC_ID[1] IMX_ADDRSTB[5] 199 200 IMX_ADDRSTB[4] L_DD9 87 88 L_DD8 0ohms IMX_ADDRSTB[3] 201 202 IMX_ADDRSTB[2] L_DD7 90 L_DD6 89 204 IMX_ADDRSTB[1] 203 IMX_ADDRSTB[0] PB61 L_DD5 91 92 L_DD4 PB61 R11 205 206 PB62 PDC_ID[0] L_DD3 93 94 L_DD2 PB62 RD/nWR_STB 207 208 nWE_STB PB63 0ohms L_DD1 95 96 L_DD0 PB63 nOE_STB 209 210 DQM0_STB PB64
BLADE 6 BLADE 5 BLADE 4 BLADE 3 BLADE 2 BLADE 1 97 98 PB64 BLADE 3 DQM1_STB 211 212 DQM2_STB PB65 BLADE 6 GP14 99 100 Samtec-MIT-114-03-L-D PB65 DQM3_STB 213 214 nSDCS0_STB GP12 101 102 GP13 nSDCS1_STB 215 216 nSDCS2_STB GP10 103 104 GP11 nSDCS3_STB 217 218 nSDCAS_STB 105 106 GP9 nSDRAS_STB 219 220 SDCKE0_STB GP32 107 108 GP7 SDCKE1_STB 221 222 GP4 109 110 GP5 223 224 SDCLK0_STB GP2 111 112 GP3 SDCLK1_STB 225 226 GP0 113 114 GP1 227 228 SDCLK2_STB
PERIPH_SIGS J10B GPIO_SIGS A A IXM_DATASTB
IXM_ADDRSTB
Intel Corp. DCPXA250 Processor Card IXM_CNTLSTB Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 4
REV Project: DCPXA250 Schematic: Daugtercard Connector
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(04;) Fri Oct 11 10:19:07 2002 1234
CLOCKS
D PXTAL D
1 X1
Fox-HC49S 3.6864 MHz 2 VCCN NP R59B 1Kohms OSC_PEXTAL PEXTAL 1 1 1 1 1 Voltage divider to bring down to VCC_CORE (1.0-1.3) C165B C144B C103B C109B C185B C189B C154B C143B C178B C184B C77
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 22uF 21 21 21 21 21 2 2 2 2 2 R61B 470ohms NP
VCC
VCCN C3 C73 C68 22uF 22uF 22uF TXTAL C205B C152B C151B C173B 1uF 1uF 1uF 1uF C C32 1 X2 C 4.7uF
Fox-NC38 2 32.768 kHz
C27 C58 C57 1uF 1uF 1uF TEXTAL VCCQ 1 C169B C149B C137B C133B C135B
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 2
+3.3V CORE_VCC
C25 C79 C86 1 1 B 22uF 22uF 22uF 1 1 B C170B C164B C162B C194B C150B C91B C99B C163B C136B C160B
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 21 21 +3.3V 2 2 2 2
C76 4.7uF 1 1 1 1 C21 C100B C120B C17 C19 C97B C118B C114B
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 2 2 2 2 CORE_VCC C2 C198B 1uF 1uF
C201B C172BC199B C122B 1uF 1uF 1uF 1uF
+3.3V
VCCQ
C39 C46 C61 C20 C9 C37 C92B C78 1uF 1uF 1uF 1uF 1uF 1uF 1uF 1uF C130B C183B C128B C36 1uF 1uF 1uF 1uF
A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 5
REV Project: DCPXA250 Schematic: Clocks
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(05;) Fri Oct 11 10:19:07 2002 1234
+3.3V
+3.3V TP11 U1 VCCN VCCN +3.3V +3.3V 5 C87B Molex_2_Header_TH Molex_2_Header_TH RED MAX823TEUK R33B VCC C155B C176B C132B C196B MAX823TEUK 0.1uF 0ohms 1
2 1 2 1 RESET 1 1 2 2 0.1uF 0.1uF 0.01uF 0.01uF VCCN 2 2 R34B 0.1uF 0.1uF 0.1uF 0.1uF J6 J8 4 3 1.5Kohms WDI MR
C50 C60 PERIPH_SIGS 12 12 1 1
D C168B C177B GND J2 D TP12 VCCQ VCCQ C138B C148B C131B C158B 2 nTRST 1 2 RED 0.1uF 0.1uF 0.01uF 0.01uF Molex_2_Header_TH Molex_2_Header_TH 3 4 VCCQ
1 1 TDI 5 6 2 2 +3.3V 2 2 TMS 7 8 J7 J9
0.1uF 0.1uF 0.1uF 0.1uF R44B TCK 9 10 1.5Kohms C54 12 12 1 1 11 12 C171B C113B C102B VCC
TDO 13 14
JTAG_CPU_RST# 15 16
C16 C88B 17 18 R1 R46B 20ohms 19 20
1uF 1uF Molex_70246-2021
0ohms +3.3V C4 R45B C11 C89B 4.7uF R36B PTH-20-VERT_HDR 1.5Kohms VCC_SPLY R41B 1uF 1uF 0ohms 10Kohms
+3.3V 1 2
D4 | D3 | D2 | D1 | D0 | OUT VOLTAGE POWER_SIGS PSGND J3 0 | 1 | 0 | 1 | 1 | 1.20V Molex_2_Header_TH
R35B 22Kohms C R40B A TP14 C 8 7 6 5 8 7 6 5 C7 C8 0ohms R39B 10uF 10uF D2 BLK 2 0ohms SCHOTTKY-30V-100mA R37B 11Kohms U2 NC CMPSH-3 8 7 RP7B
10Kohms 2 9 SDN/SKP VCC C DA DB 1 2 3 4 5 17 1 2 3
4 NEG VDD TP1 12 1 ILIM V+ Q1 RPAK_S4_10K, 5% 2 G NP 20 MOSFET_DUAL_FDS6982 YEL OVP TP5
Bourns-CAY16-103J4 13 26 MOSFET__DUAL_FDS6982 POS BST S C90B RED C5 28 DH C26 C28 C81 CORE_VCC 0.22uF 0.1uF 1 L1 11 470uF 470uF 470uF REF
10 27 12 TON LX DVM_D C12
470pF 6
CC 2 1 1 65 Bourns 6.8uH 2 16 C98B DL C C83 C40 C74 DVM_D[0] PSGND 25 DA DB D1 SDR1005-6R8M J4 D0 470uF 470uF 470uF 0.1uF DVM_D[1] 24 15 SCHOTTKY-40V-2.1A D1 GND/PGND Q1 4 G 10MQ040N Molex_2_Header_TH DVM_D[2] 23 R43B MOSFET_DUAL_FDS6982
D2 2 1 1 0ohms A 2 DVM_D[3] 22 19 MOSFET__DUAL_FDS6982 D3 ZMODE S J5 DVM_D[4] 21 18 R38B D4 SUS 3 4 TP3 FB 0ohms Molex_2_Header_TH
NP 7 S0 TIME 3 YEL R42B 8 14 B S1 VGATE 120Kohms B C22
8 7 7 6 6 5 5 8 470uF VCC MAX1718EEI TP2 NP R2 100Kohms YEL RP6B 10Kohms
1 2 3 4 1 2 3 4
CORE_VCC CORE_VCC RPAK_S4_10K, 5% NP Bourns-CAY16-103J4 R31 R8 NP 0ohms 0ohms TP6 NP U5 RED VCC VCC L2 NP 1 5 R14 1 2 PLL_VCC +3.3V IN OUT R47B NP 0ohms 150Kohms C105B Panasonic 4.7uH R13 C126B C106B
NP 2 1uF C23 TP8 C93B 0ohms 4.7uF ELJ-PC4R7MF 0.01uF 0.1uF 33uF place .1uf close to pin R12 BLK
3 TPS77001 4
0.1uF EN FB/NC 1 NP NP NP C159B U3 4 0ohms NP 3 GND VDD D 2 Q2 TPS77001 531 G A MR RESET 2N7002 A 2N7002 S GND1 GND2 2 R10 1 2 VCC_CNTL TPS3801K33 Intel Corp. DCPXA250 Processor Card 0ohms Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 6
REV Project: DCPXA250 Schematic: CORE Supply
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(06;) Fri Oct 11 10:19:07 2002 1234
CPLD BYPASS
+3.3V
D 1 1 D C124B C175B C104B C125B C200B
C112B C66 C110B C119B C75 C35
0.1uF 0.1uF 0.1uF 0.1uF 22uF 22uF 21 21 2 2 1uF 0.015uF 0.015uF 0.015uF 0.015uF
+3.3V 1 C95B C115B C108B C111B C191B
C14 C24 C33 C121B C72 C44
0.1uF 0.1uF 0.1uF 0.1uF 22uF 22uF 21 21 21 2 1uF 0.015uF 0.015uF 0.015uF 0.015uF
VCCN PLANE SPLIT CAPACITANCE
C C VCCN 1 1 1 1 1 1 C179B C127B C145B C140B C116B C167B C204B C192B
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 2 2 2 2 2 2
+3.3V PLANE SPLIT CAPACITANCE
+3.3V 1 1 C62 C55 C43 C31 C80 C34 C67 C59
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 21 21 B 2 2 B
BULK CAPACITANCE
VCC +3.3V
C6 C41 C82 1uF 1uF 1uF
C63 C13 C15 4.7uF 4.7uF 4.7uF
A A
C18 C38 C1 C10 22uF 22uF 22uF 22uF Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 7
REV Project: DCPXA250 Schematic: CORE CNTL
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(07;) Fri Oct 11 10:19:07 2002 1234
D D
RP15B IXM_ADDR[24] 8 9 IMX_ADDRST[24]
RP15B IXM_ADDR[23] 215 IMX_ADDRST[23]
RP15B IXM_ADDR[22] 7 10 IMX_ADDRST[22]
RP15B IXM_ADDR[21] 6 11 IMX_ADDRST[21]
RP15B IXM_ADDR[20] 512 IMX_ADDRST[20]
RP15B IXM_ADDR[19] 413 IMX_ADDRST[19]
RP13B IXM_ADDR[18] 89 IMX_ADDRST[18]
22ohms RP13B IXM_ADDR[17] 710 IMX_ADDRST[17]
RP13B IXM_ADDR[16] 611 IMX_ADDRST[16]
RP13B IXM_ADDR[15] 512 IMX_ADDRST[15]
RP15B IXM_ADDR[14] 116 IMX_ADDRST[14]
RP13B C IXM_ADDR[13] 314 IMX_ADDRST[13] C
RP13B IXM_ADDR[12] 413 IMX_ADDRST[12]
RP13B IXM_ADDR[11] 1 16 IMX_ADDRST[11]
RP12B IXM_ADDR[10] 89 IMX_ADDRST[10]
22ohms
RP12B IXM_ADDR[9] 710 IMX_ADDRST[9]
RP13B IXM_ADDR[8] 2 15 IMX_ADDRST[8]
RP12B IXM_ADDR[7] 4 13 IMX_ADDRST[7]
RP12B IXM_ADDR[6] 5 12 IMX_ADDRST[6]
RP12B IXM_ADDR[5] 314 IMX_ADDRST[5]
RP12B IXM_ADDR[4] 611 IMX_ADDRST[4]
RP12B IXM_ADDR[3] 116 IMX_ADDRST[3]
RP12B IXM_ADDR[2] 215 IMX_ADDRST[2]
B B
R60B IXM_ADDR[1] 1 2 IMX_ADDRST[1]
22ohms
R58B IXM_ADDR[0] 1 2 IMX_ADDRST[0]
22ohms
22ohms
RP15B IXM_ADDR[25] 314 IMX_ADDRST[25] IXM_ADDR
IXM_ADDRST
A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 8
REV Project: DCPXA250 Schematic: Address Terminators
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(08;) Fri Oct 11 10:19:07 2002 1234
D D
1mohms RP16B 1mohms RP17B IXM_DATA[31] 8 9 IXM_DATAST[31] IXM_DATA[15] 6 11 IXM_DATAST[15]
RP17B RP16B IXM_DATA[30] 7 10 IXM_DATAST[30] IXM_DATA[14] 5 12 IXM_DATAST[14]
RP17B RP16B IXM_DATA[29] 4 13 IXM_DATAST[29] IXM_DATA[13] 7 10 IXM_DATAST[13]
RP16B RP17B IXM_DATA[28] 6 11 IXM_DATAST[28] IXM_DATA[12] 8 9 IXM_DATAST[12]
RP17B RP16B IXM_DATA[27] 2 15 IXM_DATAST[27] IXM_DATA[11] 4 13 IXM_DATAST[11]
RP16B RP17B IXM_DATA[26] 2 15 IXM_DATAST[26] IXM_DATA[10] 314 IXM_DATAST[10]
RP17B RP16B IXM_DATA[25] 1 16 IXM_DATAST[25] IXM_DATA[9] 3 14 IXM_DATAST[9]
RP19B RP17B IXM_DATA[24] 8 9 IXM_DATAST[24] IXM_DATA[8] 5 12 IXM_DATAST[8]
1mohms RP18B IXM_DATA[7] 89 IXM_DATAST[7] 1mohms RP19B RP19B IXM_DATA[23] 6 11 IXM_DATAST[23] IXM_DATA[6] 7 10 IXM_DATAST[6]
RP19B RP16B C IXM_DATA[22] 2 15 IXM_DATAST[22] IXM_DATA[5] 1 16 IXM_DATAST[5] C
RP19B RP18B IXM_DATA[21] 3 14 IXM_DATAST[21] IXM_DATA[4] 6 11 IXM_DATAST[4]
RP18B RP18B IXM_DATA[20] 3 14 IXM_DATAST[20] IXM_DATA[3] 7 10 IXM_DATAST[3]
RP18B RP18B IXM_DATA[19] 1 16 IXM_DATAST[19] IXM_DATA[2] 4 13 IXM_DATAST[2]
RP18B RP18B IXM_DATA[18] 2 15 IXM_DATAST[18] IXM_DATA[1] 5 12 IXM_DATAST[1]
RP19B RP19B IXM_DATA[17] 4 13 IXM_DATAST[17] IXM_DATA[0] 5 12 IXM_DATAST[0]
RP19B IXM_DATA[16] 1 16 IXM_DATAST[16]
IXM_DATA
B B IXM_DATAST
A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 9
REV Project: DCPXA250 Schematic: Data Bus Terminators
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(09;) Fri Oct 11 10:19:07 2002 1234
RP14B 1mohms D nPOE 512 nPOE_ST D
RP9B 1mohms nPWE 116 nPWE_ST
RP14B 1mohms RP11B 1mohms nCS5 3 14 nCS5_ST nSDCS0 5 12 nSDCS0_ST
RP14B 1mohms RP9B 1mohms nCS4 413 nCS4_ST nSDCS1 314 nSDCS1_ST
RP14B 1mohms RP11B 1mohms nCS3 215 nCS3_ST nSDCS2 8 9 nSDCS2_ST
RP14B 1mohms RP11B 1mohms nCS2 611 nCS2_ST nSDCS3 4 13 nSDCS3_ST
RP14B 1mohms C nCS1 1 16 nCS1_ST RP11B 1mohms C nSDCAS 3 14 nSDCAS_ST RP14B 1mohms nCS0 710 nCS0_ST RP11B 1mohms nSDRAS 2 15 nSDRAS_ST
RP9B 1mohms SDCKE0 512 SDCKE0_ST
RP9B 1mohms SDCKE1 413 SDCKE1_ST
R53B SDCLK1 12 SDCLK1_ST
0ohms
RP9B 1mohms RD/nWR 710 RD/nWR_ST R54B RP11B 1mohms SDCLK0 1 2 SDCLK0_ST nOE 6 11 nOE_ST 22ohms RP11B 1mohms nWE 7 10 nWE_ST R55B SDCLK2 1 2 SDCLK2_ST
22ohms
22ohms B R67 B DQM0 12 DQM0_ST RP10B
22ohms 1 8
RP11B 1mohms 2 7 DQM1 1 16 DQM1_ST DREQ1 3 6 DREQ1_ST RP9B 1mohms DQM2 8 9 DQM2_ST DREQ0 4 5 DREQ0_ST
RP9B 1mohms DQM3 611 DQM3_ST RPAK_S4_22, 5% Bourns-CAY16-220J4
IXM_CNTL
IXM_CNTLST
A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 10
REV Project: DCPXA250 Schematic: CNTL Terminators
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(10;) Fri Oct 11 10:19:07 2002 1234
DATA BUFFERS ADDRESS BUFFERS
D IXM_DATASTB D
IXM_ADDRST IXM_ADDRSTB CPLD_BUS
IXM_DATAST U19B U7 74LVCH16245A 74LVCH16245A
DATA_DIR 1 ADDR_DIR 1 1ATOB 1ATOB DATA_OE 48 ADDR_OE 48 1OE 1OE
IXM_DATAST[31] 2 47 IXM_DATASTB[31] IMX_ADDRST[25] 2 47 IMX_ADDRSTB[25] 1B1 1A1 1B1 1A1 IXM_DATAST[30] 3 46 IXM_DATASTB[30] IMX_ADDRST[24] 3 46 IMX_ADDRSTB[24] 1B2 1A2 1B2 1A2 IXM_DATAST[29] 5 44 IXM_DATASTB[29] IMX_ADDRST[23] 5 44 IMX_ADDRSTB[23] 1B3 1A3 1B3 1A3 IXM_DATAST[28] 6 43 IXM_DATASTB[28] IMX_ADDRST[22] 643IMX_ADDRSTB[22] 1B4 1A4 1B4 1A4 IXM_DATAST[27] 8 41 IXM_DATASTB[27] IMX_ADDRST[21] 841IMX_ADDRSTB[21] 1B5 1A5 1B5 1A5 IXM_DATAST[26] 9 40 IXM_DATASTB[26] IMX_ADDRST[20] 940IMX_ADDRSTB[20] 1B6 1A6 1B6 1A6 SN74LVCH16245ADGG IXM_DATAST[25] 11 SN74LVCH16245ADGG 38 IXM_DATASTB[25] IMX_ADDRST[19] 11 38 IMX_ADDRSTB[19] 1B7 1A7 1B7 1A7 IXM_DATAST[24] 12 37 IXM_DATASTB[24] IMX_ADDRST[18] 12 37 IMX_ADDRSTB[18] 1B8 1A8 1B8 1A8
IXM_DATAST[23] 13 36 IXM_DATASTB[23] IMX_ADDRST[17] 13 36 IMX_ADDRSTB[17] 2B1 2A1 2B1 2A1 IXM_DATAST[22] 14 35 IXM_DATASTB[22] IMX_ADDRST[16] 14 35 IMX_ADDRSTB[16] 2B2 2A2 2B2 2A2 IXM_DATAST[21] 16 33 IXM_DATASTB[21] IMX_ADDRST[15] 16 33 IMX_ADDRSTB[15] 2B3 2A3 2B3 2A3 IXM_DATAST[20] 17 32 IXM_DATASTB[20] IMX_ADDRST[14] 17 32 IMX_ADDRSTB[14] 2B4 2A4 2B4 2A4 IXM_DATAST[19] 19 30 IXM_DATASTB[19] IMX_ADDRST[13] 19 30 IMX_ADDRSTB[13] C 2B5 2A5 2B5 2A5 C IXM_DATAST[18] 20 29 IXM_DATASTB[18] IMX_ADDRST[12] 20 29 IMX_ADDRSTB[12] 2B6 2A6 2B6 2A6 IXM_DATAST[17] 22 27 IXM_DATASTB[17] IMX_ADDRST[11] 22 27 IMX_ADDRSTB[11] 2B7 2A7 2B7 2A7 IXM_DATAST[16] 23 26 IXM_DATASTB[16] IMX_ADDRST[10] 23 26 IMX_ADDRSTB[10] 2B8 2A8 2B8 2A8
DATA_DIR 24 ADDR_DIR 24 2ATOB 2ATOB DATA_OE 25 ADDR_OE 25 2OE 2OE TSSOP-48 TSSOP-48 LVCH16245A_DGG LVCH16245A_DGG U9 U17B 74LVCH16245A 74LVCH16245A
DATA_DIR 1 ADDR_DIR 1 1ATOB 1ATOB DATA_OE 48 ADDR_OE 48 1OE 1OE
IXM_DATAST[15] 247IXM_DATASTB[15] IMX_ADDRST[9] 2 47 IMX_ADDRSTB[9] 1B1 1A1 1B1 1A1 IXM_DATAST[14] 346IXM_DATASTB[14] IMX_ADDRST[8] 3 46 IMX_ADDRSTB[8] 1B2 1A2 1B2 1A2 IXM_DATAST[13] 544IXM_DATASTB[13] IMX_ADDRST[7] 5 44 IMX_ADDRSTB[7] 1B3 1A3 1B3 1A3 IXM_DATAST[12] 643IXM_DATASTB[12] IMX_ADDRST[6] 6 43 IMX_ADDRSTB[6] 1B4 1A4 1B4 1A4 IXM_DATAST[11] 841IXM_DATASTB[11] IMX_ADDRST[5] 8 41 IMX_ADDRSTB[5] 1B5 1A5 1B5 1A5 IXM_DATAST[10] 940IXM_DATASTB[10] IMX_ADDRST[4] 9 40 IMX_ADDRSTB[4] 1B6 1A6 1B6 1A6 SN74LVCH16245ADGG IXM_DATAST[9] 11SN74LVCH16245ADGG 38 IXM_DATASTB[9] IMX_ADDRST[3] 11 38 IMX_ADDRSTB[3] 1B7 1A7 1B7 1A7 IXM_DATAST[8] 12 37 IXM_DATASTB[8] IMX_ADDRST[2] 12 37 IMX_ADDRSTB[2] 1B8 1A8 1B8 1A8
IXM_DATAST[7] 13 36 IXM_DATASTB[7] IMX_ADDRST[1] 13 36 IMX_ADDRSTB[1] B 2B1 2A1 2B1 2A1 B IXM_DATAST[6] 14 35 IXM_DATASTB[6] IMX_ADDRST[0] 14 35 IMX_ADDRSTB[0] 2B2 2A2 2B2 2A2 IXM_DATAST[5] 16 33 IXM_DATASTB[5] 16 33 2B3 2A3 2B3 2A3 IXM_DATAST[4] 17 32 IXM_DATASTB[4] 17 32 2B4 2A4 2B4 2A4 IXM_DATAST[3] 19 30 IXM_DATASTB[3] 19 30 2B5 2A5 2B5 2A5 IXM_DATAST[2] 20 29 IXM_DATASTB[2] 20 29 2B6 2A6 2B6 2A6 IXM_DATAST[1] 22 27 IXM_DATASTB[1] 22 27 2B7 2A7 2B7 2A7 IXM_DATAST[0] 23 26 IXM_DATASTB[0] 23 26 2B8 2A8 2B8 2A8
DATA_DIR 24 ADDR_DIR 24 2ATOB 2ATOB DATA_OE 25 ADDR_OE 25 2OE 2OE TSSOP-48 TSSOP-48 LVCH16245A_DGG LVCH16245A_DGG
+3.3V +3.3V +3.3V 1 1 1 C142B C197B C49 C47 1 C48 C70 C51 C147B 0.1uF 0.1uF 0.1uF 0.1uF C30 C146B C71 C64 21 2 2 2 0.015uF 0.015uF 0.015uF 0.015uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 2 A A
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 11
REV Project: DCPXA250 Schematic: Memory Bus Transceivers
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(11;) Fri Oct 11 10:19:07 2002 1234
CONTROL BUFFERS
D IXM_CNTLSTB D
IXM_CNTLST
CPLD_BUS U6 74LVCH16245A
CNTL_DIR 1 1ATOB U13 CNTL_OE 48 1OE 74LVCH16245A
IXM_CNTL nCS5_ST 2 47 nCS5_STB CNTL_1111_DIR 1 1B1 1A1 1ATOB nCS4_ST 3 46 nCS4_STB CNTL_1111_OE 48 1B2 1A2 1OE nCS3_ST 5 44 nCS3_STB 1A3 1B3 nOE_ST 247nOE_STB 1A1 nCS2_ST 6 43 nCS2_STB 1B1 1A4 1B4 nWE_ST 346nWE_STB 1A2 nCS1_BS 8 41 nCS1_STB 1B2 1B5 1A5 544 9 40 1B3 1A3 nCS0_BS nCS0_STB R66B 1B6 1A6 12 37 SDCLK1_ST 12SDCLK1_STR SDCLK1_STB 11 SN74LVCH16245ADGG 38 1B4 1A4 1B7 1A7 841 33ohms 12 37 1B5 1A5 1B8 1A8 940 1B6 1A6
11SN74LVCH16245ADGG 38 1B7 1A7 RD/nWR_ST 13 36 RD/nWR_STB 2B1 2A1 643 14 35 1B8 1A8 2B2 2A2 nPOE_ST 16 33 nPOE_STB 2B3 2A3 DQM0_ST 13 36 DQM0_STB 17 32 2B1 2A1 2B4 2A4 DQM1_ST 14 35 DQM1_STB 2B2 2A2 nPWE_ST 19 30 nPWE_STB 2B5 2A5 DQM2_ST 16 33 DQM2_STB C 20 29 2B3 2A3 C 2B6 2A6 DQM3_ST 17 32 DQM3_STB 2B4 2A4 nSDCS3_ST 22 27 nSDCS3_STB 2B7 2A7 nSDCS0_ST 19 30 nSDCS0_STB 2B5 2A5 nSDCS2_ST 23 26 nSDCS2_STB 2B8 2A8 nSDCAS_ST 20 29 nSDCAS_STB 2B6 2A6 CNTL_DIR 24 nSDRAS_ST 22 27 nSDRAS_STB 2ATOB 2B7 2A7 CNTL_OE 25 23 26 2OE 2B8 2A8 TSSOP-48 CNTL_1111_DIR 24 LVCH16245A_DGG 2ATOB CNTL_1111_OE 25 2OE TSSOP-48 LVCH16245A_DGG
U15B 74LVCH16245A
CNTL_DIR 1 1ATOB CNTL_OE 48 1OE
nSDCS1_ST 2 47 nSDCS1_STB 1B1 1A1 SDCKE1_ST 3 46 SDCKE1_STB 1B2 1A2 SDCKE0_ST 5 44 SDCKE0_STB 1B3 1A3 DREQ1_ST 643DREQ1_STB 1B4 1A4 DREQ0_ST 8 41 DREQ0_STB 1B5 1A5 B 9 40 B 1B6 1A6
11 SN74LVCH16245ADGG 38 1B7 1A7 12 37 1B8 1A8
13 36 2B1 2A1 SDCLK2_ST 14 35 SDCLK2_STB 2B2 2A2 SDCLK0_ST 16 33 SDCLK0_STB 2B3 2A3 17 32 2B4 2A4 19 30 2B5 2A5 20 29 2B6 2A6 22 27 2B7 2A7 23 26 2B8 2A8
CNTL_DIR 24 2ATOB CNTL_OE 25 2OE TSSOP-48 LVCH16245A_DGG
+3.3V +3.3V +3.3V 1 1 A C85 C187B C207B C29 A C182B C206B C69 C141B C94B C101B C203B C52
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 21 21 21 2 2 0.015uF 0.015uF 0.015uF 0.015uF
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 12
REV Project: DCPXA250 Schematic: CNTL Transceivers
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(12;) Fri Oct 11 10:19:07 2002 1234
BB=BASE BOARD 3 3 2 4 4
+3.3V DC=DAUGHTER CARD S1 S2 CS1 CS0 RP2B RP2B +3.3V 4.7Kohms 4.7Kohms RP4B RP4B RP4B RP4B 10Kohms 10Kohms 10Kohms 10Kohms 4.7Kohms RP2B 12 5 16 1 15 13 13 U16B 14 14 U16B 00 BB BB 4.7Kohms 11 6 11 10 3 4 RP8B DOT=1 DOT NO DOT 4.7Kohms SN74CBT3125DBQR SN74CBT3125DBQR 01 BB DC 98 NO DOT=0 RP8B 12 2 4.7Kohms +3.3V D S3 NO WP WP 10 7 D 10 DC BB RP8B J1 U16B 4.7Kohms SN74CBT3125DBQR U16B S4 I2C HEX 12 5 1 RP8B 14 13 6 7 11 BB BB 2 S5 RSV RSV SN74CBT3125DBQR TCK_CPLD 3
15 5 TDO_CPLD 4
TDI_CPLD 5
TMS_CPLD 6 nCS0_ST FET_OE[0] nCS1_ST FET_OE[1] nCS0_ST FET_OE[2] nCS1_ST FET_OE[3] FLASH_CS nCS1_BS GPIO_SIGS nCS0_BS Molex_6_Header_TH
IXM_CNTL
DVM_D
IXM_ADDRST
IXM_CNTLST
POWER_SIGS +3.3V U4 Xilinx XPLA3 3128B
S1 IMX_ADDRST[25] 1 56 DVM_D[4] TP9 IOE0 IOG0 4.7Kohms RP2B 3 GP21 143 55 DVM_D[3]
11 6 IOE1 IOG1 1 YEL 2 GP22 142 54 DVM_D[2] FLASH SELECT 0 IOE2 IOG2
+3.3V FET_OE[0] 141 53 DVM_D[1] IOE3 IOG3 FET_OE[1] 140 46 DVM_D[0] SPDT_1K2 IOE4 IOG4 1 3 2 5 6 7 8 4 FET_OE[2] 139 45 C 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms S2 IOE5 IOG5 C FET_OE[3] 138 44 IOE6 IOG6 3 RP5B RP5B RP5B RP5B RP5B RP5B RP5B RP5B U4 1 9 137 42 GP14 11 16 15 12 10 13 14 IOE10 IOG10 2 FLASH SELECT 1 106 90 136 41 GP13 IOA0 IOC0 IOE11 IOG11 104 89 134 40 GP2 IOA1/TDO IOC1/TCK SPDT_1K2 IOE12 IOG12 PWR_EN 102 88 133 39 GP3 IOA2 IOC2 IOE13 IOG13 nRESET 101 87 S3 132 38 GP4 IOA3 IOC3 IOE14 IOG14 DATA_DIR ADDR_DIR DATA_OE ADDR_OE CNTL_DIR CNTL_OE CNTL_1111_DIR CNTL_1111_OE 100 86 3 131 37 GP5 IOA4 IOC4 IOE15 IOG15 1 CNTL_1111_OE 99 84 2 IOA5 IOC5 WRITE PROTECT CNTL_1111_DIR 98 83 nCS5_ST 2 18 IOA6 IOC6 IOF0 IOH0 CNTL_OE 97 82 4 20 +3.3V IOA10 IOC10 SPDT_1K2 IOF1/TDI IOH1/TMS +3.3V +3.3V CNTL_DIR 96 81 nCS4_ST 5 21 IOA11 IOC11 IOF2 IOH2 S4 nRP DATA_OE 94 80 nCS3_ST 6 22 IOA12 IOC12 IOF3 IOH3 3 nWP 8 8 7 7 6 6 5 5 DATA_DIR 93 79 1 nCS2_ST 7 23 IOA13 IOC13 IOF4 IOH4
2 SWITCH VS. I2C XCR3128XL-7TQ144C-B VPEN
2 ADDR_OE 92 78 nCS1_ST 8 25 IOA14 IOC14 IOF5 IOH5 ADDR_DIR 91 77 nCS0_ST 9 26 IOA15 IOC15 IOF6 IOH6 10Kohms 10Kohms 10Kohms 10Kohms 10Kohms 10Kohms 10Kohms 10Kohms RP1 C84 0.1uF SPDT_1K2 1 1 6 3 8 7 2 4 nOE_ST 10Kohms 10 27 IOF10 IOH10
1 2 3 4 107 60 S5 nWE_ST 11 28 nSDCS0_ST IOB0 IOD0 IOF11 IOH11 U14B 109 61 3 nPWE_ST 12 29 DQM3_ST RP3B RP3B RP3B RP3B RP3B RP3B RP3B RP3B IOB1 IOD1 IOF12 IOH12 1 9 11 12 5 16 10 15 13 14 110 62 2 RESERVED RD/nWR_ST 14 30 DQM2_ST R3 IOB2 IOD2 IOF13 IOH13 16 111 63 nPCE1 15 31 DQM1_ST V+ IOB3 IOD3 IOF14 IOH14 0ohms 13 112 65 nPCE2 16 32 DQM0_ST ALERT IOB4 IOD4 SPDT_1K2 IOF15 IOH15
B XCR3128XL-7TQ144C-B B
PERIPH_SIGS SDA 12 1 113 66 SMBDATA IO0 IOB5 IOD5 RP4B SCL 14 2 114 67 126 125 SMBCLK IO1 IOB6 IOD6 CLK2/IN2 CLK3/IN3 710 10Kohms 15 3 116 68 13 R4 SMBSUS IO2 IOB10 IOD10 PE 4 117 69 IO3 IOB11 IOD11 RP4B 11 0ohms ADD1 89 5 118 70 IO4 IOB12 IOD12 10Kohms R5 10 ADD0 6 119 71 IO5 IOB13 IOD13 +3.3V RP4B 0ohms U4 611 7 120 72 IO6 IOB14 IOD14 10Kohms 9 GND 8 121 74 24 3 IO7 IOB15 IOD15 VCC_1 GND_1 50 17 VCC_2 GND_2 127 MAX1608EEE CLK1/IN1 128 51 33 address=0010 100 CLK0/IN0 VCC_3 GND_3 58 52 VCC_4 GND_4 CPLD_BUS Xilinx XPLA3 3128B 73 57 VCC_5 GND_5
76 59 VCC_6 GND_6 +3.3V 95 64 VCC_CNTL RP4B +3.3V VCC_7 GND_7
10Kohms 115 85 VCC_SPLY 512 VCC_8 GND_8 123 105 C123B TP7 VCC_9 GND_9 130 124 U8 0.1uF VCC_10 GND_10 C156B
12 0.01uF YEL
8 7 144 129 VCC_11 GND_11 SMD_OSC_3.6864 MHz 135 GND_12 1 4 RP2B RP2B RP2B CE VCC RP2B 19 S6 NC_1 9 1516 2 1 R56B 10 HEX_ROTARY 34 49 56ohms NC_2 NC_8 2 3 CLK0_ST GND OUT 35 75 A 1 NC_3 NC_9 A 0 XCR3128XL-7TQ144C-B 1 F H1 2 E 36 103 5 2 NC_4 NC_10 3 D C H2 43 108 NC_5 NC_11 ECS-3953M-036 R27 4 C 3 5 B H4 47 122 56ohms NC_6 NC_12 OSC_PEXTAL 6 A 4 7 8 9 H8 48 Intel Corp. DCPXA250 Processor Card NC_7
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 13
NKK-DRSC16P Xilinx XPLA3 3128B REV 4.7Kohms 4.7Kohms 4.7Kohms 4.7Kohms Project: DCPXA250 Schematic: CPLD & JTAG
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C:\projects\dcpxa250_F\dcpxa250.sbk(13;) Fri Oct 11 10:19:07 2002 1234
IXM_DATAST
IXM_ADDRST U11 U18B
IMX_ADDRST[25] H8 A24 FLASH_8Mx16 IMX_ADDRST[25] H8 A24 FLASH_8Mx16
IMX_ADDRST[24] G1 A23 E7 IXM_DATAST[15] IMX_ADDRST[24] G1 A23 E7 IXM_DATAST[31] D15 D15 IMX_ADDRST[23] A8 A22 G7 IXM_DATAST[14] IMX_ADDRST[23] A8 A22 G7 IXM_DATAST[30] D D14 D14 D IMX_ADDRST[22] C8 A21 H5 IXM_DATAST[13] IMX_ADDRST[22] C8 A21 H5 IXM_DATAST[29] D13 D13 IMX_ADDRST[21] C7 F5 IXM_DATAST[12] IMX_ADDRST[21] C7 A20 F5 IXM_DATAST[28] A20 D12 D12 IMX_ADDRST[20] B7 F4 IXM_DATAST[11] IMX_ADDRST[20] B7 F4 IXM_DATAST[27] A19 D11 A19 D11 IMX_ADDRST[19] A7 F3 IXM_DATAST[10] IMX_ADDRST[19] A7 F3 IXM_DATAST[26] A18 D10 A18 D10 IMX_ADDRST[18] D8 E3 IXM_DATAST[9] IMX_ADDRST[18] D8 E3 IXM_DATAST[25] A17 D9 A17 D9 IMX_ADDRST[17] D7 E1 IXM_DATAST[8] IMX_ADDRST[17] D7 E1 IXM_DATAST[24] A16 D8 A16 D8 IMX_ADDRST[16] C5 H7 IXM_DATAST[7] IMX_ADDRST[16] C5 H7 IXM_DATAST[23] A15 D7 A15 D7 IMX_ADDRST[15] B5 G6 IXM_DATAST[6] IMX_ADDRST[15] B5 G6 IXM_DATAST[22] A14 D6 A14 D6 IMX_ADDRST[14] A5 G5 IXM_DATAST[5] IMX_ADDRST[14] A5 G5 IXM_DATAST[21] A13 D5 A13 D5 IMX_ADDRST[13] C4 E5 IXM_DATAST[4] IMX_ADDRST[13] C4 E5 IXM_DATAST[20] A12 D4 A12 D4 IMX_ADDRST[12] D3 E4 IXM_DATAST[3] IMX_ADDRST[12] D3 E4 IXM_DATAST[19] A11 D3 A11 D3 +3.3V IMX_ADDRST[11] C3 G3 IXM_DATAST[2] IMX_ADDRST[11] C3 G3 IXM_DATAST[18] A10 D2 A10 D2 IMX_ADDRST[10] B3 E2 IXM_DATAST[1] IMX_ADDRST[10] B3 E2 IXM_DATAST[17] A9 D1 A9 D1 +3.3V IMX_ADDRST[9] A3 F2 IXM_DATAST[0] IMX_ADDRST[9] A3 F2 IXM_DATAST[16] A8 D0 R65B A8 D0 IMX_ADDRST[8] C2 4.7Kohms IMX_ADDRST[8] C2 A7 A7 IMX_ADDRST[7] A2 IMX_ADDRST[7] A2 A6 E8 A6 E8 R15 +3.3V STS STS IMX_ADDRST[6] D2 IMX_ADDRST[6] D2 4.7Kohms A5 A5 IMX_ADDRST[5] D1 IMX_ADDRST[5] D1 A4 B6 A4 B6 DU1/NC DU1/NC IMX_ADDRST[4] C1 PLACE CLOSE TO FLASH IMX_ADDRST[4] C1 A3 +3.3V A3 +3.3V 1 C6 C6 nWPR 0ohms 28F128_STRATA_EASY 28F128_STRATA_EASY DU2/nWP DU2/nWP IMX_ADDRST[3] B1 R28 IMX_ADDRST[3] B1 R24 A2 A2 D5 VDDQ_1 1 2 0ohms D5 VDDQ_2 120ohms IMX_ADDRST[2] A1 DU3/VDDQ IMX_ADDRST[2] A1 DU3/VDDQ R26 A1 D6 A1 D6 G2 DU4/VDDQ NP G2 DU4/VDDQ NP C 2 A0 A0 C +3.3V +3.3V H2 DU8/VSSQ H2 DU8/VSSQ PLACE CLOSE TO FLASH G4 G4 VDDQ VDDQ D4 nRST/nRP D4 nRST/nRP A4 A4 VPEN VPEN NP F1 nBYTE F1 nBYTE SDCLK0_ST R2512 0ohms E6 CLK E6 CLK nSDCAS_ST R3012 0ohms A6 A6 VDD1 VDD1 F6 ADV F6 ADV H3 H3 VDD2 VDD2 NP F7 WAIT F7 WAIT
nOE_ST F8 nOE B2 nOE_ST F8 nOE B2 VSS1 VSS1 nWE_ST G8 nWE H4 nWE_ST G8 nWE H4 VSS2 VSS2 FLASH_CS B4 nCE0 H6 FLASH_CS B4 nCE0 H6 VSS3 VSS3 B8 nCE1 B8 nCE1
H1 H1 nCE2 nCE2 VSSQ_2
VSSQ_1
IXM_CNTLST R32 B 100Kohms B
0ohms 0ohms 0ohms 1
PLACE CLOSE TO FLASH NP NP NP PLACE CLOSE TO FLASH R22 R23 R64B 21 21 2 NP
R52B 1 2 nWP 0ohms RESISTOR J3 FLASH K3 FLASH VPEN
R22 NP P nRP +3.3V +3.3V R23 NP P
R24 NP P 1 R25 NP P C193B C45 C186B C42 C56 C53 C180B C181B
0.1uF 0.1uF 0.1uF 0.1uF 21 21 21 R26 P NP 2 0.015uF 0.015uF 0.015uF 0.015uF
R28 NP P
R30 NP P A A R52B NP P
R64B NP P
Intel Corp. DCPXA250 Processor Card
Date: 28Mar02 Engineer: BAUER/BOAZ/JOVEL Sheet 14
REV Project: DCPXA250 Schematic: STRATAFLASH
1 2 3 4
C:\projects\dcpxa250_F\dcpxa250.sbk(14;) Fri Oct 11 10:19:07 2002