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M3000 Instruction Set Manual Change Log INSTRUCTION SET M3000 Instruction Set Manual Change Log Date Revision Changes 08/07/2007 R080707 Initial Release The information in this book has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. System Semiconductor, reserves the right to make changes without further notice to any products herein to improve reliability, function or design. System Semiconductor does not assume any liability arising out of the application or use of any product or circuit described herein in accordance with System Semiconductor’s standard warranty; neither does it convey any license under its patent TM rights of others. System Semiconductor SYSTEM and SSI are trademarks of System Semiconductor SEMICONDUCTOR inc. System Semiconductor’s general policy does not recommend the use of its products in life support or aircraft applications wherein a failure or malfunction of the product may directly threaten life or injury. Per System Semiconductor’s terms and conditions of sales, the user of System Semiconductor, products in life support or aircraft applications assumes all risks of such use and indemnifies System Semiconductor, against all damages. M3000 Motor and Motion Controller Instruction Set Revision R080707 Copyright © 2007 System Semiconductor, Inc. All Rights Reserved TM M3000 Section 1: Addressing Modes .............................................................................1 The Program and Data Addressing Modes ....................................................................1 Register Direct, Single Register Rd ...............................................................................1 Register Direct, Two Registers Rd and Rr .....................................................................1 I/O Direct .................................................................................................................2 Data Direct ...............................................................................................................2 Data Indirect with Displacement ................................................................................2 Data Indirect Addressing ............................................................................................3 Data Indirect with Pre-decrement ...............................................................................3 Data Indirect with Post-increment ..............................................................................3 Constant Addressing Using the LPM, ELPM, and SPM Instructions.............................4 Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction ...4 Direct Program Addressing, JMP and CALL ...............................................................4 Indirect Program Addressing, IJMP and ICALL ..........................................................5 Relative Program Addressing, RJMP and RCALL ........................................................5 Section 2: Instruction Set Nomenclature ...........................................................6 Status Register ............................................................................................................6 Registers and Operands ...............................................................................................6 I/O Registers ..............................................................................................................6 Stack .........................................................................................................................6 Flags .........................................................................................................................6 Section 3: Complete Instruction Set Summary ..................................................7 Arithmetic and Logic Instructions .................................................................................7 MCU Control Instructions ...........................................................................................7 Branch Instructions .......................................................................................................8 Data Transfer Instructions .............................................................................................9 Bit and Bit-Test Instructions .......................................................................................10 Conditional Branch Summary .....................................................................................10 Section 4: Instruction Set Details ....................................................................11 ADC – Add with Carry ...............................................................................................11 ADC – Add without Carry ..........................................................................................12 ADIW – Add Immediate to Word ...............................................................................13 AND – Logical AND ..................................................................................................14 ANDI – Logical AND with Immediate .......................................................................15 ASR – Arithmetic Shift Right ......................................................................................16 BCLR – Bit Clear in SREG .........................................................................................17 BLD – Bit Load from the T Flag in SREG to a Bit in Register ....................................17 BRBC – Branch if Bit in SREG is Cleared ..................................................................18 BRBS – Branch if Bit in SREG is Set ..........................................................................18 BRCC – Branch if Carry Cleared ................................................................................19 BRCS – Branch if Carry Set ........................................................................................19 BREAK – Break ..........................................................................................................20 BREQ – Branch if Equal .............................................................................................20 BRGE – Branch if Greater or Equal (Signed) ..............................................................21 BRHC – Branch if Half Carry Flag is Cleared ............................................................21 BRHS – Branch if Half Carry Flag is Set .....................................................................22 BRID – Branch if Global Interrupt is Disabled ...........................................................22 BRIE – Branch if Global Interrupt is Enabled .............................................................23 BRLO – Branch if Lower (Unsigned) ..........................................................................23 BRLT – Branch if Less Than (Signed) .........................................................................24 BRMI – Branch if Minus ............................................................................................24 BRNE – Branch if Not Equal ......................................................................................25 BRPL – Branch if Plus ................................................................................................25 BRSH – Branch if Same or Higher (Unsigned) ...........................................................26 BRTC – Branch if the T Flag is Cleared ......................................................................26 BRTS – Branch if the T Flag is Set ..............................................................................27 TM SYSTEM SEMICONDUCTOR inc. M3000 Instruction Set, Revision R080707 i TM M3000 BRVC – Branch if Overflow Cleared ...........................................................................27 BRVS – Branch if Overflow Set ...................................................................................28 BSET – Bit Set in SREG .............................................................................................29 BST – Bit Store from Bit in Register to T Flag in SREG .............................................29 CALL – Long Call to a Subroutine .............................................................................30 CBI – Clear Bit in I/O Register ...................................................................................30 CBR – Clear Bits in Register .......................................................................................31 CLC – Clear Carry Flag ..............................................................................................31 CLH – Clear Half Carry Flag ......................................................................................32 CLI – Clear Global Interrupt Flag ...............................................................................32 CLN – Clear Negative Flag .........................................................................................33 CLR – Clear Register ..................................................................................................33 CLS – Clear Signed Flag .............................................................................................34 CLT – Clear T Flag .....................................................................................................34 CLV – Clear Overflow Flag .........................................................................................35 CLZ – Clear Zero Flag ................................................................................................35
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