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N O T I C E This Document Has Been Reproduced From N O T I C E THIS DOCUMENT HAS BEEN REPRODUCED FROM MICROFICHE. ALTHOUGH IT IS RECOGNIZED THAT CERTAIN PORTIONS ARE ILLEGIBLE, IT IS BEING RELEASED IN THE INTEREST OF MAKING AVAILABLE AS MUCH INFORMATION AS POSSIBLE r^i 44 The University of Tennessee Department of Electrical Engineering Knoxville, Tennessee 37916 (NASA-C,9-1bu791) A SIULY OF LNIYEASA.I N82--2! MODULATICN TECHN101 S APPL11 D TO SA?ELLI;TE 4 DATA COLLECTION Final Report (Tennessee tFn v.) 176 p HC A09/MF A01 CSCL 1711 Uncla G3/32 21917 A STUDY OF UNIVERSAL MODULATION TECHNIQUES APPLIED TO SATELLITE DATA COLLECTION If ^^ tit Final Report Y December 1980 Contract No. NAS5-24250 Prepared for National Aeronautics and Space Administration Goddard Space Flight Center r Greenbelt, Maryland 20771 f i PRECEDING PAGE BLANK NOT FILMED .Osp* Abstract A scheme for a universal modulation and frequency control system for use with data-collection platform (DCP) transmitters is examined. The final design discussed can, under software/firmwave control, generate all of the specific digital data modulation formats currently used in the NASA satellite data-collection service and can simultaneously synthesize the proper RF carrier frequencies employed, A novel technique for DCP time and frequency control is presented, The emissions: of NBS rad o station WW/WWVH are received, detected, and finally decoded in microcomputer software to generate a highly accurate time base for the platform; with the assistance of external hardware, the microcomputer also directs the recalibration of all DCP oscillators to achieve very high frequency accuracies and low drift rates versus tem perature, supply voltage, and time. The final prograwmable DCP design also employs direct microcomputer control of data acquisition, data reduction, formatting, transmitter switching, and system power management, The system hardware and software was described in detail. Finally, future techniques for PDCP design, projected t,wsks for PDCP field units, and the anticipated capab 1 ties of new uni l ts to handle these jobs are presented, T lftt4 u CONTENTS SECTION PAGE 1 INTRODUCTION . 1-1 F 1.1 Background and Purpose . 1-1 r 1.2 Design Philosophy . 1-2 2 DIGITAL OSCILLATOR SYSTEM . 2-1 2.1 System Concepts . 2-1 i 2.2 Digital Oscillator Theory . 2-2 M 2.3 Software Implementations . 2-11 2.3.1 Demonstration Software for 1802 . 2-14 2.3.2 Demonstration Software for 8080A . 2-27 2.4 Hardware Design Considerations . 2-37 2.4.1 Original PDCP/UM Design Parameters . 2-39 i 2.4.2 Modified Hardware Configuration . 2,48 3 MICROPROCESSOR BOARDS . 3-1 3.1 Introduction . 3-1 3.2 CPU Board - uP0 3-4 3.3 CPU Board - uP l 3-7 r 3.4 Expansion Memory Board . 3-10 4 RF BOARD . • . 4.1 Introduction . • . 4-1 4.2 RF Filter/Frequency-Translator Chain . 4-4 4.3 RF Oscillators . 4-6 4.4 WWV Receiving System . 4,12 4.5 Phase-Locked Oscillator System . • • • • 4-13 iv CONTENTS (continued) SECTION PAGE 5 POWER SUPPLY/INTERFACE BOARD . 5-1 5.1 General . , . 50 5.2 Power Supplies . , 5,1 5.2.1 Digital Oscillator Power Supply . 5-2 5,2,2 Dual-Polarity 5-Volt Power Supply and Power Switch . , . , , . 5-4 5,2.3 Microprocessor Power Supplies . , 5-5 5,2,4 RF Board Power Supplies . , . 5-7 5.3 Interface Circuits . 5-9 5.3.1 Standard DCP Transmitter Interface . 5-9 5.3.2 Telephone Audio Interface . 5-12 6 SYSTEM SOFTWARE , . 6-1 6.1 System Perspective . 6-1 6.2 Executive Control Programs for p PO 6-2 6.2.1 Overview . , , , , 6-2 6.2.2 Main/Real-Time Clock Program . 6-5 6.2.3 WWV Time-Decode Routine , , , . 6-17 6.2.4 Event Tim ing/Selection Routine . , , 6-24 6.2.5 Overall Software Timing .. , . 6,26 uP0 6.2.6 System Initialization Program . , . 6-26 6.3 DATA PROCESSING/TRANSMITTING ROUTINES FOR nP 1 . 6-28 6.3.1 Overview . .. 608 6.3.2 PDCP Transmitting Routines . 6-,31 6.3,3 WWV Frequency-Correction Software . , . 6-43 v CONTENTS (continued) SECTION PAGE 7 FUTURE DCP TECHNIQUES . 7R1 7 .1 DCP Design Trends . 7-1 7.2 Technological Trends in DCP Design . 7-6 7.2.1 Digital Integrated Circuit Technology . 7-6 7.2.2 Microcomputer Component Technology . 7 -8 7.2.3 Proposed DCP Simplii^ications . 7-10 7.2.4 Proposed New Integrated Circuits for DCP Use . 7-15 7.2.4.1 Digital Oscillator Chip . 7-15 7.2.4.2 Proposed Thermally-Stabilized Crystal Oscillator Chip . 7-18 7.3 Projections on DCP Designs and Uses . 7-22 7.3-.1 Semiconductor Technology Forecasts . 7-22 7.3.2 Future DCP Uses . 7-24 vi 4 LIST OF FIGURES FIGURE PAGE 2.2.1 Basic Digital Oscillator-Block Diagram 24 2.2.2 Enhanced Digital Oscillator System - Bl ock Diagram . , . 2-8 2,3.1 Basic Flow Chart for 1802 MSK/PSK Demonstration Program . 2-16 2.3.2 Basic Flow Chart for 8080A MSK/PSK De ►nonstration Program . 2-28 3.2 Microprocessor CPU Board (I ► PO ) Block Diagram 3-6 3.3 Microprocessor CPU Board (pP 1 ) Block Diagram 3.8 3.4 Typical .Add-on Memory Board Block Diagram 3-12 4.1 Block Diagram of RF Board . 4,2 4,3 Microprocessor-Based Oscillator AFC System . 4-10 4.5 Black Diagram of Phase-locked Oscillator System 4-15 5,2 Block Diagram of Power Supply System . 5,3 5.2.3 Block Diagram of Micropower +5 Volt Switching Regulator . 51-8 5.3 Block Diagram of Interface Circuitry . , . 5,-10 6.2.1 Program Information Flow . , 6--4 6.2.2.1 Flow Diagram for uP 0 Main Program/Real-Time Clock Routine . 6-8 6.242.2 Flow Diagram for "Load WWV Time Data" Software 6-g 6.2,2.3 Flow Diagram for Time-Update Subroutine 6-12 6.2.3.1 Chart of time code transmissions from NBS radio Ago LIST OF FIGURES (cont.) FIGURE PAGE 6.2.3.2 Flow Diagram for WWV Time-Decode Program . 6-20 6.2.3.3 Flow Diagram for "Decode/Load Data" Routine . 6-22 6.2.4 Flow Diagram for Event Timing/Selection Routine 6-25 6.2.5 Diagram of Relative Software Timing . 6.27 pP0 6.2.6 Flow Diagram for Initialization Program . 6-29 6.3.2.1 A Flow Chart for the NIMBUS-F (TWERL£) Data Transmission Subroutine . 6-33 6.3.2.2 A Flow Chart for the TIROS-N Transmission Subroutine . 6-37 6.3,2.3 A Flow Chart for the GOES Data Transmission Subroutine . 6-40 6,3.3 Flow Diagram for WWV Frequency-Correction Software . 6-45 7.2.1 Coitparision of Digital IC Technologies . 7-7 7.2.3 Simplified Digital Oscillator System Block Diagram . 7-12 7.2.4.1 Proposed Digital Oscillator I.C. , . : . , 7-16 7.2.4.2.1 Block Diagram of Proposed Crystal Oscillator Chi p . , . 7,19 7,2303 General Physical Layout of Proposed Chip . , 7-20 viii __ , _7 0,4 LIST OF TABLES TABLE P 2:.3.1 Microprocessor Speed Comparisons . , . , . 2-13 2.3.2 Restart Locations and Parameters for 8080A Demonstration Software . 2-38 2.4 Basic Requirements for PDCP/UM System . , . , 2-40 2.4.1.1 Current Satellite Standards for DCPs . , 2-41 2.4.1.2 GOES Satellite Channel Frequencies . 2-43 2,4.1,3 Parameters for Original PDCP/UM Configuration . 2-47 2.4.2.1 Parameters for t4odif`ied PDCP/UM Configuration . 2-50 5.3,1 Power Supply/Interface Control Function Decoding 5-11 6-6 6.2.2 Register Assignments for 00 • 6,3.2.1 NIMBUS•-F (TWERLE) data Transmission Sequence Specifications . 6-32 6.3.2.2 TIROS-N Data Transmission Sequence Specifications 6-36 6,3.2.3 GOES Data Transmission Sequence Specifications . 6-39 7.2.3 Parameters for Simplified Digital Oscillators (M S K Mode) . , . , . , . 7-14 7,3.1 Status of Semiconductor Technology . , . 7-23 ix I. INTRODUCTION 1.1 BACKGROUND AND PURPOSE The major impetus for this project was the desire of NASA personnel at Goddard Space Flight Center, particularly Mr. J. Earle Painter, to develop a universally applicable data-collection platform (DCP) which would be capable of acquiring various types of analog and digital data, formatting and storing this information, and then through a standard RF transmitter relaying the digital data stream to an overhead satellite for transmission to a central data receiving stationEl], Perhaps the major difficulty in implementing such a universal data- collection system is the considerable variation from satellite to satellite in their requirements for data bit rates, transmission burst lengths, data formats, modulation parameters, modulation types, and final RF frequencies employed in the DCP-to-satellite uplinks. For this reason DCP's have been implemented for specific satellites only; only through substantial hardware and/or crystal changes (normally done at the depot or factory level) could a platform for a specific satellite be converted for use with another,121.. In addition, the DCPs available at pres- ent are quite costly for the data-collection end-user to purchase, thus precluding many potential DCP users from getting into the field. As a result, satellites are frequently underutilized and their capacity for public service is curtailed. NASA personnel have therefore greatly en- couraged the development of a system which will not only fulfill the operational requirements of a universal DCP but which will be moderate in cost, highly reliable, and simple for the end-user to operate 1-2 44 The system developed by the Electrical Engineering Department at the University of Tennessee meets these requirements by utilizing the vast flexibility of a microprocessor-controlled DCP developed by U-'T for NASA under Contract No.
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