Rc Relaxational Oscillator with High Supply Rejection

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RC RELAXATIONAL OSCILLATOR WITH HIGH SUPPLY REJECTION

TIANYU WANG

THESIS

Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical and Computering Engineering in the Graduate College of the University of Illinois at Urbana-Champaign, 2018

Urbana, Illinois

Adviser:

Professor Pavan Hanumolu

ABSTRACT

A low power RC relaxation oscillator with very low voltage and temperature sensitivities is presented. Supply sensitivity is reduced by using a self-regulation loop that

biases the oscillator near its zero-voltage coefficient point. Fabricated in a 65nm CMOS

process, the prototype 1.5MHz oscillator consumes 6μW from 1V supply and achieves

better than ±50ppm/ ̊C and ±1500ppm/V temperature and voltage sensitivities,

respectively.

ii TABLE OF CONTENTS

Chapter 1: Introduction…………………………………………………………………….1

Chapter 2: Frequency stability of RC oscillators…….…………………..……….3

Chapter 3: Proposed RC oscillator…….………………………………....…………….7

Chapter 4: Experiment result...…….………………………………………………..….12

Chapter 5: Summary…….……………………………...……………..….……………..….16

References………………………………………………………………………………………17

iii Chapter 1.Introduction

RC oscillators have become the de-facto clock generators for time keeping and ultra- low power clock generation in applications such as implantable devices, sensors, radio frequency identification (RFID) devices and micro-controller units (MCUs). Compared to crystal oscillators, they offer attractive tradeoffs in terms of monolithic integration and power, especially in cost sensitive or power constrained applications.

A conceptual block diagram of an RC oscillator is shown in figure 1. When ɸ is logic high (ɸ = 1), Vramp1 is reset to 0V while constant current I charges capacitor C resulting in a ramp voltage at Vramp2 (see figure 1b). When Vramp2 exceeds Vref (= IR), the top comparator output flips to logic low, which causes the SR latch output to go low (i.e. ɸ = 0). This resets the capacitor and pulls Vramp2 to 0V while Vramp1 starts to ramp up. When Vramp1 exceeds

Vref, the SR latch is set and ɸ goes high. This process repeats resulting in an oscillatory output as depicted in figure 1b. The period of oscillation (TOSC) is dictated by the time taken

퐼푅 for Vramp to reach Vref, which is equal to T = = 푅퐶 resulting in TOSC = 2RC. Because the RC 퐼/퐶 frequency of RC oscillators is ideally defined only by the RC time constant, excellent frequency stability can be achieved if R and C are designed to be process and temperature insensitive. In practice, comparator imperfections and other circuit non-idealities degrade frequency stability especially in the presence of voltage and temperature variations as described in chapter 2.

Vramp Vramp2 Vramp1 Vref I I I

vramp2 ɸ ɸ S Q ɸ t ɸ C R Q ɸ vref vramp1 VDD C R

t (a) (b) Figure 1: RC oscillator schematic and its waveforms.

Chapter 2. Frequency stability of RC oscillators

The typical error sources that affect frequency stability are: aging (10 years, 100% duty cycle at 85°C), trim accuracy, temperature (-40 to 85 °C), and supply voltage (>300mV).

Across different technologies, it is fair to assume that aging could cause up to 0.5% of frequency shift, and temperature could also contribute about 0.5% error, then it leaves no margin for voltage-induced frequency variation. Under this situation, the system will need to periodically recalibrate the oscillator, or design the MCU with a higher toleration to frequency variation. Overdesigning for high-frequency toleration will severely degrade the system’s performance, and recalibration comes with the price of higher power consumption and complexity. A conceptual block diagram of frequency recalibration is shown in figure 2.

Temperature Supply sensor sensor

Enable Calibration

Frequency Measurement Integrated oscillator

Freq Adjustment

Figure 2: Frequency recalibration system.

It is worthwhile to consider more details about the frequency recalibration because it might be inevitable for some systems that have strict frequency stability specifications. In this case, the importance of frequency stability versus supply voltage becomes even higher.

Temperature can change 1-2 °C at most in a couple of seconds, corresponding to a

3 frequency shift of ~100ppm, while in the same duration, voltage can change by more than

300mV, which leads to a frequency change of ~3000ppm. The recalibration system needs to be turned on very frequently due to the voltage-induced frequency variation, and this leads to a large power penalty because the crystal oscillator is much more power hungry and takes a long time to turn on. Thus, improving the frequency’s voltage stability will allow a less duty-cycled recalibration system and large power saving.

TD I I I Vos1

vramp2 ɸ ɸ S Q ɸ C(T) R Q ɸ vramp1 vref Vos2 C(T) R(T)

Figure 3: Error sources of frequency stability.

Figure 3 shows the block diagram of an RC oscillator where the comparator offset voltage (VOS), comparator delay and logic delay (TD), temperature dependency of resistors and capacitors are explicitly shown to highlight their impact on frequency stability. The

2푉 퐶 oscillator period can be derived as: 푇 = 푠푤푖푛푔 + 2푇 = 2푅퐶 + 2푇 . Based on this 푂푆퐶 퐼 퐷 퐷 equation, we can evaluate how each error source affects the overall period.

Comparator and logic delay (TD):

Delay through the comparator and logic circuit, TD, affects the total period by Δ푇푂푆퐶 =

2Δ푇퐷. The comparator is usually made of an amplifier followed by a Schmitt trigger or

CMOS. Both components are sensitive to temperature and supply variation. Therefore, TD introduces voltage and temperature sensitivities to the oscillator. A common solution is to make TD a very small portion (< 0.5%) [1] of the total period so even if it varies, it will not change the frequency much. However, this requires a very power-hungry comparator, especially in a high-frequency oscillator. A solution will be proposed in the next session.

Offset voltage of the comparator (Vos):

One source of frequency is the offset voltage of the comparator. The offset voltage is a random value, but once the circuit is fabricated, it is deterministic. It is modeled as a voltage source with unknown value at the input of the comparator. The offset voltage will deviate the swing from designed value and affect the frequency. Since the offset voltage is a strong function of temperature, it cannot be fixed by trimming. In fact, the offset voltage is the bottleneck for conventional RC oscillators to achieve high temperature stability and low

(푉 +푉 )∗퐶 swing operation. The offset voltage’s effect on the period is: Δ푇 = 표푠1 표푠2 . A solution 표푠푐 퐼 to address the comparator offset problem is shown in figure 4. In this architecture, only one comparator is used and once the clock phase is changed, the Vref will be shifted to the other side of the input of the comparator. With this design, the comparator offset makes no difference in the overall period [1], and since it only uses one comparator, power consumption is also reduced.

I I I ɸ vref ɸ ɸ ɸ ɸ ɸ vramp2 ɸ C ɸ vramp1

C R

Figure 4: RC oscillator with comparator offset cancellation.

Temperature sensitivity of the RC time constant:

Despite the offset voltage, the time it takes for the Vramp to match Vref is equal to the time constant RC, which contributes most of the period of the oscillation. Usually the resistors in the integrated circuit will have some non-zero temperature coefficient, so this temperature coefficient will translate to the temperature sensitivity of the oscillator. This sensitivity can be mitigated by using a combination of resistors with positive and negative coefficients so that the overall temperature coefficient is near zero [2].

Chapter 3. Proposed RC oscillator Self-Regulation Loop (SRL)

VDD

M6 M4 MP Oscillator core VREG

M1 M2

I1 I2 M3 RREG ɸ ɸ VIR VC1 VC2 IPTAT M5 IREF

IPTAT R ɸ C C ɸ

ɸ ɸ ɸ ɸ VREG = VTH5 + VOV5 + IPTATRREG ɸ ɸ

Figure 5: Proposed architecture of RC oscillator.

The proposed RC oscillator architecture is shown in figure 5. It is composed of an offset-canceling oscillator core and a self-regulation loop (SRL). The oscillator core uses a single comparator whose inputs are reversed at every charging/discharging cycle so that oscillator period, TOSC, is independent of comparator offset [1]. Temperature sensitivity of the RC time constant is reduced by using a metal capacitor and a resistor whose temperature coefficient is minimized by a trimmable combination of resistors with positive and negative temperature coefficients [2]. A low voltage SRL sets output voltage of the regulator (VREG) such that the oscillator operates at its zero-voltage coefficient point with reduced voltage sensitivity. Current reference is implemented using a constant-gm architecture described in section 3.2.

The SRL is composed of a common-source stage (M5/M6) that provides the requisite loop gain and an inverting buffer stage (M3/M4) that improves power supply rejection

(PSR) by coupling supply noise to the gate of the output transistor (MP). The PSR provided

푟 1 by the SRL is approximately equal to: 푃푆푅 ≈ ( 푟푐표 ) × ( ), where the first 푟푟푐표+푟푟푑푠푝 푔푚5(푟푑푠5||푟푑푠6) term denotes open-loop PSR, the second term is the approximate SRL loop gain, and rrco is the impedance looking into the supply node of the oscillator.

In steady-state, output voltage (VREG) is regulated to: 푉푅퐸퐺 = 푉푇퐻5 + 푉푂푉5 + 퐼푃푇퐴푇푅푅퐸퐺, where VTH5 and VOV5 are the threshold and overdrive voltages of M5, respectively. The negative temperature coefficient of VTH5 causes VREG to decrease with temperature, which severely degrades temperature and voltage stability of the oscillator. To mitigate this, VREG is level shifted up by a voltage IPTATRREG that has a positive temperature coefficient, thereby making it nearly independent of temperature. The level shifter also helps setting VREG to the oscillator's zero voltage sensitivity point as described next. The common-source stage

M5/M6 is biased with PTAT current, while the level shifter is biased with a programmable combination of PTAT and temperature-independent current for optimal cancellation of the temperature dependence of VGS5.

3. 1. Zero voltage coefficient point (ZVC)

In addition to the comparator delay variation, TOSC is also affected by channel length modulation of the two current sources (M1/M2), switch imperfections including charge redistribution and clock feedthrough (see figure 6). The impact of these secondary effects can be quantified by expressing oscillation period deviation, ΔTOSC, due to supply variations as: Δ푇푂푆퐶 ≈ 2Δ푇푅퐶 + 2Δ푇퐷 + 2Δ푇푆푊, where ΔTRC, ΔTD, ΔTSW, denote variations in delay due to channel length modulation, comparator delay and switch imperfections, respectively. To quantify the behavior of ΔTRC, we note that VDS1 is held constant at VDD – I1R while VDS2 8 ramps down from VDD to VDD – I2R. Consequently, average current charging the capacitor, I2, is greater than the current, I1, through the resistor. This reduces the time taken to charge the capacitor voltage to the threshold voltage of I1R and changes RC time constant to 푇푅퐶 =

퐼1 1+휆푉̅̅̅퐷푆̅̅̅1̅ 1+휆푉퐷퐷−퐼푅 0.5휆퐼푅 훼RC, where 훼 = ≈ = 퐼푅 ≈ 1 − . This expression shows that TRC has 퐼2 1+휆푉̅̅̅퐷푆̅̅̅2̅ 1+휆푉 − 1+휆푉퐷퐷 퐷퐷 2 a positive voltage coefficient (see figure 6).

VDD

M1 M2 IREF (1) Comparator delay variation, ΔTD I1 I2 (2) Current source channel length Modulation, ΔTCLM R C Reset Logic

(3) Switch imperfections, ΔTSW

Minimum supply ΔTOSC FOSC sensitivity

ΔTSW ΔTD

ΔTCLM

VZVC VDD VZVC VDD

Figure 6: Illustration of ZVC concept.

To illustrate the impact of switch imperfections, we note that when the switch turns on, charge stored in the parasitic capacitance of M2 and M3 at node VC gets shared with capacitor C, which introduces an instantaneous jump in VC and reduces the delay. Because parasitic charge (and therefore the jump) is proportional to supply voltage, VDD, charge sharing causes ΔTSW to have a negative voltage coefficient (see figure 6).

The opposing sensitivities of ΔTRC, ΔTD and ΔTSW are balanced to achieve a zero-voltage coefficient point (VZVC) where oscillation period variation due to the switching delay

9 compensates for the channel length modulation and comparator delay variation as shown in figure 6. Therefore, for minimum supply sensitivity, the oscillator supply voltage must be set to VZVC independent of temperature, which is ensured in the proposed SRL by appropriately setting IPTATRREG. While the amount of cancellation depends on process and temperature, exhaustive simulations indicate that setting VREG equal to VZVC provides at least a factor of 5 additional PSR improvement across all PVT conditions.

3. 2. Building blocks

1:1 M1 M4 M3 M2 ɸ ɸ V+ V- 36:1 M2 M1

R1 M3 M4 M5

(a) (b)

Figure 7: (a) Constant-gm current reference; (b) Comparator.

Current reference:

The schematic of the current reference circuit is shown in figure 7 (a). Equally sized current sources M3/M4 are biased using an error amplifier to improve supply noise immunity. Choosing width of M2 36 times larger than that of M1 results in an output current

5푉푂푉1 equal to , where VOV1 is the overdrive voltage of M1, which is inversely proportional to 6푅

5 the mobility, described by 푉푂푉1 = 푊1 . Consequently, using a temperature- 6휇푛퐶표푥( )푅 퐿1 independent R results in a PTAT output current. On the other hand, temperature-

10 independent output current can be generated by using R with a positive temperature coefficient. The reference current, IREF, used in the oscillator (figure 6) is biased by temperature-independent current reference circuit while PTAT current is used in SRL and the comparator. The constant-gm provided by the PTAT source also helps maintain constant bandwidth of the comparator, thus making its delay constant to the first order.

Comparator:

The schematic of the comparator is shown in figure 7 (b). It is composed of a two-stage amplifier that provides high gain (≈ 50dB), followed by CMOS inverters to generate rail to rail output. The channel lengths of the current sources (M1/M2) were sized large (퐿 = 2μm) to increase output impedance for better supply noise immunity. The bias current in the first and second stages are 1μA and 0.5μA, respectively. Total delay through the comparator is

24ns, which is about 4% of the total period.

Chapter 4. Experiment result

The prototype oscillator was implemented in a standard 65nm CMOS process and the die micro-graph is shown in figure 8. It occupies an active area of 0.12 mm2. It operates from 1.0V supply and consumes 6μW at 1.5MHz output frequency. Current sources in the oscillator core nominally consume 0.4μA each, while the comparator and regulator each consume 1.5μA. The two current references operating from the unregulated supply voltage draw 1μA each.

Figure 8: Die photo.

Output frequency of the unregulated RC oscillator versus its supply voltage at different temperatures is plotted in figure 9. It reveals that VZVC is approximately equal to 0.85mV independent of temperature. Supply sensitivity is measured by sweeping the oscillator supply voltage from 1V to 1.3V and plotting the output frequency deviation as shown in figure 10. Frequency variation is less than ±500ppm at both 30 ̊C and 90 ̊C, which translates to a voltage sensitivity of ±1500ppm/V across the entire temperature range.

The measured regulator output voltage across temperature varied by less than 15mV indicating that the proposed voltage stability improvement is insensitive to temperature variation. The temperature sensitivity plot shown in figure 11 indicates frequency variation is less than ±0.5% over a temperature range of 0 to 100 ̊C, which translates to a sensitivity of ±50ppm/ ̊C. The concaveness of the temperature induced frequency variation typically indicates that the second-order temperature coefficient of the resistor is the dominant source of error. The performance summary and comparison to prior art is shown in table 1.

Compared to the state-of-the-art works, the proposed solution achieves excellent supply noise immunity without degrading temperature sensitivity and power efficiency.

Figure 9: Measured frequency variation versus unregulated supply voltage at two temperatures.

Figure 10: Measured frequency variation versus regulated supply voltage across 4 chips, at two temperatures.

Figure 11: Measured frequency variation versus temperature across 4 chips.

Table 1: Performance summary.

Chapter 5. Summary

A 1.5MHz RC oscillator with high voltage variation immunity using self-regulation and zero voltage coefficient biasing is presented. Experimental results of the prototype oscillator show ±0.15% and ±50ppm/ ̊C with a power consumption of only 6μW. Compared to the state-of-the-art works, the proposed oscillator achieves the best frequency stability with remarkable power efficiency.

References [1] A. Paidimarri, et al., “An RC oscillator with comparator offset cancellation,” in J. Solid- State Circuits, pp. 1866-1877, 2016.

[2] T. Tokairin, et al., “A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme,” IEEE Symp. VLSIC, pp. 16-17, 2012.

[3] A. Savanth, et al., “A 0.68nW/kHz supply independent relaxation oscillator with ±0.49%/V and 96ppm/ ̊C stability,” IEEE ISSCC, pp. 96-97, 2017.

[4] J. Lee, et al., “A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs,” IEEE ISSCC, pp. 106-107, 2015.

[5] J. Koo, et al., “A quadrature relaxation oscillator with a process-induced frequency-error compensation loop,” IEEE ISSCC, pp. 94-95, 2017.