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Place & Route Tutorial #1 NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis Place & Route Tutorial #1 In this tutorial you will use Synopsys IC Compiler (ICC) to place, route, and analyze the timing and wire- length of two simple designs. This tutorial assumes that you have worked through Tutorial #1: Introduction to Simulation and Synthesis on the ECE 520 ASIC Design Tutorials Page and that you know how to simulate, synthesize and analyze timing on basic designs. I. Setup Log in to a Linux machine. Download and unpack the file pr_tut1.tar.gz. This archive contains a directory called ''pr_tut1'' with two subdirectories called “counter” and “xbar”. Each of these directories contains two subdirectories called ''v'' and ''pr'' with files needed to complete this tutorial. We will start with the counter design and move on to the xbar design. Change to the counter/v/synth directory and synthesize the simple ''counter.v'' design with the command “make”. This design is copied from the ECE 520 tutorial #1 mentioned above. When complete, you should have a file called “counter/v/src/gate/counter_final.v”, which will serve as the starting point for this tutorial. II. Initialize the Design 1. Change to the PR directory and Start ICC with the command “make gui”. Look inside the Makefile, and you’ll see that this recipe executes the following commands add synopsys2015 icc_shell -gui 2. Once the ICC Main Window appears, type the command “source import.tcl” at the icc_shell> prompt at the bottom of the window. You may want to open the import.tcl file in a separate window to see what’s inside. If you do, you’ll notice that it’s doing the following: (You should update these details as needed to for your own designs) Sources setup.tcl – The setup.tcl file defines various variables used throughout the design flow. In particular, it sets a variable used in the remainder of the file called modname, which is the module-name, set to “counter” for this tutorial. This file gives the standard-cell netlist that will be placed and routed. Creates the MilkyWay library – The next command creates a library called “work” in the current directory to store all results. This library is in the Synopsys MilkyWay database format and uses a 32nm technology file and standard-cell library. Imports the Verilog Netlist – The Verilog netlist is imported into a cell called “counter_init” (i.e. initialized). To successfully import the file, the path is specified, along with the name of the top-level cell in the Verilog file. Sources the Timing Constraint File - This reads the timing constraint(s) that will be used for the design. The file loaded is almost identical to the “Constrainsts.tcl” file used earlier to synthesize the design with Synopsys Design Compiler. Look in this file and you'll see that it defines the clock port and a 10 ns clock period. NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis 3. At this point, your design should look like the figure below. To make your view look exactly like the one below, you will need to edit the “View Settings”. You can do that by using F8 or by selecting View → Toolbars → View Settings. Then select the check-boxes in the “Vis.” column (i.e. “visible”) for object types Pin and Site Row and then click the “Apply” button. You can zoom in by left-clicking on the zoom-tool and draging a box. Some convenient key-bindings are included below. Button/Key Action Description Select Tool Allows selection of objects in the Layout Window q Query Display the object attributes for the selected object. Selection f Fit Display Zooms the display to fit the design area. z Zoom Tool Selects the Zoom tool + Zoom-in Zooms in the display, 2x. Shift-z or - Zoom-out Zooms out the display, 2x. Arrows Pan Pans the display in direction of arrow. Ctrl-U Ruler Selects the Ruler tool for measuring distance. Clear Rulers Clears all rulers in the view. 4. Now that the design has been loaded, you can analyze the timing of the design. Type the command “report_timing” in the Main Window icc_shell> prompt. This timing report should look identical to the report in Design Compiler. The slack on the critical path is 7.7901 ns. This is pretty good! Our clock period is not set very aggressively for this design. If we reduce the clock period in the constraints.tcl file by more than 7.7901ns, then we will see a negative number here. Compare this to the critical path given in the file ''../v/synth/timing_max_slow_holdfixed_tut1.rpt'', and you'll note that the path and delay are NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis identical. This is no great surprise, since ICC and Design Compiler are using the same timing engine. 5. Lastly, note that all of the output that you see in the Main Window is also appearing in the UNIX shell window where you typed “make gui”. This output is also recorded in the file icc_output.log. We’ll be referring to this file throughout the rest of this tutorial. III. Place & Route the Design Choose Placement → Core Placement and Optimization… to run the Placer. Click OK on the next pop-up to run placement with default options. Once complete, your design should look like the one below. Choose File → Save Design.... In the Save Design dialog box, check the “Show Advanced Options” box and then scroll to the right until you see the “Save As Name” box. Enter the name “counter_placed” and check the “Save As” box to the left of the name. Then click Ok. Once saved, you can open the design with File → Open Design... in the ICC Main Window. Choose Route → Global Route… and click OK on the next pop-up to route with default options. Your routed design should look like the one below. The only difference you should see will be that some vias have been added to connect from one metal layer to another, but no wires have been routed, yet. This is because the Global Route performs only the first part of the routing process. That is, all wires are assigned to Global Routing Cells (GRCs). NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis To perform the next part of the routing process, choose Route → Track Assignment… and click OK on the next pop-up to route with default options. Once complete, your design will look like the one below. You can turn the different routing layers on and off to get an idea which wires are in which layers. To do that, select the “Layers” tab in the view settings as shown below. Then click on the box in the “shape” column and metal-layer row of interest, and click “Apply” to save the view settings. It’s tempting to thing that the route is done, since we can see the wires. But these shapes are only the second step in getting a legal route. At each step, there will be a varying number of short-circuits and other design-rule violations. We can current number by running a geometry check, which is normally NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis done after a “Detail Route”. Choose Route→Verify Route... and click Ok on the pop-up window. When done, you will be able to browse the violations by choosing Verification → Error Browser…, selecting “Detail Route” on the subsequent dialog box, and clicking Ok. The image below shows a short on layer M2 between nets n37 and n45. You should also see the following messages appear in the icc_output.log file: DRC-SUMMARY: @@@@@@@ TOTAL VIOLATIONS = 39 Less than minimum area : 15 Needs fat contact : 2 Same net spacing : 13 Short : 9 Ideally, a completed design will have zero violations. Any violations that cannot be fixed within ICC will need to be fixed manually, using a tool such as Cadence Virtuoso. For now, however, we won’t worry about them, because these violations are likely to be fixed once we perform a Detail Route. One of the main reason for performing a trial route is so that we can get a more accurate idea of delays due to wire parasitic capacitances and resistances. Type the command “report_timing” in the Main Window again, and you will see that the critical-path slack has increased slightly to 8.8331 ns. Look through the icc_output.log file, and you'll see the following messages: NC State University Fall 2016 ECE Department ECE 720 W. Rhett Davis Information: The RC model used is detail route TLU+. (RCEX-015) Information: Start mixed mode parasitic extraction. (RCEX-023) Information: Start rc extraction... Information: Parasitic source is LPE. (RCEX-040) Information: Parasitic mode is RealRC. (RCEX-041) Information: Using virtual shield extraction. (RCEX-081) Information: Extraction mode is MIN_MAX. (RCEX-042) Information: Extraction derate is 125/125/125. (RCEX-043) Information: Coupling capacitances are lumped to ground. (RCEX-044) Information: Start back annotation for parasitic extraction. (RCEX-023) Information: End back annotation for parasitic extraction. (RCEX-023) Information: Start timing update for parasitic extraction. (RCEX-023) Information: End timing update for parasitic extraction. (RCEX-023) Information: End parasitic extraction. (RCEX-023) You will also see the following messages printed out with the timing report, indicating that the parasitcs are being used in the delay calculation: Operating Conditions: ss0p95v125c Library: saed32lvt_ss0p95v125c Parasitic source : LPE Parasitic mode : RealRC Extraction mode : MIN_MAX Extraction derating : 125/125/125 It is important to make note of the kind of extractor that was used for a particular timing report, because it is difficult to tell if a particular design change has had a positive or negative effect, especially if the timing reports were created with different types of extractors.
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