Conformal Equivalence Checker Formal verification technology for fast and accurate bug detection and correction
Cadence® Conformal® Equivalence Checker (EC) makes it possible to verify and debug multimillion–gate designs without using test vectors. It offers the industry’s only complete equivalence checking solution for verifying SoC designs—from RTL to final LVS netlist (SPICE). Conformal EC enables designers to verify the widest variety of circuits, including complex arithmetic logic, datapaths, memories, and custom logic.
Conformal EC
Already proven in thousands of RT tapeouts, Conformal EC is the industry’s most widely supported independent equivalence-checking product. It is Synthesis • ogic equivalence checking production proven on more physical • Dual language support design closure products, advanced Place and Route • Semantic checks synthesis software, ASIC libraries, and • Structural checks IP than any other formal verification technology. Physical Synthesis
Conformal EC is available in three configurations: the L offering delivers ECOs Conformal EC L core equivalence checking technology, the XL offering extends the L capabil- Final ayout E tends equivalence ities with automated checking of checking to datapath and S reference complex datapaths and equivalence Datapath Synthesis SPICE netlist Conformal EC XL checking of the final place-and-route netlist, and the GXL offering extends the L and XL capabilities with transistor Custom Circuit Design E tends equivalence checking circuit analysis for custom designs and to digital custom logic embedded memories. and memories Custom emory Design Conformal EC GXL Engineers can use the GXL offering with custom embedded memories, Figure 1: Conformal EC offers a complete solution, from RTL to final layout, arithmetic blocks, datapaths, standard to drive convergence on design goals and extended libraries, and all other custom and semi-custom digital circuit functions. Circuit styles supported include standard and complex Boolean functions, latches and registers, pass-gate, transmission-gate, tri-state switch logic, pre-charged logic cells, domino logic blocks, and dual-rail. Conformal Equivalence Checker
Benefits
• Exhaustively verifies multi-million–gate ASICs several times faster than traditional gate-level simulations
• Decreases the risk of missing critical bugs with independent verification technology.
• Enables faster, more accurate bug detection and correction throughout the entire design flow
• Extends equivalence checking capability to complex datapaths and closes the RTL-to-layout verification gap (XL configuration)
• Ensures RTL models perform the same functions as the corresponding transistor circuits implemented on silicon (GXL configuration)
Features
Conformal EC L Equivalence checking
During a design’s development, it undergoes numerous iterations prior to Figure 2: Conformal EC has an easy-to-use GUI with extensive final layout, and each step in this process diagnosis and debugging capabilities has the potential to introduce logical bugs. Conformal EC L checks the functional • Graphical debugging via an integrated test vectors. It can handle a wide variety equivalence of different versions of a schematic viewer that shows logic of datapath structures required for design at these various stages and enables values for each error vector highperformance designs: designers to identify and correct errors • Full cross-highlighting between RTL • Automatic flat datapath module as soon as they are introduced, thereby model and circuit verification—Enables easy verification maintaining the initial design intent. without manually specifying boundaries • Automatic error candidate identification or architectures in the flattened netlist, Design flow independence with assigned and weighted automatically verifies merged operators, percentages Conformal EC L provides an independent compares circuitry that has gone through audit of the design process to eliminate the • Logic-cone pruning to focus debugging expression optimization, and automatically risks associated with sharing technologies on relevant information verifies multipliers with standard across design implementation and verifi- architectures and dynamic structures cation products. The tool includes technol- Conformal EC XL ogies developed independently from the • Advanced pipelining check design flow, such as production proven Datapath synthesis verification and diagnosis—Verifies proper implementation of pipelined designs HDL parsing, synthesis, mapping, optimi- Datapath optimization can create designs zation, and datapath algorithms. Using that are difficult to formally verify because • Carry-save verification capability—Allows Conformal EC L ensures that you will catch of complex arithmetic operations. verification of circuits containing carry-save the maximum number of design bugs. Designers have been relying on simulation transformations introduced during Integrated environment to verify datapath blocks, but simulation optimization for sequence of adders, runtimes are exceedingly long and the multipliers, and registers An intuitive GUI provides for setup and results can be incomplete. debugging, allowing you to work more Final circuit verification Conformal EC XL offers a first-of-its-kind productively and quickly pinpoint the Conformal EC XL is the only verification formal solution that exhaustively verifies cause of mismatches: product that enables a complete verifi cation complex datapath blocks without using solution from RTL to final layout, driving
www.cadence.com 2 Conformal Equivalence Checker convergence on original design goals. It functionally compares a SPICE netlist created for LVS or extracted from GDS to the RTL E al n ra on or gate model. This process ensures that L CE C n f r n the circuit on silicon has the same intent n l as the initial design that was verified. Conformal EC Smart setup and diagnosis
Conformal EC XL includes a set of intel- Conformal EC L ligent analysis commands to ease setup and diagnosis. For example, smart setup L investigates the current environment and automatically remedies common setup issues sometimes experienced by new Ga al n G users. In tandem, non-equivalent analysis can be invoked if non-equivalences are encountered, and presents concise root cause information for quicker debug. Figure 3: Conformal EC provides complete verification from RTL to SPICE
Parallel processing functions and their ever-increasing comprehensive and trusted solutions for complexity. Conformal EC GXL provides equivalence checking, timing constraints For larger and complex designs, overall exhaustive logic verification and— since management, asynchronous clock-domain- verification time can be reduced with multiple no testbench is needed—the quality of crossing synchronization checks, functional licenses by running comparison and datapath results is not limited by availability of time ECO analysis and generation, and low-power analysis on many machines or cores simul- or resources to develop comprehensive design verification. taneously. LSF is also supported. tests. Conformal EC GXL generates The Conformal technology family memory-primative models for Verilog Conformal EC GXL consists of Conformal Constraint system simulation and complete logic Designer, Conformal Equivalence function verification of the transistor Custom logic abstraction Checker, Conformal Low Power, circuit design using abstraction and equiv- and Conformal ECO Designer. Conformal EC GXL analyzes digital transistor alence checking. circuits and abstracts an equivalent logical Verilog model. The underlying abstraction • Intuitive graphical interface to generate Platforms algorithms are more powerful than pattern- specific primitives • Linux (32-bit, 64-bit) based solutions. A Verilog gate logic model • Generated primitives are address, word, • Sun Solaris (64-bit) of the abstracted circuit can be used for: and column MUX-configurable • IBM AIX (64-bit) • Equivalence checking • All read-write, read-only, and write-only combinations can be generated • Fault grading—Preserves the circuit Language Support hierarchy and structure for maximum • Generated simulation models have • Verilog (1995, 2001, 2005) debugging efficiency the highest performance and contain • Emulation—Provides accurate built-in assertions for trapping illegal • SystemVerilog emulation models for actual memory use such as address collision • VHDL (87, 93) transistor-level circuits and simultaneous read-write • SPICE (traditional, LVS) • Simulation acceleration—Runs many Conformal Technology times faster than SPICE circuit simulation • EDIF To shorten overall design-cycle times and Memory verification minimize silicon re-spins, designers need • Liberty Traditional and symbolic simulation tools production-proven validation. Conformal • Mixed languages do not scale for verifying today’s memory verification technologies offer the most
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Cadence Services and Support
• Cadence application engineers can answer your technical questions by telephone, email, or internet. They can also provide technical assistance and custom training.
• Cadence-certified instructors teach more than 70 courses and bring their real-world experience into the classroom.
• More than 25 Internet Learning Series (iLS) online courses allow you the flexibility of training at your own computer via the internet.
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• For more information, please visit www.cadence.com/support and www.cadence.com/training for training.
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