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Quartus II Handbook Version 11.0 Volume 3: Verification; Section V

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Quartus II Handbook Version 11.0 Volume 3: Verification; Section V Section V. Formal Verification The Quartus® II software easily interfaces with EDA formal design verification tools such as the Cadence Encounter Conformal and Synopsys Synplify software. In addition, the Quartus II software has built-in support for verifying the logical equivalence between the synthesized netlist from Synopsys Synplify and the post-fit Verilog Quartus Mapped (.vqm) files using Cadence Encounter Conformal software. This section discusses formal verification, how to set-up the Quartus II software to generate the .vqm file and Cadence Encounter Conformal script, and how to compare designs using Cadence Encounter Conformal software. This section includes the following chapter: ■ Chapter 19, Cadence Encounter Conformal Support May 2011 Altera Corporation Quartus II Handbook Version 11.0 Volume 3: Verification V–2 Section V: Formal Verification Quartus II Handbook Version 11.0 Volume 3: Verification May 2011 Altera Corporation 19. Cadence Encounter Conformal Support December 2010 QII53011-10.1.0 QII53011-10.1.0 The Quartus® II software provides formal verification support for Altera® designs through interfaces with a formal verification EDA tool, the Cadence Encounter Conformal Logic Equivalence Check (LEC) software. The two types of formal verification are equivalence checking and model checking. This chapter discusses equivalence checking with the Conformal LEC software. Use the Conformal LEC software to verify the functional equivalence of a post-synthesis Verilog Quartus Mapping (.vqm) netlist file from Synopsys Synplify Pro software, a post-fit Verilog Output File (.vo) from the Quartus II software, or both. You can also use the Conformal LEC software to verify the functional equivalence of the register transfer level (RTL) source code and post-fit .vo file with the Quartus II software when using Quartus II integrated synthesis. These formal verification flows support designs for the Arria® GX, Cyclone®, Cyclone II, Cyclone III, HardCopy® II, Stratix®, Stratix II, Stratix II GX, Stratix III, and Stratix IV device families. This chapter contains the following sections: ■ “Formal Verification Design Flow” on page 19–2 ■ “RTL Coding Guidelines for Quartus II Integrated Synthesis” on page 19–4 ■ “Black Boxes in the Conformal LEC Flow” on page 19–8 ■ “Generating the Post-Fit Netlist Output File and the Conformal LEC Setup Files” on page 19–10 ■ “Understanding the Formal Verification Scripts for Conformal LEC” on page 19–12 ■ “Comparing Designs Using Conformal LEC” on page 19–15 ■ “Known Issues and Limitations” on page 19–16 ■ “Black Box Models” on page 19–18 ■ “Conformal Dofile/Script Example” on page 19–19 Equivalence checking uses mathematical techniques to compare the logical equivalence of two versions of the same design rather than using test vectors to perform simulation. The two compared versions can be post-map design and post-fit design, or RTL design and post-fit design. Equivalence checking greatly shortens the verification cycle of the design. Formal Verification Versus Simulation Formal verification cannot be considered as a replacement for vector-based simulation. Formal verification only complements the existing vector-based simulation techniques to speed up the verification cycle. Vector-based simulation techniques of gate-level designs can take a considerable amount of time. © 2010 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Quartus II Handbook Version 11.0 Volume 3: Verification December 2010 Subscribe 19–2 Chapter 19: Cadence Encounter Conformal Support Formal Verification Design Flow You can use Vector-based simulation techniques to perform the following functions: ■ Verify design functionality ■ Verify timing specifications ■ Debug designs Formal Verification: What You Need to Know If you use formal verification techniques to verify logic equivalence of your design, you can save time by foregoing a comprehensive vector-based simulation of the gate-level design. However, there might be an impact on area and performance during recompilation of your design with the Quartus II software if you choose to use formal verification flow for Conformal LEC software. The area and performance of your design might be affected by the following factors: ■ Hierarchy preservation ■ ROM implementation by logic elements (LEs) ■ Disabled retiming is disabled Refer to “Known Issues and Limitations” on page 19–16 before you consider using the formal verification flow in your design methodology. Formal Verification Design Flow Altera supports formal verification using the Conformal LEC software for the following two synthesis tools: ■ “Quartus II Integrated Synthesis” on page 19–3 ■ “Synplify Pro” on page 19–3 The following sections describe the supported design flows for these synthesis tools. Quartus II Handbook Version 11.0 Volume 3: Verification December 2010 Altera Corporation Chapter 19: Cadence Encounter Conformal Support 19–3 Formal Verification Design Flow Quartus II Integrated Synthesis The design flow for formal verification using the Quartus II integrated synthesis is shown in Figure 19–1. This flow performs equivalency checking for the RTL source code and the post-fit netlist generated by the Quartus II software. The RTL source code can be in Verilog HDL or VHDL format. The post-fit netlist generated by the Quartus II software is always in Verilog HDL format. Figure 19–1. Formal Verification Using Quartus II Integrated Synthesis and the Conformal LEC Software RTL Synthesis Equivalence Checking Formal Verification Encounter Conformal Quartus II Library Software Software Place-and-Route Post-Fit Verilog Output EDA Tool Support for Quartus II Integrated Synthesis The formal verification flow using the Quartus II software and Conformal LEC software supports the following software versions and operating systems: ■ Quartus II software beginning with version 4.2 ■ Cadence Conformal LEC software beginning with version 4.3.5A ■ Solaris and Linux operating systems Synplify Pro The design flow for formal verification using Synplify Pro Synthesis performs equivalency checking for the post-synthesis netlist from Synplify Pro and the post-fit netlist generated by Quartus II software, as shown in Figure 19–2 on page 19–4. December 2010 Altera Corporation Quartus II Handbook Version 11.0 Volume 3: Verification 19–4 Chapter 19: Cadence Encounter Conformal Support RTL Coding Guidelines for Quartus II Integrated Synthesis f For additional information about performing equivalency checking between RTL and post-synthesis netlists generated from Synplify Pro software, refer to the Synplify Pro documentation. Figure 19–2. Formal Verification Flow Using Synplify Pro and the Conformal LEC Software RTL Equivalence Checking/ Synplify Pro Encounter Conformal Synthesized Formal Verification Netlist Library Quartus II Equivalence Checking/ Encounter Conformal P&R Netlist RTL Coding Guidelines for Quartus II Integrated Synthesis The Conformal LEC software can compare the RTL code against the post-fit netlist generated by the Quartus II software. The Conformal LEC software and the Quartus II integrated synthesis parse and compile the RTL description in slightly different ways. The Quartus II software supports some RTL features that the Conformal LEC software does not support and vice versa. The style of the RTL code is of particular concern because neither tool supports some constructs, leading to potential formal verification mismatches; for example, state machine extraction, wherein different encoding mechanisms can result in different structures. Therefore, for successful verification, both tools must interpret the RTL code in the same manner. The following section provides information about recognizing and preventing problems that can arise in the formal verification flow. f For more details about RTL coding styles for Quartus II integrated synthesis, refer to the Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook. 1 Some of the coding guidelines apply to both the Quartus II integrated synthesis and Synplify Pro flow, as indicated in each of the guidelines in the following sections. Synthesis Directives and Attributes Synthesis directives, also known as pragmas, play an important role in successful verification of RTL against the post-fit .vo netlist file from the Quartus II software. Pragmas and trigger keywords that are supported in Quartus II integrated synthesis and the Conformal LEC software are also supported in the formal verification flow. The Quartus II integrated synthesis and Conformal LEC both support the trigger keywords “synthesis” and “synopsys.” When the Quartus II software does not recognize
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