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Application-Specific Integrated Circuits Application-Specific Integrated Circuits (ASICS) S. K. Tewksbury Microelectronic Systems Research Center Dept. of Electrical and Computer Engineering West Virginia University Morgantown, WV 26506 (304)293-6371 May 15, 1996 Contents 1 Introduction 1 2 The Primary Steps of VLSI ASIC Design 3 3 The Increasing Impact of Interconnection Delays on Design 5 4 General Transistor Level Design of CMOS Circuits 6 5 ASIC Technologies 8 5.1 Full Custom Design ......................................... 8 5.2 Standard Cell ASIC Technology ................................... 9 5.3 Gate Array ASIC Technology .................................... 10 5.4 Sea-of-Gates ASIC Technology ................................... 10 5.5 CMOS Circuits using Megacell Elements .............................. 10 5.6 Field Programmable Gate Arrays: Evolving to an ASIC Technology .............. 11 6 Interconnection Performance Modeling 12 7 Clock Distribution 14 8 Power Distribution 15 9 Analog and Mixed-Signal ASICs 16 10 Summary 16 1 Introduction Today’s VLSI CMOS technologies can place and interconnect several million transistors (representing over a million gates) on a single integrated circuit (IC) approximately 1 cm square. Provided with such a vast number of gates, a digital system designer can implement very sophisticated and complex system functions (including full systems) on a single IC. However, ecient design (including optimized performance) of such functions using all these gates is a complex puzzle of immense complexity. If this technology were to have been provided to the world overnight, it is doubtful that designers could in fact make use of this vast amount of logic on an IC. 1 Figure 1: Photomicrograph of the SHARC digital signal processor of Analog Devices, Inc., provided for this chapter by Douglas Garde, Analog Devices, Inc., Norwood, MA. However, this technology instead has evolved over a long period of time (about three decades), starting with only a few gates per IC, with the number of gates per IC doubling consistently about every 18 months (a progression referred to as Moore’s Law), and evolving to the present high gate densities per IC. Projections of this evolution [1] over the next 15 years, as shown in Table 1, promise continued dramatic advances in the amount of logic and memory which will be provided on individual integrated circuits. Paralleling the technology evolution, computer-aided design (CAD) tools [2, 3, 4, 5] have evolved to assist designers of the increasingly complex ICs. With these CAD tools, today’s design teams eectively have an army of very ”experienced” designers embedded in the tools, capable of applying the knowledge gained over the long and steady history of IC evolution. This prior experience captured in CAD tools includes the ability to convert a high level description [6, 7] of a specic function (e.g., ALU, register, control unit, microcontroller, etc.) into an ecient physical implementation of that function. Figure 1 is a photomicrograph of a contemporary, high performance VLSI ASIC circuit, the SHARC digital signal processor from Analog Devices, Inc. This chapter summarizes the design process, the gate-level physical design, and several issues which have become particularly important with today’s VLSI technologies. An important and growing issue is that of testing, including built-in testing, design for testability, and related topics (e.g., [20, 21]). This is a broad Table 1: Prediction of VLSI evolution by Semiconductor Industries Association [1] YEAR 1995 1998 2001 2004 2007 2010 Feature size (m) 0.35 0.25 0.18 0.13 0.10 0.07 DRAM bits/chip 64M 256M 1G 4G 16G 64G ASIC gates/chip 5M 14M 26M 50M 210M 430M Chip size (ASIC) (mm2) 450 660 750 900 1100 1400 Maximum number of wiring levels (logic) 4-5 5 5-6 6 6-7 7-8 On-chip speed (MHz) 300 450 600 800 1000 1100 Chip-to-board speed (MHz) 150 200 250 300 375 475 Desktop supply voltage (V) 3.3 2.5 1.8 1.5 1.2 0.9 Maximum power (Watts), heatsink 80 100 120 140 160 180 Maximum power (Watts), no heatsink 5 7 10 10 10 10 Power (Watts), battery systems 2.5 2,5 3.0 3.5 4.0 4.5 Number of I/O 900 1350 2000 2600 3600 4800 2 Behavioral Specification A Schematic Design HDL Capture Entry Description Verification and/or Simulation B Functional Test Pattern Simulation Generation Map to Physical C Blocks Static Timing Analysis Front End Floorplanning D Design Synthesis Floor Verification and/or E Simulation Planner Gate-Level Simulation Placement and F Routing Back Annotation Direction Forward Annotation Direction Layout vs Placement & Design Rule Verification and/or G Schematic Routing Check Simulation Logic Physical Design H Extraction Completed Back End Golden Verification and/or I Simulation Simulation (a) (b) Figure 2: Representative VLSI design sequences. (a) Simplied but representative sequence. (b) Example design approach from recent trade journal [14] topic, beyond the scope of this chapter. 2 The Primary Steps of VLSI ASIC Design The VLSI IC design process consists of a sequence of well-dened steps [8, 9, 10, 11] related to the denition of the functions to be designed; organization of the circuit blocks implementing these logic functions within the area of the IC; verication and simulation at several stages of design (e.g., behavioral simulation, gate- level simulation, circuit simulation [12, 13], etc.); routing of physical interconnections among the blocks, and nal detailed placement and transistor-level layout of the VLSI circuit. This process can also be used hierarchically to design one of the blocks comprising the overall IC, representing that circuit block in terms of simpler blocks. This establishes the “top-down” hierarchical approach, extendible to successively lower level elements of the overall design. These general steps are illustrated in Figure 2a, roughly showing the basic steps taken. A representative example [14] of a contemporary design approach is illustrated in Figure 2b. Design approaches are continually changing and Figure 2b is merely one of several current design sequences. Below, we summarize the general steps highlighted in Figure 2a. 3 A(s) A(b) c1 c2 D(p) A(f) D(f) A(p) B(s) c3 c4 B(b) B(f) C(f) C(s) C(b) E(p) c5 c6 E(f) D(s) D(b) C(p) B(p) E(s) E(b) (a) (b) (c) (d) Figure 3: Circuit stages of design. (a) Initial specication (e.g., HDL, schematic, etc.) of ASIC function in terms of functions, with the next lower level description of function C illustrated. (b) Estimated size of physical blocks implementing functions. (c) Floorplanning to organize blocks on IC. (d) Placement and routing of interconnections among blocks. A. Behavioral Specication of Function: The behavioral specication is essentially a description of the function expected to be performed by the IC. The design can be represented by schematic capture, with the designer representing the design using block diagrams. High-level description languages (HDLs) such as VHDL [15, 16, 17] and Verilog [18] are increasingly used to provide a detailed specication of the function in a manner which is largely independent of the physical design of the function. VHDL and Verilog are “hardware description languages,” representing designs from a variety of viewpoints including behavioral descriptions, structural descriptions, and logical descriptions. Figure 3a illustrates the specication of the overall function in terms of subfunctions (A(s), B(s), ..., E(s)) as well as expansion of one subfunction (C(s)) into still simpler functions (c1, c2, c3, ..., c6). B. Verication of Function’s Behavior: It is important to verify that the behavior specication of today’s complex ICs properly represents the behavior desired. In the case of HDL languages, there may be software “debugging” of the “program” until the desired behavior is obtained, much as programming languages need to be debugged until correct operation is obtained. Early verication is important since any errors in the specication of the function will lead to an IC which is faulty due to the design, rather than to physical defects. C. Mapping of Logical Function into Physical Blocks: Next, the logical functions (e.g., A(s), B(s), ..., E(s) in Figure 3a) are converted into physical circuit blocks (e.g., blocks A(b), B(b), ..., E(b) in Figure 3b). Each physical block represents a logic function as a set of interconnected gates. Although details of the physical layout are not known at this point, the estimated area and aspect ratio (ratio of height to width) of each circuit block is needed to organize these blocks within the area of the IC.. D. Floorplanning: Next, the individual circuit blocks must be compactly arranged to t within a minimum area. Floorplanning establishes this organization, as illustrated in Figure 3c. At this stage, routing of interconnections among blocks has not been performed, perhaps requiring modications to the oorplan after routing. During oorplanning, the design of a logic function in terms of a block function can be modied to achieve shapes which better match the available IC area. For example, the block E(b) in Figure 3b has been redesigned to provide a dierent geometrical shape for block E(f) in the oorplan in Figure 3c. E. Verication/Simulation of Function’s Performance: Given the oorplan, it is possible to estimate the average length of interconnections among the blocks (with the actual length not known until after 4 interconnection routing in step F below. Signal timing throughout the IC are estimated, allowing verication that the various circuit blocks interact within timing margins. F. Placement and Routing: When an acceptable oorplan has been established, the next step is to complete the routing of interconnections among the various blocks of the design. As interconnections are routed, the overall IC area expands to provide the area for the wiring, with the possibility that the original oorplan (which ignored interconnections) is not optimal.
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